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Renesas mPD98431 User Manual

Renesas mPD98431 User Manual

10/100 mbps ethernet controller
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On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
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Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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April 1
, 2010
Renesas Electronics Corporation

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Summary of Contents for Renesas mPD98431

  • Page 1 On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding.
  • Page 2 Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific”...
  • Page 3 User’s Manual µ µ µ µ PD98431 10/100 Mbps Ethernet Controller Document No. S14054EJ4V0UM00 (4th edition) Date Published July 2001 NS CP(K) © 1999 Printed in Japan...
  • Page 4 [MEMO] User’s Manual S14054EJ4V0UM...
  • Page 5 NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred.
  • Page 6 • The information in this document is current as of July 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country.
  • Page 7 Major Revisions in This Edition Page Description p.17 Modification of caution in CHAPTER 2 (1) Register interface HCLK. Modification of caution in CHAPTER 2 (2) FIFO interface FCLK. p.23 Modification of description in CHAPTER 2 (4) JTAG pins TRST#. p.29 Addition and modification of description in 3.4.1 (2) Appending CRC.
  • Page 8 INTRODUCTION Target Users This manual is intended for user engineers who wish to understand the functions of the µ PD98431, and design and develop application systems using it. This manual explains the hardware functions of the µ PD98431 in the following Purpose organization.

  • Page 9: Table Of Contents

    CONTENTS CHAPTER 1 GENERAL........................11 1.1 Features ..........................11 1.2 Ordering Information......................11 1.3 Pin Configuration....................... 12 1.4 Internal Block Diagram...................... 15 1.5 System Configuration Example..................15 CHAPTER 2 PIN FUNCTIONS ......................16 CHAPTER 3 FUNCTIONAL DESCRIPTION ................... 25 3.1 System Configuration ....................... 25 3.2 Function Blocks.........................
  • Page 10 3.8.3 Connecting µ PD98431 MII output signal pins.................56 3.8.4 10 Mbps serial interface......................56 3.9 Flow Control ........................56 3.9.1 Receiving control frame ......................56 3.9.2 Flow control pause timer......................57 3.9.3 Transmitting pause control frame ...................57 3.10 Back Pressure ........................57 3.11 Operation for VLAN Frames.................... 57 3.11.1 Detecting VLAN frames ......................57 3.11.2 Receiving VLAN frames ......................58 3.11.3 Transmitting VLAN frames ....................58...
  • Page 11 LIST OF FIGURES Figure No. Title Page Example of System Configuration Using µ PD98431 ................µ PD98431 Functional Block Diagram....................Ethernet/IEEE802.3 Frame Structure ....................VLAN Frame Structure .......................... FIFO Interface Write Timing ........................Timing for Changing Transmit Data Write Port Using TXFPT[2:0] ............FIFO Interface Read Timing ........................
  • Page 12 LIST OF TABLES Table No. Title Page TXFDQ Pins and Transmit Data Attributes (32-Bit Dual Bus)..............FDQ Pins and Transmit Data Attributes (64-Bit Single Bus)..............RXFDQ Pin and Receive Data Attribute (32-Bit Dual Bus) ..............FDQ Pin and Receive Data Attribute (64-Bit Single Bus) ..............CLKS Bit of MIIC Register and Frequency of HCLK ................

  • Page 13: Chapter 1 General

    CHAPTER 1 GENERAL The µ PD98431 is a 10/100 Mbps Ethernet controller having eight Media Access Control (MAC) ports conforming to IEEE 802.3 and IEEE 802.3u. Its main features are as follows: 1.1 Features • Eight 10/100 Mbps Ethernet MAC ports conforming to IEEE 802.3 and IEEE 802.3u •...

  • Page 14: Pin Configuration

    CHAPTER 1 GENERAL 1.3 Pin Configuration µ PD98431 (352-PIN PLASTIC BGA) TOP VIEW Index mark µ PD98431 (352-PIN PLASTIC BGA) BOTTOM VIEW Index mark User’s Manual S14054EJ4V0UM...
  • Page 15 CHAPTER 1 GENERAL (1/2) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1(A1) TXFD30/FD62 51(AF26) 101(B2) TXFD27/FD59 151(AA25) 2(B1) TXFD29/FD61 52(AE26) 102(C2) TXFD28/FD60 152(Y25) 3(C1) TXFD26/FD58 53(AD26) 103(D2) TXFD24/FD56 153(W25) 4(D1) TXFD23/FD55 54(AC26) 104(E2) TXFD21/FD53...
  • Page 16 CHAPTER 1 GENERAL (2/2) Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 201(L3) TXFD3/FD35 239(Y24) 277(D4) 315(AC23) 202(M3) TXFD2/FD34 240(W24) 278(E4) 316(AB23) 203(N3) RXFDQ0/FDQ0 241(V24) 279(F4) 317(AA23) 204(P3) RXFDQ3/FDQ3 242(U24) 280(G4) 318(Y23) 205(R3) RXFD25/FD25 243(T24)

  • Page 17: Internal Block Diagram

    CHAPTER 1 GENERAL 1.4 Internal Block Diagram PORT #7 MII/10M serial × 8 PORT #6 PORT #5 PORT #4 · PORT #3 · PORT #2 · PORT #1 · FIFO PORT #0 FIFO DATA · DATA BUS Common TX-FIFO 10/100M interface RX-FIFO Register / statistics counter...

  • Page 18: Chapter 2 Pin Functions

    CHAPTER 2 PIN FUNCTIONS (1) Register interface (1/2) Pin Name Pin No. Function Chip select. When this signal is low, the internal registers of the chip can be accessed. Host read/write. This pin is used by the host system to access the register bus. When a high level is input to this pin, the register bus is accessed for read.
  • Page 19 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Pin No. Function HCLK Register interface clock. This pin inputs a synchronization clock used to access a register. The maximum frequency of the input clock is 66 MHz. Caution Make sure that the frequency of HCLK is always higher than the frequencies of RXCLK and TXCLK.
  • Page 20 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Pin No. Function RXFPT[2:0] 63 to 65 Receive port number. 3-state These signals indicate a port number from which receive data is output when the receive FIFO is accessed for read. The relation between RXFPT[2:0] and a port number is as follows: Port 0 →...
  • Page 21 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Pin No. Function RXFDQ[3:0]/ 204, 12, 111, 203 O / O/I, Receive data attribute/FIFO bus attribute. FDQ[3:0] 3-state These signals indicate the attribute of data on the FIFO bus. The functions of these signals differ as follows depending on the bus mode: (1) 32-bit dual bus mode These signals function as RXFDQ[3:0] and output the attribute of the receive data output onto RXFD[31:0] when the FIFO bus is accessed by...
  • Page 22 CHAPTER 2 PIN FUNCTIONS (3) MII (Media Independent Interface) (1/4) Pin Name Pin No. Function TXCLK[7:0] 230, 137, 222, 29, MII transmit clock. 190, 92, 179, 174 These pins input the transmit clock (duty: 50%) necessary for outputting data to the PHY device connected to each port. Transmit data from each port, TXD7[3:0] through TXD0[3:0], and TXEN[7:0] that indicates that the transmit data on TXD is valid are output to each port in synchronization with this clock.
  • Page 23 CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name Pin No. Function TXD6[3:0] 135, 38 to 40 MII transmit data (port 6). These pins output transmit data to the PHY device connected to port 6. In the MII mode, transmit data of nibble width (4 bits wide) is output at the rising edge of TXCLK6.
  • Page 24 CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name Pin No. Function RXD3[3:0] 98, 275, 276, 192 MII receive data (port 3). These pins input data received from the PHY device connected to port 3. In the MII mode, receive data of nibble width (4 bits wide) is input at the rising edge of RXCLK3.
  • Page 25 CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name Pin No. Function RXER[7:0] 46, 41, 221, 216, MII receive error. 274, 185, 86, 81 These are input signals to detect errors occurring at each port of the PHY device during reception. Fix RXER of an unused port to the low level. MII management data clock.
  • Page 26 CHAPTER 2 PIN FUNCTIONS (5) Test pins and power pins Pin Name Pin No. Function TEST 234, 233, 170, Test pins. 146, 100, 25 These pins are used to test the device. Always fix these pins to low. 279, 283, 285, –...

  • Page 27: Chapter 3 Functional Description

    CHAPTER 3 FUNCTIONAL DESCRIPTION 3.1 System Configuration The µ PD98431 is an 8-port, 10/100 Mbps Ethernet MAC (Media Access Control) having many modes and features. This device has been developed for network devices requiring multiple ports such as LAN switches and rooters.

  • Page 28: Function Blocks

    CHAPTER 3 FUNCTIONAL DESCRIPTION 3.2 Function Blocks The µ PD98431 has an MAC module, PCS module, SAL module, STAT module, and FIFOs for each port. In addition, it also has common modules such as a FIFO bus module, MII management module, and register bus module (refer to Figure 3-2).

  • Page 29: Pcs Module

    CHAPTER 3 FUNCTIONAL DESCRIPTION 3.2.2 PCS module The PCS module implements the Physical Coding Sublayer function that is used to connect a 10 Mbps serial interface. This module is connected to the MAC module at the system side. At the network side of the PCS module, a PHY device supporting MII or 10BASE-T transceiver can be connected.

  • Page 30: Operating Clock

    CHAPTER 3 FUNCTIONAL DESCRIPTION 3.2.9 Operating clock The µ PD98431 requires four operating clocks: transmit clock and receive clock provided by a PHY device, a clock for register access, and a clock to transfer data with the FIFO bus. The transmission block of the MAC module reads transmit data from the transmit FIFO in synchronization with the transmit clock input from the PHY device, generates a transmit frame, and outputs it to the PHY device.

  • Page 31: Transmission Operation

    CHAPTER 3 FUNCTIONAL DESCRIPTION (6) Frame check sequence The frame check sequence field is used to write 32-bit CRC (Cyclic Redundancy Check) to check transfer data. A VLAN frame is slightly different from the normal frame in structure. In this frame, a 4-byte VLAN header is inserted immediately after the source address field.

  • Page 32: Starting Packet Transmission

    CHAPTER 3 FUNCTIONAL DESCRIPTION (3) Appending PAD If the data length of one packet written to the transmit FIFO is less than the minimum frame length of 64 bytes (68 bytes in the case of a VLAN frame), the µ PD98431 automatically appends PAD to extend the data length to the minimum frame length.

  • Page 33: Collision And Retransmission

    CHAPTER 3 FUNCTIONAL DESCRIPTION (2) Non-back-to-back IPG The non-back-to-back IPG set by the IPGR register is used to start outputting a transmit data stream to the PHY device after transmission by another station has been completed and the IPG time has elapsed. The non-back- to-back IPG consists of two portions.

  • Page 34: Reception Operation

    CHAPTER 3 FUNCTIONAL DESCRIPTION (3) Occurrence of late collision If the number of collision windows exceeds the collision window set by the LCOL field of the CLRT register, it is assumed as a late collision and transmission is aborted. If a late collision occurs, the LCOL bit of the TSVREG1 register is set to 1.

  • Page 35: Crc Check

    CHAPTER 3 FUNCTIONAL DESCRIPTION 3.5.3 CRC check Each port of the µ PD98431 automatically calculates a 4-byte frame check sequence (FCS) from the receive packet data and compares it with the CRC data suffixed to the receive packet. The result of comparison is reported to the host system as status information.

  • Page 36: Receive Fifo Overflow

    CHAPTER 3 FUNCTIONAL DESCRIPTION (3) Filtering broadcast address The broadcast packet is stored in the receive FIFO when the ABC bit of the AFR register is set to 1. (4) Promiscuous mode The promiscuous mode is set when the PRO bit of the AFR register is set to 1, and the packets of all address types are stored in the receive FIFO.
  • Page 37 CHAPTER 3 FUNCTIONAL DESCRIPTION (1) Transmit FIFO bus interface operation Figure 3-5. FIFO Interface Write Timing (a) Example in 32-bit dual bus mode FCLK TXFEN# TXFBA[N] TXFDQ[3] TXFDQ[2] TXFDQ[1] TXFDQ[0] TXFPT[2:0] Port N 1st word 2nd word 3rd word 4th word n−2 th word n−1 th word n th word...
  • Page 38 CHAPTER 3 FUNCTIONAL DESCRIPTION In the 32-bit dual bus mode, writing data to the transmit FIFO is enabled by making the TXFEN# signal low. In the 64-bit single bus mode, the FEN# and FRW signals are made low. When these signals are asserted, the TXFBAn signal function of all the ports is enabled. Each port makes the TXFBAn signal high if the data stored in the transmit FIFO does not exceed the value set by the TFDMH field of the TFIC register.
  • Page 39 CHAPTER 3 FUNCTIONAL DESCRIPTION Table 3-2. FDQ Pins and Transmit Data Attributes (64-Bit Single Bus) FDQ pins Data Attribute Valid Data Byte Position Little Endian Big Endian Idle – – Data start FD[63:0] FD[63:0] Intermediate data FD[63:0] FD[63:0] Data start (with CRC appended) FD[63:0] FD[63:0] ×...
  • Page 40 CHAPTER 3 FUNCTIONAL DESCRIPTION Figure 3-6. Timing for Changing Transmit Data Write Port Using TXFPT[2:0] (a) Example in 32-bit dual bus mode FCLK TXFEN# TXFBA[M] TXFBA[N] TXFDQ[3] TXFDQ[2] TXFDQ[1] TXFDQ[0] TXFPT[2:0] Port M Port N 1st word 2nd word 3rd word 4th word 1st word 2nd word...
  • Page 41 CHAPTER 3 FUNCTIONAL DESCRIPTION If a cause that aborts transmission of a packet (such as excessive collision or excessive defer) occurs while data is written to the transmit FIFO, the transmit packet data that has already been accumulated in the transmit FIFO is cleared.
  • Page 42 CHAPTER 3 FUNCTIONAL DESCRIPTION (2) Receive FIFO bus interface operation Figure 3-7. FIFO Interface Read Timing (a) Example in 32-bit dual bus mode FCLK RXFEN# RXFA RXFDQ[3] RXFDQ[2] RXFDQ[1] RXFDQ[0] RXFPT[2:0] Port N 1st Dword n−1 th n th RXFD[31:0] 32 bits Dword Dword...
  • Page 43 CHAPTER 3 FUNCTIONAL DESCRIPTION The µ PD98431 starts data transfer to the host system after reception from the network side has been completed and one packet of data has been completely stored in the receive FIFO. Data is read from the receive FIFO in the following procedure: (a) Reading from receive FIFO Reading data from the receive FIFO is enabled by making the RXFEN# signal low in the 32-bit dual bus...
  • Page 44 CHAPTER 3 FUNCTIONAL DESCRIPTION Table 3-4. FDQ Pin and Receive Data Attribute (64-Bit Single Bus) FDQ Pin Data Attribute Valid Data Byte Position Little Endian Big Endian Idle – – Data start FD[63:0] FD[63:0] Intermediate data FD[63:0] FD[63:0] Reserved FD[63:0] FD[63:0] Status information (first) FD[31:0]...
  • Page 45 CHAPTER 3 FUNCTIONAL DESCRIPTION Figure 3-8. Timing for Changing Port After Completion of Received Data Read (1/2) (a) Example in 32-bit dual bus mode FCLK RXFEN# RXFA RXFDQ[3] RXFDQ[2] RXFDQ[1] RXFDQ[0] RXFPT[2:0] Port M Port N RXFD[31:0] n−3 th n−2 th n−1 th n th 1st Dword...
  • Page 46 CHAPTER 3 FUNCTIONAL DESCRIPTION Figure 3-8. Timing for Changing Port After Completion of Received Data Read (2/2) (b) Example in 64-bit single bus mode FCLK FEN# RXFA FDQ[3] FDQ[2] FDQ[1] FDQ[0] RXFPT[2:0] Port M Port N n−3 th n−2 th n−1 th n th FD[63:0]...
  • Page 47 CHAPTER 3 FUNCTIONAL DESCRIPTION (b) SKIP signal The port number of the receive FIFO whose data is read through the FIFO bus is instructed by the µ PD98431. By inputting the SKIP signal when the RXFA signal goes high after reading the receive FIFO has been enabled or while receive data is being read by means of burst transfer, the host system can read being a port other than the one specified by the µ...
  • Page 48 CHAPTER 3 FUNCTIONAL DESCRIPTION Figure 3-9. Timing for Changing Port to Be Read Using SKIP Signal (Before Port Is Read) (a) Example in 32-bit dual bus mode FCLK RXFEN# RXFA RXFDQ[3] RXFDQ[2] RXFDQ[1] RXFDQ[0] RXFPT[2:0] Port M Port N RXFD[31:0] 1st Dword 1st Dword Dword...
  • Page 49 CHAPTER 3 FUNCTIONAL DESCRIPTION Figure 3-10 shows a timing example of changing the port by inputting the SKIP signal while the port is read. In this case, the new port is selected two clocks of FCLK after the SKIP signal has been detected. The µ...
  • Page 50 CHAPTER 3 FUNCTIONAL DESCRIPTION Figure 3-10. Timing for Changing Port to Be Read Using SKIP Signal (While Port Is Read) (1/2) (a) Example in 32-bit dual bus mode (if the next port is not the port skipped) FCLK RXFEN# RXFA RXFDQ[3] RXFDQ[2] RXFDQ[1]...
  • Page 51 CHAPTER 3 FUNCTIONAL DESCRIPTION Figure 3-10. Timing for Changing Port to Be Read Using SKIP Signal (While Port Is Read) (2/2) (c) Example in 64-bit single bus mode (if the next port is not the port skipped) FCLK FEN# RXFA FDQ[3] FDQ[2] FDQ[1]...
  • Page 52 CHAPTER 3 FUNCTIONAL DESCRIPTION (c) Appending status information The µ PD98431 can append the status information of a packet to the receive data stream that is read from the FIFO bus. When the APSS bit of the MACC3 register is set to 1, the status information on the packet to be read is prefixed to the receive data stream.
  • Page 53 CHAPTER 3 FUNCTIONAL DESCRIPTION Figure 3-11. Timing for Changing FIFO Bus Read/Write in 64-Bit Single Bus Mode (1/2) (a) Example of timing for changing write cycle to read cycle FCLK FEN# TXFBA[N] RXFA FDQ[3] FDQ[2] FDQ[1] FDQ[0] Port N Port N RXFPT[2:0] TXFPT[2:0] Port N...

  • Page 54: Register Bus Interface

    CHAPTER 3 FUNCTIONAL DESCRIPTION Figure 3-11. Timing for Changing FIFO Bus Read/Write in 64-Bit Single Bus Mode (2/2) (b) Example of timing for changing read cycle to write cycle FCLK FEN# TXFBA[N] RXFA FDQ[3] FDQ[2] FDQ[1] FDQ[0] RXFPT[2:0] Port N Port M TXFPT[2:0] Port N...
  • Page 55 CHAPTER 3 FUNCTIONAL DESCRIPTION (1) Controlling reading/writing registers To read an internal register of the µ PD98431, the host system sets the address of the register to be read in A[10:0], and makes the RW signal high and the CS# signal low. The µ PD98431 recognizes read access by the host system by checking the statuses of the RW and CS# signals.

  • Page 56: Network Interface

    CHAPTER 3 FUNCTIONAL DESCRIPTION (3) Interrupt servicing If an interrupt occurs, the µ PD98431 makes the INT# signal low to report to the host system. The sources of interrupts are as follows: • Transmit packet status information indicated by TSVREG1 register •...
  • Page 57 CHAPTER 3 FUNCTIONAL DESCRIPTION Table 3-5. CLKS Bit of MIIC Register and Frequency of HCLK CLKS Bit of MIIC Frequency Range of HCLK Input Bit 3 Bit 2 Not used 33 MHz MAX 50 MHz MAX 66 MHz MAX The MDC is output only when a management frame is transmitted or received. (2) MII management frame data Figure 3-13 shows the MII management frame structure.

  • Page 58: Connecting Μ Pd98431 Mii Output Signal Pins

    CHAPTER 3 FUNCTIONAL DESCRIPTION 3.8.3 Connecting µ µ µ µ PD98431 MII output signal pins To connect the MII output signals (TXD, TXEN, TXER, MDC, MDIO) to a PHY device, connect a series resistor of 18 Ω to 27 Ω to each MII output signal as shown in Figure 3-14, to make the driving capability of the MII output buffer conform to the IEEE802.3u standard.

  • Page 59: Flow Control Pause Timer

    CHAPTER 3 FUNCTIONAL DESCRIPTION 3.9.2 Flow control pause timer The flow control pause timer is a 16-bit timer and stores the pause timer value in the received pause control frame. If the pause timer value of the pause control frame is not 0, it indicates that a new frame should not be transmitted.

  • Page 60: Receiving Vlan Frames

    CHAPTER 3 FUNCTIONAL DESCRIPTION 3.11.2 Receiving VLAN frames If the value of the TPID field in a receive packet coincides with the value of the VLTP register, the VLAN bit of the RSVREG register is set to 1. At this time, judgment related to the receive frame size is made based on MAX: 1522 bytes, MIN: 64 bytes.
  • Page 61 CHAPTER 3 FUNCTIONAL DESCRIPTION Figure 3-15. Output of MII Data to Mirror Port (1) Transmit MII data mirror port output (2) Receive MII data mirror port output µ µ PD98431 PD98431 TXCLK TXCLK TXD[3:0] TXD[3:0] TXEN TXEN TXER TXER [10/100M MAC] [10/100M MAC] Port 0 to 3 Port 0 to 3...

  • Page 62: Low-Power Mode

    CHAPTER 3 FUNCTIONAL DESCRIPTION Table 3-7. Setting of Mirror Port 4 Transmission/ Mirror Port Port Selection Reception Selection Mirror Port 4 MII Output [P4EN = 1] MP4[1:0] T/R4 Port 4 Port 4 MII receive data Port 4 MII transmit data Port 5 MII receive data Port 5 MII transmit data Port 6 MII receive data...

  • Page 63: Notes On Using Μ Μ Μ Μ Pd98431

    CHAPTER 3 FUNCTIONAL DESCRIPTION 3.16 Notes on Using µ µ µ µ PD98431 (1) Connection with PHY device If the µ PD98431 is connected to the PHY device of some manufacturers, a write access is not correctly completed when MII management access is made, and the data is not correctly written to the PHY register. This phenomenon has reportedly occurred with the following product: •...
  • Page 64 CHAPTER 3 FUNCTIONAL DESCRIPTION <3> Read data remaining in receive FIFO. Read the packet data remaining in the receive FIFO. If a packet completely accumulated in the receive FIFO exists when reception is stopped, that packet can be read. The packet being received cannot be read. It is not necessary to read the remaining packet if it is to be discarded.

  • Page 65: Chapter 4 Register Description

    CHAPTER 4 REGISTER DESCRIPTION 4.1 Control Register Map (1) Port control register map (1/2) Register Address Name Function Default A[7:0] MACC1 MAC configuration register 1 00000800H MACC2 MAC configuration register 2 00000000H IPGT Back-to-back IPG register 00000013H IPGR Non-back-to-back IPG register 00000E13H CLRT Collision register...
  • Page 66 CHAPTER 4 REGISTER DESCRIPTION (2/2) Register Address Name Function Default A[7:0] 39H to 4BH – Reserved – – CAM1 CARRY register 1 mask register 00000000H CAM2 CARRY register 2 mask register 00000000H 4EH to 4FH – Reserved – – 50H to 81H –...

  • Page 67: Port Setting Registers

    CHAPTER 4 REGISTER DESCRIPTION 4.2 Port Setting Registers The port setting register is used to define the operation of each port or check the status of the port. To access the register of each port, input a port number to A[10:8] of the address bus A[10:0], and the address of the register to A[7:0].
  • Page 68 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default PADEN PAD append If this bit is set to 1, padding is performed if the packet length is less than 64 bytes (68 bytes in the case of a VLAN frame). If this bit is 1, the µ PD98431 automatically appends CRC regardless of the specification by the TXFDQ signal or setting of the CRCEN bit.
  • Page 69 CHAPTER 4 REGISTER DESCRIPTION MACC2 - MAC configuration register 2 (register address A[7:0] = 01H) R/W Reserved Reserved MCRST RFRST TFRST Reserved BPNB Reserved Name Function Default 31:11 – Reserved. Write 0 to these bits. – MCRST MAC control block software reset. When this bit is set to 1, software reset is executed.
  • Page 70 CHAPTER 4 REGISTER DESCRIPTION IPGT - Back-to-back IPG register (register address A[7:0] = 02H) R/W Reserved Reserved IPGT Name Function Default 31:7 – Reserved. Write 0 to these bits. – IPGT IPG for back-to-back. These bit set a back-to-back IPG by using the following expression: IPG = (5 + IPGT) ×...
  • Page 71 CHAPTER 4 REGISTER DESCRIPTION CLRT - Collision register (register address A[7:0] = 04H) R/W Reserved Reserved LCOL Reserved RETRY Name Function Default 31:14 – Reserved. Write 0 to these bits. – 13:8 LCOL Collision window. This field sets a collision window width by using the following expression: Collision window width = (LCOL + 8) ×...
  • Page 72 CHAPTER 4 REGISTER DESCRIPTION LSA1 - Station address register 1 (register address A[7:0] = 15H) R/W Reserved SA[15:0] Name Function Default 31:16 – Reserved. Write 0 to these bits. 15:0 LSA1 Station address SA[47:32]. SA[47:0] are used for comparison of a source address when a pause control frame is assembled and a destination address when address filtering is used.
  • Page 73 CHAPTER 4 REGISTER DESCRIPTION VLTP - VLAN type register (register address A[7:0] = 19H) R/W Reserved VLTP[15:0] Name Function Default 31:16 – Reserved. Write 0 to these bits. – 15:0 VLTP VLAN type. This field specifies a VLAN type. Reception : The value of this field and the value of the TPID field of the receive frame are compared to detect a VLAN frame.
  • Page 74 CHAPTER 4 REGISTER DESCRIPTION MCMD - MII command register (register address A[7:0] = 25H) Write only Reserved Reserved RSTAT Name Function Default 31:1 – Reserved. Write 0 to these bits. – RSTAT MII management read. When this bit is set to 1, read access by the MII management interface is executed.
  • Page 75 CHAPTER 4 REGISTER DESCRIPTION MWTD - MII write data register (register address A[7:0] = 27H) R/W Reserved CTLD[15:0] Name Function Default 31:16 – Reserved. Write 0 to these bits. – 15:0 CTLD MII write data. This is a write data field used for write access by the MII management interface.
  • Page 76 CHAPTER 4 REGISTER DESCRIPTION AFR - Address filter register (register address A[7:0] = 32H) R/W Reserved Reserved Name Function Default 31:4 – Reserved. Write 0 to these bits. – Promiscuous mode. In this mode, all packets are accepted. Multicast reception. In this mode, all multicast packets are accepted.
  • Page 77 CHAPTER 4 REGISTER DESCRIPTION CAR1 - CARRY register 1 (register address A[7:0] = 37H) R/W Reserved C1VT C1UT C1BT C1MT C1PT C1TB C1MX C11K C1FE C1TE C1OT C1SF C1BR C1MR C1PR C1RB This register indicates that a statistics counter has overflowed. Each bit of this register corresponds to a statistics counter.
  • Page 78 CHAPTER 4 REGISTER DESCRIPTION CAR2 - CARRY register 2 (register address A[7:0] = 38H) R/W C2DV Reserved C2IM C2CS C2NC C2XC C2LC C2MC C2SC C2XC C2DF C2XF C2TE C2JB C2FG C2OV C2UN C2FC C2CD C2FO C2AL C2UO C2PF C2CF C2RE This register indicates that a statistics counter has overflowed.
  • Page 79 CHAPTER 4 REGISTER DESCRIPTION CAM1 - CARRY register 1 mask register (register address A[7:0] = 4CH) R/W Reserved M1VT M1UT M1BT M1MT M1PT M1TB M1MX M11K M1FE M1TF M1OT M1SF M1BR M1MR M1PR M1RB This register masks the INT# signal that is generated when a bit of the CAR1 register is set to 1. When a bit of this register is set to 1, the corresponding bit of the CAR1 register is unmasked.
  • Page 80 CHAPTER 4 REGISTER DESCRIPTION CAM2 - CARRY register 2 mask register (register address A[7:0] = 4DH) R/W M2DV Reserved M2IM M2CS M2NC M2XC M2LC M2MC M2SC M2XD M2DF M2XF M2TE M2JB M2FG M2OV M2UN M2FC M2CD M2FO M2AL M2UO M2PF M2CF M2RE Name...
  • Page 81 CHAPTER 4 REGISTER DESCRIPTION MACC3 - MAC configuration register 3 (register address A[7:0] = 90H) R/W PTIME[15:0] Reserved APSE APSS BUSMODE BACKPE FLWCNT TXFFLH RXFLH Name Function Default 31:16 PTIME Pause timer value. FFFFH The value of this field is used as a pause timer value when the µ PD98431 generates a pause control frame.
  • Page 82 CHAPTER 4 REGISTER DESCRIPTION TIMR - Transmission interrupt mask register (register address A[7:0] = 91H) R/W Reserved ITFOV ITFUN ITWMH ICSE ITBP ITPP ITPCF ITCFR ITGNT ILCOL IECOL ITEDFR ITDFR ITBRO ITMUL ITDONE ITFLOR ITFLER ITCRCE This register masks occurrence of the INT# signal due to each cause. When each bit of this register is set to 1, the mask is cleared.
  • Page 83 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default ITDFR Transmission defer. When this bit is 0, the interrupt of the corresponding bit of the TSVREG1 register is masked. ITBRO Broadcast packet transmission. When this bit is 0, the interrupt of the corresponding bit of the TSVREG1 register is masked.
  • Page 84 CHAPTER 4 REGISTER DESCRIPTION RIMR - Reception interrupt mask register (register address A[7:0] = 92H) R/W Reserved IRFOV IRWMH IRWML IRLENE IVLAN IUSOP IRPCF IRCFR IDNB IRBRO IRMUL IRXOK IRLOR IRLER IRCRCE IRCV ICEPS IREPS IPAIG This register masks occurrence of the INT# signal due to each cause. When each bit of this register is set to 1, the mask is cleared.
  • Page 85 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default IRLOR Length field check. When this bit is 0, the interrupt of the corresponding bit of the RSVREG register is masked. IRLER Data length non-coincidence. When this bit is 0, the interrupt of the corresponding bit of the RSVREG register is masked.
  • Page 86 CHAPTER 4 REGISTER DESCRIPTION TSVREG1 - Transmit status register 1 (register address A[7:0] = 93H) Read only Reserved TCBC ITPP TPCF TCFR TGNT LCOL ECOL TEDFR TDFR TBRO TMUL TDONE TFLOR TFLER TCRCE This register indicates an interrupt source when the INT# signal is made low by the status of a transmit packet (except bits 31 through 16).
  • Page 87 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default TEDFR Excessive defer. When this bit is 1, it indicates that an excessive defer (i.e., transmission is not started even after 24288 bit time) has occurred. TDFR Transmission defer. When this bit is 1, it indicates that a transmission delay has occurred. This bit is not set to 1 if transmission is aborted.
  • Page 88 CHAPTER 4 REGISTER DESCRIPTION TSVREG2 - Transmit status register 2 (register address A[7:0] = 94H) Read only TTBC TBYT This register indicates the number of transmit bytes per transmitted packet, and is updated at the end of each transmission or when transmission is aborted. If this register is read when the SRRC bit of the MISCR register is set to 1, all the bits are automatically cleared.
  • Page 89 CHAPTER 4 REGISTER DESCRIPTION RSVREG - Receive status register (register address A[7:0] = 95H) Read only RBYT RLENE VLAN USOP RPCF RCFR DBNB RBRO RMUL RXOK RLOR RLER RCRCE CEPS REPS PAIG This register indicates an interrupt source when the INT# signal is made low by the status of a receive packet (except bits 31 through 16).
  • Page 90 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default RLOR Length field check. When this bit is 1, it indicates that the value of the length field of a received packet exceeds 1500. This bit is not set to 1 if the FLCHT bit of the MACC1 register is 0.
  • Page 91 CHAPTER 4 REGISTER DESCRIPTION FSVREG - FIFO status register (register address A[7:0] = 96H) Read only Reserved Reserved TFOV TFUM TWMH Reserved RFOV RWMH RWML This register indicates an interrupt source when the INT# signal is made low by each status (except Reserved bits).
  • Page 92 CHAPTER 4 REGISTER DESCRIPTION PCSC - PCS configuration register (register address A[7:0] = 98H) R/W Reserved Reserved PCRST INTLB EXINT ENJAE Name Function Default 31:4 – Reserved. Write 0 to these bits. PCRST PCS block software reset. When this bit is set to 1, software reset is executed. To clear software reset, write 0 to this bit.
  • Page 93 CHAPTER 4 REGISTER DESCRIPTION RFIC1 - Receive FIFO configuration register 1 (register address A[7:0] = 9BH) R/W Reserved RFDMH Reserved RFDML Name Function Default 31:27 – Reserved. Write 0 to these bits. 26:16 RFDMH Pause frame transmission level. 7FFH If the quantity of data in the receive FIFO exceeds the value of this field when the transmission flow control function is enabled, a pause frame having the pause timer value set by the MACC3 register is automatically transmitted.
  • Page 94 CHAPTER 4 REGISTER DESCRIPTION RFIC2 - Receive FIFO configuration register 2 (register address A[7:0] = 9CH) R/W Reserved RFUB Reserved SIFT DCRCE FCRX Name Function Default 31:27 – Reserved. Write 0 to these bits. Note 1 26:16 RFUB Receive FIFO upper limit setting 7FFH This field sets the upper limit of the receive FIFO.
  • Page 95 CHAPTER 4 REGISTER DESCRIPTION TFIC - Transmit FIFO configuration register (register address A[7:0] = 9DH) R/W Reserved TFDMH Reserved TFDWL Name Function Default 31:25 – Reserved. Write 0 to these bits. 24:16 TFDMH Transmission full level. 0FFH If the quantity of the data in the transmit FIFO is less than the value of this field, the µ...

  • Page 96: Global Registers

    CHAPTER 4 REGISTER DESCRIPTION 4.3 Global Registers The global registers are used to set and check the statuses of all the ports. When accessing a global register, only A[7:0] of the address bus A[10:0] are valid, and A[10:8] are ignored. STIR - Status information register (register address A[7:0] = FBH) Read only P7TS P7RS...
  • Page 97 CHAPTER 4 REGISTER DESCRIPTION (2/2) Name Function Default P7TS Port 4 TSVREG status. This bit is set to 1 if any bit of the TSVREG1 register of port 4 is set to 1. P7RS Port 4 RSVREG status. This bit is set to 1 if any bit of the RSVREG register of port 4 is set to 1. P7FS Port 4 FSVREG status.
  • Page 98 CHAPTER 4 REGISTER DESCRIPTION MISCR - FIFO bus width/interrupt setting register (register address A[7:0] = FCH) R/W Reserved BUSWTH Reserved INTEN Reserved SRRC Name Function Default 31:17 – Reserved. Write 0 to these bits. – BUSWTH FIFO bus interface data bus width. When this bit is 0, the data bus width of the FIFO bus interface is 32 bits (32-bit dual bus mode).
  • Page 99 CHAPTER 4 REGISTER DESCRIPTION MIRR - Mirror port setting register (register address A[7:0] = FDH) R/W Reserved Reserved MP4EN MP0EN Name Function Default 31:8 – Reserved. Write 0 to these bits. – Transmission/reception selection (mirror port: port 4). When port 4 is used as a mirror port, this bit selects which of transmission or reception is mirrored.
  • Page 100 CHAPTER 4 REGISTER DESCRIPTION POWD - Power down control register (register address A[7:0] = FFH) R/W Reserved Reserved POWD Name Function Default 31:8 – Reserved. Write 0 to these bits. – POWD Setting of power down mode. This field sets a power down mode. By setting a bit of this field to 1, clock supply to the corresponding port in the device is cut.

  • Page 101: Chapter 5 Statistics Counters

    CHAPTER 5 STATISTICS COUNTERS Statistics counter map (1/2) Register Address Name Function Default A[7:0] RBYT Byte reception counter 00000000H RPKT Packet reception counter 00000000H RFCS CRC error reception counter 00000000H RMCA Multicast packet reception counter 00000000H RBCA Broadcast packet reception counter 00000000H RXCF Control frame reception counter...
  • Page 102 CHAPTER 5 STATISTICS COUNTERS (2/2) Register Address Name Function Default A[7:0] TXDF Transmission excessive defer counter 00000000H TSCL Single collision packet transmission counter 00000000H TMCL Multi-collision packet transmission counter 00000000H TLCL Late collision counter 00000000H TXCL Excessive collision counter 00000000H TNCL Total collision counter 00000000H...
  • Page 103 CHAPTER 5 STATISTICS COUNTERS RBYT - Byte reception counter (register address A[7:0] = 50H) R/W RBYT[31:16] RBYT[15:0] This counter indicates the byte count of a receive packet. It counts the number of bytes from the destination address to the FCS byte of the packet. It also counts even if an error occurs. If a packet exceeding the length set by the LMAX register is received when the HUGEN bit of the MACC1 register is 0, the value of the LMAX register is counted as the packet length.
  • Page 104 CHAPTER 5 STATISTICS COUNTERS RMCA - Multicast packet reception counter (register address A[7:0] = 53H) R/W RMCA[31:16] RMCA[15:0] This counter counts multicast packets with a length of longer than 64 bytes and less than 1518 bytes (less than 1522 bytes in the case of a VLAN frame) when such packets have been received. Broadcast packets are not included.
  • Page 105 CHAPTER 5 STATISTICS COUNTERS RXUO - Undefined control frame reception counter (register address A[7:0] = 57H) R/W RXUO[31:16] RXUO[15:0] This counter counts received control frames including an op code other than PAUSE or pause control frames having an invalid destination address. The counter is not incremented when a CRC error has been detected. RALN - Alignment error reception counter (register address A[7:0] = 58H) R/W RALN[31:16] RALN[15:0]...
  • Page 106 CHAPTER 5 STATISTICS COUNTERS RFCR - False Carrier reception counter (register address A[7:0] = 5BH) R/W RFCR[31:16] RFCR[15:0] This counter counts False Carrier if it occurs in an idle state, after the next packet has been received. It is assumed that False Carrier has been generated if 1110B is input from RXD as nibble data when RXER is high level. Even if two or more False Carriers are generated between idle states, this counter counts only once.
  • Page 107 CHAPTER 5 STATISTICS COUNTERS RJBR - Error jabber packet reception counter (register address A[7:0] = 5FH) R/W RJBR[31:16] RJBR[15:0] This counter is incremented if the receive packet is longer than 1518 bytes (less than 1522 bytes in the case of a VLAN frame) and includes a CRC error or alignment error.
  • Page 108 CHAPTER 5 STATISTICS COUNTERS R511 - 256-to-511 byte frame reception counter (register address A[7:0] = 63H) R/W R511[31:16] R511[15:0] This counter is incremented if the receive packet length is 256 to 511 bytes. Packets including a CRC error, symbol error, or length/type error are also counted. R1K - 512-to-1023 byte frame reception counter (register address A[7:0] = 64H) R/W R1K[31:16] R1K[15:0]...
  • Page 109 CHAPTER 5 STATISTICS COUNTERS TBYT - Byte transmission counter (register address A[7:0] = 70H) R/W TBYT[31:16] TBYT[15:0] This counter indicates the byte count of a transmit packet. If a collision occurs before transmission has been completed or aborted, it also counts the transmit byte when the collision occurred. However, the preamble and SFD are not counted.
  • Page 110 CHAPTER 5 STATISTICS COUNTERS TBCA - Broadcast packet transmission counter (register address A[7:0] = 74H) R/W TBCA[31:16] TBCA[15:0] This counter is incremented when a broadcast packet has been transmitted. Multicast packets are not included. This counter is not incremented if transmission is aborted or if a CRC error has been detected. TUCA - Unicast packet transmission counter (register address A[7:0] = 75H) R/W TICA[31:16] TUCA[15:0]...
  • Page 111 CHAPTER 5 STATISTICS COUNTERS TXDF - Transmission excessive defer counter (register address A[7:0] = 78H) R/W TXDF[31:16] TXDF[15:0] This counter is incremented if transmission is aborted by an excessive defer. TSCL - Single collision packet transmission counter (register address A[7:0] = 79H) R/W TSCL[31:16] TSCL[15:0] The value of this counter is incremented if transmission is successful after a collision has occurred once during...
  • Page 112 CHAPTER 5 STATISTICS COUNTERS TXCL - Excessive collision counter (register address A[7:0] = 7CH) R/W TXCL[31:16] TXCL[15:0] This counter is incremented if a number of collisions exceeding the value set in the RETRY field of the CLRT register occurs in a single transmit operation. TNCL - Total collision counter (register address A[7:0] = 7DH) R/W TNCL[31:16] TNCL[15:0]...
  • Page 113 CHAPTER 5 STATISTICS COUNTERS RFOVR - Receive FIFO overrun counter (register address A[7:0] = 80H) R/W RFOVR[31:16] RFOVR[15:0] This counter is incremented if the receive FIFO overruns. Caution This counter does not have a carry bit. If it overflows, this counter is cleared to 0 in the same manner as the other statistics counters.

  • Page 114: Chapter 6 Jtag Boundary Scan

    CHAPTER 6 JTAG BOUNDARY SCAN The µ PD98431 has a JTAG boundary scan circuit. 6.1 Features • Conforms to IEEE1149.1 JTAG Boundary Scan Standard. • Three registers dedicated to boundary scan • Instruction register • Bypass register • Boundary scan register •...

  • Page 115: Internal Configuration Of Boundary Scan Circuit

    CHAPTER 6 JTAG BOUNDARY SCAN 6.2 Internal Configuration of Boundary Scan Circuit Figure 6-1 shows the block diagram of the internal JTAG boundary scan circuit of the µ PD98431. Figure 6-1. Block Diagram of Boundary Scan Circuit Boundary scan register Bypass register Output buffer Instruction decoder...

  • Page 116: Pin Function

    CHAPTER 6 JTAG BOUNDARY SCAN 6.3 Pin Function 6.3.1 TCK (JTAG Test Clock) pin The TCK pin is used to supply a clock signal to the JTAG boundary scan circuit (such as the bypass register, instruction register, and TAP controller. This clock signal is isolated so as not to be supplied to the other internal circuits of the µ...

  • Page 117: Operation Description

    CHAPTER 6 JTAG BOUNDARY SCAN 6.4 Operation Description 6.4.1 TAP controller The TAP controller is a circuit having 16 states synchronized with changes of the TMS and TCK pins. Its operation is specified by IEEE Standard 1149.1. 6.4.2 TAP controller state Figure 6-2 shows the state transition of the TAP controller.
  • Page 118 CHAPTER 6 JTAG BOUNDARY SCAN Figure 6-3. Operation Timing in Controller State Controller state Enters state Starts in state Starts in state at falling edge of TCK pin at rising edge of TCK pin (1) Test-Logic-Reset The boundary scan circuit performs no operation on the µ PD98431. Therefore, it does not affect the system logic of the µ...
  • Page 119 CHAPTER 6 JTAG BOUNDARY SCAN (4) Select-IR-Scan This is a temporary boundary scan state. The boundary scan register and bypass register selected by the current instruction hold the previous state. If the TMS pin signal is held low at the rising edge of the TCK pin signal while the TAP controller is in this state, the controller enters the Capture-IR state, and scan sequence to the selected registers is started.
  • Page 120 CHAPTER 6 JTAG BOUNDARY SCAN (9) Exit2-DR This is a temporary controller state. If the TMS pin signal is held high at the rising edge of the TCK pin signal with the TAP controller in this state, the controller enters the Update-DR state. This ends the scan process. If the TMS pin signal is held low at the rising edge of the TCK pin signal, the TAP controller enters the Shift-DR state.
  • Page 121 CHAPTER 6 JTAG BOUNDARY SCAN (13) Exit1-IR This is a temporary controller state. If the TMS pin signal is held high at the rising edge of the TCK pin signal, the TAP controller enters the Update-IR state. This ends the scan process. If the TMS pin signal is held low at the rising edge of the TCK pin, the TAP controller enters the Pause-IR state.

  • Page 122: Tap Controller Operation

    CHAPTER 6 JTAG BOUNDARY SCAN 6.5 TAP Controller Operation The TAP controller operates as follows. The state of the controller is changed by either of (1) and (2) below. (1) Rising edge of TCK pin signal (2) TRST# pin input The TAP controller generates signals that control the operations of the bypass register, boundary scan register, and instruction register defined by the IEEE1149.1 JTAG Boundary Scan Standard (refer to Figures 6-4 and 6-5).
  • Page 123 CHAPTER 6 JTAG BOUNDARY SCAN Figure 6-4. Operation of Test Logic (Instruction Scan) TCK pin signal TMS pin signal Controller state TDI pin signal Input data to IR IR shift register Parallel output of IR Bypass New instruction Note Input data to TDR TDR shift register Parallel output of TDR Old data...
  • Page 124 CHAPTER 6 JTAG BOUNDARY SCAN Figure 6-5. Operation of Test Logic (Data Scan) TCK pin signal TMS pin signal Controller state TDI pin signal Input data to IR IR shift register Instruction Bypass Parallel output of IR Note Input data to TDR TDR shift register Old data New instruction...

  • Page 125: Initializing Tap Controller

    CHAPTER 6 JTAG BOUNDARY SCAN 6.6 Initializing TAP Controller The TAP controller is initialized as follows: (1) The TAP controller is not initialized by the operation of system input such as system reset. (2) The TAP controller enters the Test-Logic-Reset controller state at the fifth rising edge of the TCK pin signal (while the TMS pin signal is held high).

  • Page 126: Bypass Instruction

    CHAPTER 6 JTAG BOUNDARY SCAN 6.7.1 BYPASS instruction This instruction is specified by instruction data “11”. This instruction is used to select only the bypass register (to access between the TDI and TDO pins serially) in the Shift-DR controller state. While this instruction is selected, the operation of the JTAG boundary scan circuit does not affect the operation of the µ...
  • Page 127 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we’ve taken, you may Name encounter problems in the documentation.

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