Advantech FWA-1012VC User Manual page 59

JTAG
LAN
LPC
MAC
MDIO
MTBF
NC‐SI
NMC
PCI
PCIe
PCH
PECI
PET
PHY
PICMG
QPI
RAID
RANK
RDIMM
RGMII
RTC
Sandy Bridge‐EP
Processor
SATA
SAS
SCI
SDRAM
SerDes
SGMII
SIU
SIW
SKU
Copyright 2017 Advantech Co. Ltd. All rights reserved.
Joint Test Action Group
Local Area Network
Low Pin Count
Media Access Control
Management Data Input / Output Interface over MDC/MDIO lines
Mean Time Between Failure
Network Controller Sideband Interface
Network Mezzanine Card
Peripheral Component Interconnect Local Bus
PCI Express.
Platform Controller Hub
Platform Environment Control Interface.
Platform Event Trap.
Physical Layer Device
PCI Industrial Computer Manufacturers Group
Quick Path Interconnect. A cache‐coherent, link‐based interconnect
specification for Intel Processors, chipsets, and I/O bridge.
Redundant Array of Inexpensive Disks or Redundant Array of Independent Disks
A unit of DRAM corresponds to four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a DDR3
DIMM.
Registered dual In‐line Memory Module.
Reduced gigabit media independent interface
Real Time Clock
Intel's 32‐nm processor design, follow‐on to the 32‐nm Sandy Bridge processor
design.
Serial ATA.
Serial Attached SCSI
System Control Interrupt. Used in ACPI protocol.
Synchronous Dynamic Random Access Memory
Serializer and De‐Serializer Circuit
Serialized Gigabit Media Independent Interface
Serial I/O Unit
Serial I/O and Watchdog Timer
Stock Keeping Unit
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