MSI NF720DT-C43 Series Manual page 50

▍ ▍ BIOS Setup BIOS Setup
▶ DRAM Tmng Mode
Ths field has the capacty to automatcally detect all of the DRAM tmng. If you set
ths field to [DCT 0], [DCT 1] or [Both], some fields wll appear and selectable. DCT
0 controls channel A and DCT1 controls channel B.
▶ CAS# Latency (TCL)
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Ths controls the CAS latency, whch determnes the tmng delay (n clock
cycles) before SDRAM starts a read command after recevng t.
▶ RAS#to CAS#Delay(TRCD)
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. When DRAM s refreshed, both rows and columns are addressed separately.
Ths setup tem allows you to determne the tmng of the transton from RAS (row
address strobe) to CAS (column address strobe). The less the clock cycles, the
faster the DRAM performance.
▶ RAS# Percharge Tme (TRP)
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], ths field s adjust-
able. Ths settng controls the number of cycles for Row Address Strobe (RAS) to
be allowed to precharge. If nsufficent tme s allowed for the RAS to accumulate
ts charge before DRAM refresh, refresh may be ncomplete and DRAM may fal
to retan data. Ths tem apples only when synchronous DRAM s nstalled n the
system.
▶ tRTP
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Tme nterval between a read and a precharge command.
Mn RAS# Actve Tme (TRAS)
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], ths field s adjust-
able. Ths settng determnes the tme RAS takes to read from and wrte to memory
cell.
▶ ROW Cycle Tme (TRC)
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. The rowcycle tme determnes the mnmum number of clock cycles a memory
row takesto complete a full cycle, from row actvaton up to the prechargng of the
actverow.
▶ tWR
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Mnmum tme nterval between end of wrte data burst and the start of a pre-
charge command. Allows sense amplfiers to restore data to cells.
▶ ROW to ROW Delay (TRRD)
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Specfies the actve-to-actve delay of dfferent banks. Tme nterval between a
read and a precharge command.
▶ tWTR
When the DRAM Tmng Mode sets to [DCT 0], [DCT1] or [Both], the field s adjust-
able. Mnmum tme nterval between the end of wrte data burst and the start of a
column-read command. It allows I/O gatng to overdrve sense amplfiers before read
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