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NXP Semiconductors Freescale Semiconductor MPC8308 Errata Sheet
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NXP Semiconductors Freescale Semiconductor MPC8308 Errata Sheet

NXP Semiconductors Freescale Semiconductor MPC8308 Errata Sheet

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Freescale Semiconductor
Chip Errata
MPC8308 Chip Errata
This document details all known silicon errata for the MPC8308. The following table provides a revision history for
this document.
Revision
Date
5
09/2015
4
07/2013
3
05/2012
2
12/2011
1
11/2011
0
07/2010
© 2015 Freescale Semiconductor, Inc.
Table 1. Document Revision History
Added the following errata:
• eSDHC A-005055 and A-009204
• IEEE1588 A-007734
• PCIe PEX5
• USB A-003845
Added IEEE 1588_19 to Table 3, Summary of Silicon Errata and Applicable Revision.
Modified eTSEC69.
Renamed eTSEC-A002 to A-006502 and modified the write-up.
Renamed "PEX" heading to "PCIe".
Re-ordered the USB errata numerically.
Renamed USB38 to USB erratum A-003817
Added the following errata:
• USB errata: A-003837, A-003827, A-003829
• eSDHC erratum: A-004577
Removed erratum DDR20
• In Table 2, added silicon revision 1.1 SVR and PVR information.
• In Table 3, added silicon revision 1.1 column.
• In Table 3, updated the projected solution for the following errata: IEEE1588-A001,
PCIe- A002, and A-003985.
• Added eLBC-A002
• Removed eLBC1, eLBC2, eTSEC29, IEEE1588_8, USB21
• Added USB-A005, USB-A007, CPU-A022, PCIe-A002, A-003985
• Removed SPI6
• Updated USB-A001
Initial release
Significant Changes
MPC8308CE
Rev. 5, 09/2015

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Summary of Contents for NXP Semiconductors Freescale Semiconductor MPC8308

  • Page 1 Freescale Semiconductor MPC8308CE Chip Errata Rev. 5, 09/2015 MPC8308 Chip Errata This document details all known silicon errata for the MPC8308. The following table provides a revision history for this document. Table 1. Document Revision History Revision Date Significant Changes 09/2015 Added the following errata: •...
  • Page 2 The following table provides a cross-reference to match the revision code in the processor version register to the revision level marked on the device. Table 2. Revision Level to Part Marking Cross-Reference Part Revision Processor Version Register System Version Register Value Mask Value MPC8308...
  • Page 3 Table 3. Summary of Silicon Errata and Applicable Revision (continued) Errata Name Projected Solution Silicon Rev. A-009204 System bus may hang if software register SYSCTL[RSTD] is set No plans to fix while DMA transactions are active eTSEC eTSEC42 Frame is dropped with collision and HALFDUP[Excess Defer] = No plans to fix eTSEC58 VLAN Insertion corrupts frame if user-defined Tx preamble...
  • Page 4 Table 3. Summary of Silicon Errata and Applicable Revision (continued) Errata Name Projected Solution Silicon Rev. General14 Electrostatic Discharge (ESD) may fail to meet the 2KV Human No plans to fix body body model (HBM) General16 Enabling I C could cause I C bus freeze when other I C devices No plans to fix...
  • Page 5 Table 3. Summary of Silicon Errata and Applicable Revision (continued) Errata Name Projected Solution Silicon Rev. USB37 OTG Controller as Host does not support Data-line Pulsing No plans to fix Session Request Protocol USB-A001 Last read of the current dTD done after USB interrupt No plans to fix USB-A002 Device does not respond to INs after receiving corrupted...
  • Page 6 CPU6: DTLB LRU logic does not function correctly Description: The DTLB is implemented as 2-way set associative with 32 entries per way. EA[15:19] is used to determine which one of the 32 entries of both ways. When a DTLB miss occurs, normally the CPU provides information (through SRR1 bit 14, DTLB replacement way) to indicate which of the two ways the software (DTLB exception handler or the software table walk routine) should use to bring in the new page.
  • Page 7 CPU-A002: CPU may hang after load from cache-inhibited, unguarded memory Description: There is a one-core-clock-cycle window of opportunity for a snoop to collide with the data returned from cache-inhibited memory to a load that has been cancelled. This collision can hang the data cache in a busy state, prohibiting further data cache accesses.
  • Page 8 CPU-A022: The e300 core may hang while using critical interrupt Description: If BOTH critical interrupt AND normal interrupt types are used in a system, the e300 core may hang. Impact: The processor may stop dispatching instructions until a hardware reset(HRESET). Debug tools will not be able to read any register correctly except program counter IAR which points to a location in the critical interrupt vector.
  • Page 9 DDR21: MCK/MCK AC differential crosspoint voltage outside JEDEC specifications Description: The crossover points of the MCK and MCK signals of the DDR controller are not meeting JESD79-2C specifications, which indicates that the crossover points should lie within ±125 mV range of reference voltage. Impact: Disagreement with the JESD79-2C standard.
  • Page 10 Exact values of components vary from design to design and some of them may not be required fpr all designs. We recommend that you make provisions for all these options in your design. Fix plan: No plans to fix MPC8308 Chip Errata, Rev. 5, 09/2015 Freescale Semiconductor, Inc.
  • Page 11 DDR23: DDR read failure due to t spec violation DISKEW Description: When the minimum voltage swing (500 mV) on inputs specified by JEDEC spec is applied, there will be violation of t parameter. DISKEW Impact: DDR read operation is not guaranteed if peak-to-peak input voltage swing is less than 800 mV. Workaround: Select the parallel termination resistor and configuration such that the peak-to-peak input voltage swing is more than 800 mV.
  • Page 12 eLBC5: LTEATR and LTEAR may show incorrect values under certain scenarios Description: The eLBC IP acks any transaction request when FCM special operation is in progress. In such a scenario when any one of the errors/events occur (such as Bus Monitor Timeout, Write Protect, Parity error, Atomic error, FCM command completion, or UPM command completion except for the CS error), the registers LTEAR and LTEATR capture the address and attributes of the most recently req-acked transaction instead of the FCM special operation that caused...
  • Page 13 eLBC-A001: Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus monitor timeout Description: When the FCM is in the middle of a long transaction, such as NAND erase or write, another transaction on the GPCM or UPM triggers the bus monitor to start immediately for the GPCM or UPM, even though the GPCM or UPM is still waiting for the FCM to finish and has not yet started its transaction.
  • Page 14 eLBC-A002: Core may hang while booting from NAND using FCM Description: When FCM is selected as the boot ROM controller via power-on-reset configuration, eLBC automatically loads 4K Bytes page of boot code into the FCM buffer RAM. These 4K Bytes consist of 8 pages (512 bytes each) of small-page NAND flash OR 2 pages (2048 bytes each) of Large-page NAND flash.
  • Page 15 eSDHC16: Manual Asynchronous CMD12 abort operation causes protocol violations Description: There may be protocol violations if a manual (software) asynchronous CMD12 is used to abort data transfer. Due to this erratum, the eSDHC controller continues driving data after a manual (software) asynchronous CMD12 is issued.
  • Page 16 eSDHC23: CMD CRC error or CMD index error may be set for CMD without data while CMD with data is in progress Description: While a command with data is in progress and a command without data is issued, for example CMD13, an invalid command CRC error (IRQSTAT[CCE]) and/or command index error (IRQSTAT[CIE]) might be detected.
  • Page 17 eSDHC-A002: BLKATTR[BLKCNT] does not return to 0 after Transfer Complete for multi-block transfer Description: For a multi-block transfer, when the XFERTYP[BCEN](block count enable) is 1, BLKATTR[BLKCNT] should decrement to 0 after Transfer Complete (TC)((IRQSTAT[TC] = 1). However, due to this erratum, BLKATTR[BLKCNT] returns to the initial value which was programmed while issuing the multi-block transfer command.
  • Page 18 A-004577: PRSSTAT[DLA] bit does not reflect the data line state when any command with busy (R1b) is issued Affects: eSDHC Description: When an AutoCMD12 or any command with busy (R1b) is issued, PRSSTAT[DLA] bit should reflect the data line state. However, due to this erratum, PRSSTAT[DLA] is not applicable to detect data busy state.
  • Page 19 A-005055: A glitch is generated on the card clock with software reset or a clock divider change Affects: eSDHC Description: A glitch may occur on the SDHC card clock when the software sets the SYSCTL[RSTA] bit (that is, performs a software reset). It can also be generated by setting the clock divider value. The glitch produced can cause the external card to switch to an unknown state.
  • Page 20 A-009204: System bus may hang if software register SYSCTL[RSTD] is set while DMA transactions are active Affects: eSDHC Description: In the event of that any data error (like, IRQSTAT[DCE]) occurs during an eSDHC data transaction where DMA is used for data transfer to/from the system memory, setting the SYSCTL[RSTD] register may cause a system hang.
  • Page 21 eTSEC42: Frame is dropped with collision and HALFDUP[Excess Defer] = 0 Description: eTSEC drops excessively deferred frames without reporting error status when HALFDUP[Excess Defer] = 0. This erratum affects 10/100 Half Duplex modes only. Impact: The eTSEC does not correctly abort frames that are excessively deferred. Instead it closes the BD as if the frame is transmitted successfully.
  • Page 22 eTSEC58: VLAN Insertion corrupts frame if user-defined Tx preamble enabled Description: When TCTRL[VLINS] = 1, the VLAN is supposed to be inserted into the Tx frame 12 bytes after start of the Destination Address (after DA and SA). If user-defined Tx preamble is enabled (MACCFG2[PreAmTxEn] = 1), the VLAN ID is inserted 12 bytes after the start of the preamble (4 bytes after start of DA), thus overwriting part of DA and SA.
  • Page 23 eTSEC59: False parity error at Tx startup Description: The 10 KB TxFIFO comes out of reset in an unitialized state. Each FIFO entry is initialized as Tx frame data is written to it. Under certain internal resource contention conditions, the controller may read uninitialized data and falsely signal a parity error in IEVENT.
  • Page 24 eTSEC64: User-defined Tx preamble incompatible with Tx Checksum Description: If user-defined Tx preamble is enabled (by setting MACCFG2[PreAmTxEn]=1), an extra 8 bytes of data is added to the frame in the Tx data FIFO. IP and TCP/UDP checksum generation do not take these extra bytes into account and write to the wrong locations in the frame.
  • Page 25 eTSEC67: ECNTRL[AUTOZ] not guaranteed if reading MIB counters with software Description: The MIB function of the Ethernet controller has a feature to automatically zero out the registers when reading them if ECNTRL[AUTOZ] = 1. If the register read occurs in the same cycle as a hardware update of the register, then the register clear will not occur.
  • Page 26 eTSEC68: Half-duplex collision on FCS of Short Frame may cause Tx lockup Description: In half-duplex mode, if a collision occurs in the FCS bytes of a short (fewer than 64 bytes) frame, then the Ethernet MAC may lock up and stop transmitting data or control frames. Only a reset of the controller can restore proper operation once it is locked up.
  • Page 27 eTSEC69: Ethernet controller does not exit from Magic Packet mode when an oddly formed Magic Packet is received Description: The Ethernet MAC should recognize as a Magic Packet any Ethernet frame with the following contents: • A valid Ethernet header (Destination and Source Addresses) •...
  • Page 28 eTSEC70: MAC: Malformed Magic Packet Triggers Magic Packet Exit Description: The Ethernet MAC should recognize Magic Packet sequences as follows: Any Ethernet frame containing a valid Ethernet header DA/SA (Destination and Source Addresses) and valid FCS (CRC-32), and whose payload includes the specific Magic Packet byte sequence at any offset from the start of data payload.
  • Page 29 eTSEC71: The value of TSEC_ID2 is incorrect Description: The eTSEC1 and eTSEC2 TSEC_ID2 registers (0x24004, 0x25004) have a wrong default value of 0x00EC00F0, not according to the Reference Manual. The correct value, as in the Reference Manual, should be 0x00E000F0. Impact: There is no functional impact.
  • Page 30 eTSEC73: TxBD polling loop latency is 1024 bit-times instead of 512 Description: Register bit DMACTRL[WOP] defines the use of wait on poll when transmit ring scheduling algorithm is set to single polled ring mode. (TCTRL[TXSCHED]=00). When the use polling is selected by setting DMACTRL[WOP]=0, the poll to TxBD on ring 0 should occur every 512 bit- times.
  • Page 31 eTSEC74: MAC: Rx frames of length MAXFRM or MAXFRM-1 are marked as truncated Description: If MACCFG2[Huge Frame]=0 and the Ethernet controller receives frames which are larger than MAXFRM, the controller truncates the frames to length MAXFRM and marks RxBD[TR]=1 to indicate the error. The controller also erroneously marks RxBD[TR]=1 if the received frame length is MAXFRM or MAXFRM-1, even though those frames are not truncated.
  • Page 32 eTSEC75: Misfiled Packets Due to Incorrect Rx Filer Set Mask Rollback Description: When the eTSEC Rx filer exits a cluster or AND chain that does not produce a match, it should roll back the mask to the value at the beginning of the chain or cluster. If that cluster or AND chain does not contain a Set Mask rule, however, the mask rolls back to the value prior to the previous Set Mask rule due to this erratum.
  • Page 33 End of AND chain, the 2nd rule, look for Destination Address low 24-bits & Mask greater than RQPROP. Roll back mask to value at start of chain. After rule #8, the mask should roll back to the mask set by the last Set Mask rule outside the cluster (rule #6), but instead rolls back to the previous mask value (set by rule #1, and restored after cluster exit between rule 5 and 6).
  • Page 34 eTSEC76: Excess delays when transmitting TOE=1 large frames Description: The Ethernet controller supports generation of TCP or IP checksum in frames of all sizes. If TxBD[TOE]=1 and TCTRL[TUCSEN]=1 or TCTRL[IPCSEN]=1, the controller holds the frame in the TxFIFO while it fetches the data necessary to calculate the enabled checksum(s). Because the checksums are inserted near the beginning of the frame, transmission cannot start on a TOE=1 frame until the checksum calculation and insertion are complete.
  • Page 35 eTSEC78: Controller may not be able to transmit pause frame during pause state Description: When the Ethernet controller pauses transmit of normal frames after receiving a pause control frame with PTV!=0, it should still be able to transmit pause control frames. The Ethernet controller, however, does not check whether the MAC is paused before initiating a start-of- frame request to the MAC.
  • Page 36 eTSEC-A001: MAC: Pause time may be shorter than specified if transmit in progress Description: When the Ethernet controller receives a pause frame with PTV!=0, and MACCFG1[Rx Flow]=1, it completes transmitting any current frame in progress, then should pause for PTV*512 bit times. The MAC, however, does not take the full transmission time of the current frame into account when calculating the Tx pause time, and may pause for 1-2 pause quanta (512-1024 bit times) less than the PTV value.
  • Page 37 A-006502: Incomplete GRS or invalid parser state after receiving a 1- or 2-byte frame Affects: eTSEC Description: Ethernet standards define the minimum frame size as 64 bytes. The eTSEC controller also supports receiving short frames less than 64 bytes, and can accept frames more than 16 bytes and less than 64 bytes if RCTRL[RSF] = 1.
  • Page 38 IEEE 1588_14: TxPAL timestamp uses TxBD snoop enable instead of Tx data Description: The DMACTRL register contains two snoop enable bits for Tx: TBDSEN for buffer descriptors and TDSEN for frame data. Tx timestamp writes should use TDSEN to determine transaction snoop enable, but use TBDSEN instead.
  • Page 39 IEEE 1588_16: Odd prescale values not supported Description: The 1588 timer prescale register (TMR_PRSC) defines the timer prescale as follows: PRSC_OCK: Output clock division/prescale factor. Output clock is generated by dividing the timer input clock by this number. Programmed value in this field must be greater than 1. Any value less than 1 is treated as 2.
  • Page 40 IEEE 1588_17: Cannot use inverted 1588 reference clock when selecting eTSEC system clock as source Description: The source of the 1588 reference clock can be selected with TMR_CTRL[CKSEL] register bit field, while the TMR_CTRL[CIPH] register bit field allows the user to invert the selected 1588 reference clock.
  • Page 41 IEEE 1588_19: Tx FIFO data parity error (DPE) may corrupt Tx timestamps if TMR_CTRL[TRTPE]=1 Description: If TMR_CTRL[TRPTE] = 1, the Ethernet controller writes Tx timestamp information for frames with TxFCB[PTP] = 1 to external memory in a PAL region. There is a queue of TxPAL addresses in the Ethernet controller that doesn't get cleared upon recovery from a Tx FIFO data parity error.
  • Page 42 IEEE 1588_20: eTSEC 1588: Write to reserved 1588 register space causes system hang Description: The IEEE 1588 control block contains a set of memory-mapped registers shared by all eTSEC controllers. These shared IEEE 1588 registers are located in the eTSEC1 controller memory space and support both read and write operations.
  • Page 43 IEEE1588-A001: Incorrect received timestamp or dropped packet when 1588 time- stamping is enabled Description: When timestamping is enabled for all packets arriving on an Ethernet port (TMR_CTRL[TE] = 1 and RCTRL[TS] = 1), the port may fail to properly recognize the timestamp point for received frames.
  • Page 44 A-007734: Stale time stamps and over-flow conditions can occur when using an external 1588 input clock at certain frequencies Affects: IEEE 1588 Description: When the time stamp logic is enabled using an external 1588 input clock at certain frequencies, the eTSEC receiver can fail to update with the latest time stamp. This results in a stale time stamp in the Rx buffer padding even though eTSEC_TMR_RXTS is updated correctly.
  • Page 45 General14: Electrostatic Discharge (ESD) may fail to meet the 2KV Human body body model (HBM) Description: HBM (Human Body Model) ESD testing has shown that some USB and SGMII / PCIe PHY pins do not meet the 2kV HBM ESD criteria. HBM passes at 1kV. The following pins are impacted: USB_DP, USB_DM, USB_RBIAS, USB_VBUS, USB_VDDA, USB_VDDA_BIAS, SD_PLL_TPA_ANA, TXA, TXA, TXB, TXB, SD_IMP_CAL_TX, SDAVDD, XPADVDD,...
  • Page 46 General16: Enabling I C could cause I C bus freeze when other I C devices communicate Description: When the I C controller is enabled by software, if the signal SCL is high and the signal SDA is low, and the I C address matches the data pattern on the SDA bus right after the enabling, an ACK is issued on the bus.
  • Page 47 General17: DUART: Break detection triggered multiple times for a single break assertion Description: A DUART break signal is defined as a logic zero being present on the UART data pin for a time longer than (START bit + Data bits + Parity bit + Stop bits).The break signal persists until the data signal rises to a logic one.
  • Page 48 PEX1: No support of PCI Express completions with BCM bit set (PCIX bridge interface) Description: To satisfy certain PCI-X protocol constraints, a PCI-X Bridge or PCI-X Completer for a PCI-X burst read in some cases will set the Byte Count field in the first PCI-X transaction of the Split Completion sequence to indicate the size of just that first transaction instead of the entire burst read.
  • Page 49 PEX2: DMA Interrupt descriptor race condition (IDRC) Description: The DMA DONE bit is set and issues an interrupt before the buffer descriptor (BD) is written to memory. Impact: After detecting the interrupt, the software may read wrong data from the descriptor status. Workaround: When serving the interrupt, Software must check that the done bit in the chain descriptor is set.
  • Page 50 PEX5: PCI Express LTSSM may fail to properly train with a link partner following HRESET# Description: Following HRESET#, the PCI Express controller will enter the internal LTSSM (Link Training and Status State Machine), and may fail to properly detect a receiver as defined in the PCI Express Base Specification.
  • Page 51 PEX7: Recovery from hot reset or link down Description: The PCI Express CSB bridge enters a suspend mode as a result of a hot reset or link down event in either endpoint (EP) or root complex (RC) mode. When this happens, the PCI Express controller flushes all outstanding CSB transactions and does not accept new inbound transactions involving CSB and ATMU translation until the CSB bridge is unlocked, even though the link is automatically retrained properly and is stable in L0.
  • Page 52 1. In order to be interrupted when detecting the link down, set the PEX_CSMIER[RSTIE] bit. 2. When the controller identifies a link down event, the PEX_CSMISR[RST] bit gets set, and an interrupt is generated if the PEX_CSMIER[RSTIE] bit was set. 3.
  • Page 53 PCIe-A002: PCI Express Packets may be transmitted with excess data on x1 link Description: An internal error in the PCI Express controller may cause 8 bytes of packet header or data payload to be duplicated on transmit. Depending on the location of the duplicate bytes, this may cause a malformed packet error or CRC error detected in the link partner.
  • Page 54 A-003985: Real Time Counter Register (RTCTR) may not work correctly Affects: Description: When RTC_PIT_CLK is not connected, the RTCTR counter may not count correctly for both settings of the clock source: CSB clock source (RTCNR[CLIN]=0) or RTC_PIT_CLK clock source (RTCNR[CLIN]=1) for RTC. Impact: RTC counter may not work correctly if RTC_PIT_CLK has no clock connected to it.
  • Page 55 USB15: Read of PERIODICLISTBASE after successive writes may return a wrong value in host mode Description: In the USB controller a new feature (hardware assist for device address setup) was introduced. This feature allows presetting of the device address in DEVICEADDR register before the device is enumerated, using a shadow register, to assist slow processors.
  • Page 56 USB19: USBDR in Host mode does not generate an interrupt upon detection of a CRC16/PID/Timeout error when a received IN data packet is corrupted Description: USB dual role controller (USBDR) in Host mode does not generate an interrupt and does not set the respective bit in the USBSTS register upon detection of a CRC16/PID/Timeout error when a received IN data packet is corrupted.
  • Page 57 USB25: In host mode, when the software forces a port resume by writing into the FPR bit of the portsc register, the port change detect interrupt bit is falsely fired Description: In host mode, a false "port change detect" interrupt is fired when the HCD (Host controller driver) resumes a suspended port by writing "1"...
  • Page 58 USB26: NackCnt field is not decremented when received NYET during FS/LS Bulk/ Interrupt mode Description: The spec says that NakCnt should be decremented, whenever Host receives a NYET response to the Bulk CSPLIT and it should be reloaded when a start event is detected in the asynchronous list.
  • Page 59 USB27: When an ACK or NAK is sent from the device in response to a PING, the CERR counter value is not being reset to the initial value Description: When the Controller is acting as a Host, the host state machine needs to update the ping status in response to a PING.
  • Page 60 USB28: In device mode, when receiving a Token OUT, if a Rx flush command is issued at the same time, to the same endpoint, the packet will be lost Description: When receiving a Token OUT, the packet is lost if an Rx flush command is issued at the same time to the same endpoint.
  • Page 61 USB29: Priming ISO over SOF will cause transmitting bad packet with correct CRC Description: In device mode, a priming operation performed by software while an IN token is being received (usually just after the SOF) can lead to an invalid transfer in the next frame or an abortion of a transfer that should not be canceled.
  • Page 62 USB31: Transmit data loss based on bus latency Description: When acting as a Device, after receiving a Token IN, the USB controller will reply with a data packet. If the bus memory access is not fast enough to backfill the TX fifo, it will cause an under-run.
  • Page 63 USB32: Missing SOFs and false babble error due to Rx FIFO overflow Description: When in Host mode, if an Rx FIFO overflow happens close to the next Start-of-Frame (SOF) token and the system bus (CSB) is not available, a false frame babble is reported to software and the port is halted by hardware.
  • Page 64 USB33: No error interrupt and no status will be generated due to ISO mult3 fulfillment error Description: When using ISO IN endpoints with MULT = 3 and low bandwidth system bus access, the controller may enter into a wait loop situation without warning the software. Due to the low bandwidth, the last packet from a mult3 sequence may not be fetched in time before the last token IN is received for that microframe/endpoint.
  • Page 65 USB34: NAK counter decremented after receiving a NYET from device Description: When in host mode, after receiving a NYET to an OUT Token, the NAK counter is decremented when it should not. Impact: The NAK counter may be lower than expected. Workaround: None Fix plan: No plans to fix...
  • Page 66 USB35: Core device fails when it receives two OUT transactions in a short time Description: In the case where the Controller is configured as a device and the Host sends two consecutive ISO OUT (example sequence: OUT - DATA0 - OUT - DATA1) transactions with a short inter- packet delay between DATA0 and the second OUT (less than 200 ns), the device will see the DATA1 packet as a short-packet even if it is correctly formed.
  • Page 67 USB36: CRC not inverted when host under-runs on OUT transactions Description: In systems with high latency, the HOST can under-run on OUT transactions. In this situation, it is expected that the CRC of the truncated data packet to be the inverted (complemented), signaling an under-run situation.
  • Page 68 USB37: OTG Controller as Host does not support Data-line Pulsing Session Request Protocol Description: An OTG core as a Host must be able to support at least one Session Request Protocol (SRP) method (VBUS or Data-line Pulsing), but OTG as Device must support and use both when attempting SRP.
  • Page 69 USB-A001: Last read of the current dTD done after USB interrupt Description: After executing a dTD, the device controller executes a final read of the dTD terminate bit. This is done in order to verify if another dTD has been added to the linked list by software right at the last moment.
  • Page 70 USB-A002: Device does not respond to INs after receiving corrupted handshake from previous IN transaction Description: When configured as a device, a USB controller does not respond to subsequent IN tokens from the host after receiving a corrupted ACK to an IN transaction. This issue only occurs under the following two conditions: 1.
  • Page 71 A workaround is needed if the data length of the next transaction after the corrupted ACK is less than 32 bytes and the Host_delay in the USB host system is less than 0.6 us. Under this condition, a transfer in a device controller does not progress and the total bytes field in the dTD (device transfer descriptor) remains static.
  • Page 72 USB-A003: Illegal NOPID TX CMD issued by USB controller with ULPI interface Description: During the USB reset process (speed negotiation and chirp), if the protocol engine sends Start of Frame (SOF) commands to the port control, the port control filters out those SOFs. However, at the end of reset (end of chirp back from Host), when the protocol engine sends a SOF, the ULPI port control sends the SOF to the PHY before sending the update OpMode command.
  • Page 73 USB-A005: ULPI Viewport not Working for Read or Write Commands With Extended Address Description: It is not possible to read or write the ULPI PHY extended register set (address >0x3F) using the ULPI viewport. The write operation writes the address itself as data, and a read operation returns corrupted data.
  • Page 74 USB-A007: Host controller fails to enter the PING state on timeout during High Speed Bulk OUT/DATA transaction Description: For High-speed bulk and control endpoints, a host controller queries the high-speed device endpoint with a special PING token to determine whether the device has sufficient space for the next OUT transaction.
  • Page 75 A-003817: USB Controller locks after Test mode "Test_K" is completed Affects: Description: Previously known as USB38 When using the ULPI interface, after finishing test mode "Test_K," the controller hangs. A reset needs to be applied. Impact: No impact if reset is issued after "Test K" procedure (it should be issued according to the standard).
  • Page 76 A-003827: DATA PID error interrupt issued twice for the same high bandwidth ISO transfer Affects: Description: When receiving an Isochronous OUT transfer for a High Bandwidth endpoint (MULT > 0), if one of the DATA PIDs is corrupted, the controller issues two interrupts for that transaction error, one in the current microframe to signal the DATA PID error, and one fulfillment error in the next microframe.
  • Page 77 A-003829: Host detects frame babble but does not halt the port or generate an interrupt Affects: Description: A high speed ISO Device, connected downstream to a high speed hub connected to the USB host, babbled in to the uframe boundary EOF1 time and the hub disabled the propagation of traffic to the upstream root host.
  • Page 78 A-003837: When operating in test mode, the CSC bit does not get set to 1 to indicate a change on CCS Affects: Description: When in test mode (PORTSCx[PTC] != 0000), the Connect Status Change bit (PORSTCx[CSC]) does not get set to 1 to indicate a change in Current Connect Status (PORTSCx[CCS]).
  • Page 79 A-003845: Frame scheduling robustness-Host may issue token too close to uframe boundary Affects: Description: When the USB host encounters an under-run while sending a Bulk OUT packet, it issues a CRC error according to the specification. However, the retry never occurs on the USB and the host appears to hang;...
  • Page 80 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express Home Page: freescale.com or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Web Support: freescale.com/support Freescale reserves the right to make changes without further notice to...