Pcie Interface; Pcie Interface Definition - Fibocom L850-GL Series Hardware Manual

3.4.1 PCIe Interface

L850 module supports PCIe Gen1 interface and one data transmission channel. BIOS configuration must
follow X86 platform BKC (Best Know Configuration) reference design.
PCIe interface is initialized with host driver, and then mapped MBIM & GNSS port in Win10 OS. The MBIM
interface is used for data transfer and GNSS port is used for receiving GNSS data.

3.4.1.1 PCIe Interface Definition

Pin# Pin Name
41 PETn0
43 PETP0
47 PERn0
49 PERP0
53 REFCLKN
55 REFCLKP
50 PERST#
52 CLKREQ#
54 PEWAKE#
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FIBOCOM L850-GL Series Hardware Guide
I/O Reset Value Description
PCIe TX differential signal
O -
Negative
PCIe TX differential signal
O -
Positive
PCIe RX differential signal
I -
Negative
PCIe RX differential signal
I -
Positive
PCIe reference clock signal
I -
Negative
PCIe reference clock signal
I -
Positive
Asserted to reset module PCIe interface
default. If module went into coredump, it will
I PU
reset whole module, not only PCIe interface.
Active low, internal pull up(10KΩ)
Asserted by device to request a PCIe
reference clock be available (active clock
state) in order to transmit data. It also used by
I/O PU
L1 PM Sub states mechanism, asserted by
either host or device to initiate an L1 exit.
Active low, internal pull up(10KΩ)
Asserted to wake up system and reactivate
PCIe link from L2 to L0, it depends on system
O L
whether supports wake up functionality.
Active low, open drain output and should add
external pull up (100KΩ) on platform
Type
-
-
-
-
-
-
3.3V
3.3V
3.3V
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