Pcie Link State - Fibocom L850-GL Series Hardware Manual

+3.3V
FCPO#
RESET#
AT+CFUN=0
PERST#
Module State
Activation
Index Min. Recommended Max.
t 16ms
20ms
off1
t 2ms 10ms
off2
t 500ms 500ms
off
t 8ms 20ms
on1
t 50ms 100ms
on2
Note：
When USB is used as data transfer interface, follow timing above in PERST# connecting with
host, otherwise don't control PERST# in PERST# floating condition.
3.3.4

PCIe Link State

Modem has the lowest power consumption in D0 L1.2 PCIe link state. D3
0.5mA power consumption. CLKREQ# can assert or de-assert in D3
changed again during D3
consumption compared with CLKREQ# de-asserted in D3
asserted in D3 L2.
cold
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FIBOCOM L850-GL Series Hardware Guide
t
off2
t
off1
t
sd
Finalization
Figure 3-9 Reset timing 2
Comments
RESET# should be asserted after PERST#,
-
refer
FCPO# should be asserted after RESET#,
-
refer
Time to allow the WWAN module to fully discharge any
residual voltages before the pin could be de-asserted
-
again. This is required for both Pre-OS as well as Runtime
flow
RESET# should be de-asserted after FCPO#,
-
refer
The time delay of PERST# de-asserted after FCPO#,
- PERST# must always be the last to get de-asserted.
refer
L2. When CLKREQ# asserts in D3
cold
t
off
t
on1
t
on2
typical 10s
OFF Initialization
nd
section 3.3.2
section 3.3.2
section 3.3.1.2
section 3.3.1.2
cold
L2, it will increase extra 0.3mA power
cold
L2. We recommend keep CLKREQ# de-
cold
Activation
L2 will increase extra about
cold
L2, but CLKREQ# shouldn't be
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