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Figure 8 shows the pinout of the 10-pin, 50 mil pitch connector that is used on the EVK-NORA-B1.
This is a compact debug header that can be used on a host board design as well. Other solutions such
as spring-loaded connectors (e.g., Tag-Connect-pads [8]) or simple test points can be used as well.
Keep in mind that a minimum of four signals are required for the SWD interface to work: SWDIO,
SWDCLK, GND and VDD reference are needed for the SWD interface to work. nRESET and SWO are
optional, though suggested. Pin 9 connected to GND is only needed when used with an EVK providing
an on-board debugger, such as the EVK-NORA-B1.
nRESET = 10
N/C = 8
SWO = 6
SWCLK = 4
SWDIO = 2
Figure 8: Cortex-M debug connector pin out on EVK-NORA-B1 for SWD
4.6 Serial interfaces
4.6.1
UART
The layout of the UART bus should be made so that noise injection and cross talk are avoided.
Use hardware flow control with RTS/CTS to prevent temporary UART buffer overrun.
RTS/CTS flow control signals are active low. The UART can transmit when either of these signals are
set to "0" (ON state = low level).
• CTS is an input to NORA-B1. The module can transmit when the host sets this signal to "0" (ON
state = low level).
• RTS is an output from NORA-B1. The module sets this signal to "0" (ON state = low level) when it
is ready to receive transmission.
4.6.2
USB
The layout of the USB bus should be made so that noise injection and crosstalk are avoided.
The signals MODUSB_DP and MODUSB_DM have controlled 90 Ω differential-pair impedance.
Power and ground connections from the upstream USB host should be filtered and ESD protected.
UBX-20027617 - R02
C1-Public
NORA-B1 series - System integration manual
9 = GND
7 = N/C (may be keyed)
5 = GND
3 = GND
1 = VDD reference input
Design-in
Page 29 of 58
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