Linear Technology DC1565A Demo Manual page 3

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Applying Power and Signals to the DC1565A
Demonstration Circuit
The DC1371 is used to acquire data from the DC1565A,
the DC1371 must first be connected to a powered USB
port and have 5V applied power before applying 3.6V to
6V across the pins marked V
DC1565A requires 3.6V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1565A demonstration circuit requires up
to 500mA depending on the sampling rate and the A/D
converter supplied.
The DC1565A should not be removed, or connected to
the DC1371 while power is applied.
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen‑
cies above 140MHz, refer to the LTC2152 data sheet for a
proper input network. Other input networks may be more
appropriate for input frequencies less that 5MHz.
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full‑scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide Gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Apply the analog input signal of interest to the SMA
connector on the DC1565A demonstration circuit board
marked J4 AINA. This input is capacitively coupled to a
balun transformer ETC1‑1‑13 (lead free part number:
MABA007159‑000000).
+
and GND on the DC1565A.
DEMO MANUAL DC1565A
Encode Clock
NOTE: Apply an encode clock to the SMA connector on
the DC1565A demonstration circuit board marked CLK
As a default the DC1565A is populated to have a single‑
ended input.
For the best noise performance, the encode input must
be driven with a very low jitter, sine wave source. The
amplitude should be large, up to 3V
Using bandpass filters on the clock and the analog input will
improve the noise performance by reducing the wideband
noise power of the signals. Data sheet FFT plots are taken
with 10‑pole LC filters made by TTE (Los Angeles, CA) to
suppress signal generator harmonics, non‑harmonically
related spurs and broadband noise. Low phase noise
Agilent 8644B generators are used for both the clock input
and the analog input.
Digital Outputs
The data outputs, data clock, and frame clock signals are
available on J1 of the DC1565A. This connector follows the
VITA‑57/FMC standard, but all signals should be verified
when using an FMC carrier card other than the DC1371.
Software
The DC1371 is controlled by the PScope™ System Soft‑
ware provided or downloaded from the Linear Technology
website at http://www.linear.com/software/.
To start the data collection software if PScope.exe, is in‑
stalled (by default) in \Program Files\LTC\PScope\, double
click the PScope icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC1565A demonstration circuit is properly connected
to the DC1371, PScope should automatically detect the
DC1565A, and configure itself accordingly.
If everything is hooked up properly, powered and a suit‑
able convert clock is present, clicking the Collect button
should result in time and frequency plots displayed in
the PScope window. Additional information and help for
PScope is available in the DC1371 Quick Start Guide and in
the online help available within the PScope program itself.
+
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or 13dBm.
P‑P
dc1565afa
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