Transmission Time - IDEC LonWorks FC3A-SX5LS1 User Manual

Link Registers and Network Variables
Network variables are allocated to data areas of the link registers as shown below.
b15 b14
L*00
L*01
L*02
L*03
L*04
L*05
L*06
L*07
• Example
Network variables nv_i8[0] and nv_i8[1] are allocated to link register data areas L100.00 through L100.15 as listed below.
L100
b15 b14
MSB
1 0

Transmission Time

The transmission time depends on the network configuration, application program, and user program. It is recommended
that you confirm the transmission time on the actual network system.
Processing transmit and receive data to and from the L
• Processing Transmit Data
The data in link registers are updated each time the CPU module scans the user program. The L
ule reads data from the link registers allocated to transmit data in the
are found in the comparison between the new and old read data, the interface module updates the transmit network vari-
ables of which the data has been changed, and the new data is transmitted to the network.
The refresh cycle of reading from the link register to the interface module is approximately 15 msec. When the data in the
link register is changed within 15 msec, the preceding data is not transmitted to the interface module. Data communication
between the CPU module and the interface module through link registers is not in synchronism with the user program
scanning.
When the CPU is powered up, the transmit data in the link registers are cleared to 0. Consequently, 0 cannot be transmitted
in the first cycle immediately after the CPU is powered up because the transmit network variables are not updated.
• Processing Receive Data
When the interface module receives data from the network, corresponding receive network variables are updated, and the
updated data is stored to the receive data area of link registers in the CPU module.
The refresh cycle of reading from the interface module to the link register is also approximately 15 msec, and is not in syn-
chronism with the user program scanning. When the interface module receives subsequent data within 15 msec, the incom-
ing data is stored in the buffer and is transmitted to link registers every 15 msec. The data in the link register is read each
time the CPU module scans the user program.
b13 b12 b11 b10 b9
nv_i8[1]
nv_i8[3]
nv_i8[5]
nv_i8[7]
nv_o8[1]
nv_o8[3]
nv_o8[5]
nv_o8[7]
nv_i8[1]
b13 b12 b11 b10 b9
0 0 1 1 1
O N C L
PEN ET ONTROLLER
b8 b7 b6 b5
b8 b7 b6 b5
LSB MSB
1 0 1 0
W network is described below:
ON ORKS
OpenNet Controller
W I M
ON ORKS NTERFACE ODULE
L W I
ON ORKS NTERFACE
b4 b3 b2 b1 b0
nv_i8[0]
nv_i8[2]
nv_i8[4]
nv_i8[6]
nv_o8[0]
nv_o8[2]
nv_o8[4]
nv_o8[6]
nv_i8[0]
b4 b3 b2 b1 b0
LSB
0 0 1 1 1
W
ON ORKS
CPU module. When any changes
U ' M
SER S ANUAL
M
ODULE
interface mod-
9