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Speaker
The
has a
system
unit
2
and
speaker's
control circuits
board. The
speaker connects
that attached
a three-pin connector
to
board. The
speaker
drive circuit
watt
power. The control circuits allow
approximately
1/2
of
the speaker
three
be driven
to
direct program control
A
0
generate a pulse
train.
The output
Channel
from
-
programmed
to
generate a
the timer/counter can
The clock input
of
0
with
a program
controlled
three methods
may be performed simultaneously.
channel
Expansion [/0
The
channel
extension
l/O
is
an
cessor
bus.
is,
however, demultiplexed,
It
enhanced
the
addition
of
by
Access
functions.
(DMA)
channel contains
The
l/O
bus
address
with
20
lines,
lines for memory
and
read
l/O
three channels
lines,
of DMA
refresh
control lines,
timing
and
the adapters.
line
a
ground for
the expansion cards:
provided for
and
DC
-12V
These
DC.
functions
connector
too-mil
card tab
pin
with
24
1/4-inch
audio speaker. The
the system
driver
are
on
through a two-wire interface
the system
on
is
capable
of
providing
different ways:
register
bit
may be
toggled
to
the timer/counter
may be
2 of
the speaker.
waveform to
modulated
be
the
I/O
register
bit.
All
by
the
8088 micropro-
of
repowered and
and
Direct Memory
interrupts
data
an 8-bit, bidirectional
six
levels
of
interrupt, control
and
or write, clock
timing
control
lines,
memory
a channel check
a
line,
power
Four voltage levels
are
+5V DC, -5V DC,
+12V
62-
are
a
provided
in
spacing.
available on
line is
"ready"
A
with slow
operation
channel's ready
line is
0
processor-generated
device,
all
cycles take
four 210ns/clock or
read and
l/O
generated
1.05us/byte. Refresh cycles occur once
cycle time
of
a
clocks
72
(approximately
every
clocks or approximately 7%
addressed
devices are
l/O
designed
The channel
is
addressed are
available
channel
check
A
the processor.
conditions to
Non-Masksable
Interrupt
expansion
options
Memory
errors.
channel
is
repowered
The
l/O
all
eight
to
(J1
power
conditions
of
two Low-power
slot. The
l/O
adapters
O
to allow
the
l/O
channel
deVIces.
I/O
memory
or
activated
an
addressed
not
by
read and
memory
840ns/byte.
processor—
All
clocks for
reqUIre five
write
cycles
15us)
andrequne
the bus
bandWIdth.
of
l/O-mapped
using
devnces
so that 768
l/O
the
l/O
expansion cards.
to
exists
for
reporting error
line
results
Activating this
line
the 8088 processor.
to
(NMI)
this
to report parity
line
use
provide sufficient drive
to
slots,
expansion
through J8)
loads per
Schottsky
(LS)
one load.
use
typically
only
the
If
write
four
space.
a
in
under
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