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[/0
channel description
The
a
following
is
description
lines
are
TTL
All
compatible.
oscillator
OSC,
clock
is
a high-speed
It
has a
50% duty cycle.
(14.31818MHz).
It
system clock
CLK,
operates at
one-third
the frequency
It
has a
210ns
(4.77MHz). The
period
of
duty cycle.
Reset
This
used
line is
to
reset
a
power up or during
low line
the
is
synchronized
to
falling
active
high.
address
bits
AO-A 19,
0
These
are used
address
lines
to
the system.
within
The 20
up to
megabyte
of
memory.
1
while A19
the
is
(LSB)
most significant
lines
either the processor
are generated
by
controller. They
active
are
high.
data bits
0
to
7
DO-D7,
These
data bus
lines provide
and
devices.
l/O
memory
while
the
D7 is
most significant
(LSB)
lines
are
active
high.
26
channel.
of
the PC/XT
l/O
70ns
with
a
period
the
and
of
oscillator
has a
33%
clock.
or initialize
system
logic upon
This signal
voltage
outage.
the
edge
clock
and
of
to
19
devices
memory and
l/O
address
lines allow
access
the least
A0 is
significant
bit
These
bit
(MSB).
the
or
DMA
the processor,
bits
to
7 for
0
the least
D0 is
significant
bit
These
bit (MSB).
ALE,
This line is
addresses
0
channel
)
(when
the
with
[/0
CH
This line
information on memory or
When this signal
[/0
CH
This line, normally
ready)
memory cycles.
channel
using this
is
detecting
This
line
cycles. Machine
an integral number
of
[3024307,
These
device requires
having
interrupt
to
high)
processor
103,
command
This
the data
onto
controller. This signal
DMA
O
address
latch enable
the system board
used
on
from
the processor.
it
as
indicator
valid
an
of
a
used
Processor
with AEN).
of ALE.
edge
falling
[/0 channel check
CK,
provides the
processor
devices
active
a
parity error
is
low,
channel ready
I/O
RDY,
can
(ready),
high
device
l/O
a
memory or an
by
devices
allows slower
It
minimum
of difficulty. Any
with
a
should
drive
low
line
it
address
and a
real or write
a
valid
should
never
be held
low
cycles
or memory)
(I/O
of CLK
cycles.
2
requests
interrupt
the processor that
are used
lines
to signal
attention. They
are
the
and
IRQ7
highest
priority
raising an lRQ
is
generated
request
by
and
is
holding
high until
it
it
service
(interrupt
routine).
[/0
read
command
instructs an
|/O
line
may be driven
bus.
It
is
active
to latch valid
available
the
is
to
l/O
processor address
addresses
are latched
with
(error)
parity
the
channel.
l/O
in
activated.
is
be pulled
low
(not
to
lengthen
l/O
or
attach
the
l/O
to
to
device
slow
immediately upon
command.
than
clock
10
more
are extended
by
to
7
an
I/O
with IRQZ
prioritized
the
lowest.
An
having
line (low
the
acknowledged
by
data
device to drive
its
orthe
the processor
by
low.
27
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