Linear Technology DC2183A Demo Manual page 5

DEMO MANUAL DC2183A
Quick start proceDure
JP3: SHUTDOwN: In the RUN position this pin results in
normal operation of the ADC. In the SHDN position the
ADC is powered down and the digital outputs are set in
high impedance state. (Default: RUN or down)
JP4: EEPROM: EEPROM Write Protect. For factory use
only. Should be left in the enable (PROG) position.
JP5: Overflow Test Point: This is a test point for the dif-
ferential overflow signal. This jumper can be installed to
provide a convenient way to probe the overflow signal.
(Default: removed)
JP6: Clock Term: This jumper provides termination volt-
ages for various signaling standards. LVPECL, CML, and
LVDS termination voltages can be selected. The selected
voltage is then used to terminate the clock input through
50Ω resistors. By removing the jumper completely an ex-
ternal voltage can be applied directly to pin 5 of JP6 so an
arbitrary signaling scheme can be used. (Default: LVPECL)
APPLYING POwER AND SIGNALS TO THE DC2183
DEMONSTRATION CIRCUIT
If a DC1371 is used to acquire data from the DC2183,
the DC1371 must FIRST be connected to a powered USB
port and provided an external 5 Volts BEFORE applying
+3.3V to +5.0V across the pins marked VIN and GND on
the DC2183. DC2183 requires at least 3.3V for proper
operation. Regulators on the board produce the voltages
required for the ADC. The DC2183 demonstration circuit
requires up to 800mA. The DC2183 should not be removed
or connected to the DC1371 while power is applied.
4
ANALOG INPUT NETwORk
Apply the analog input signal of interest to the SMA con-
nector on the DC2183 demonstration circuit board marked
J2. In the default setup, the DC2183 has an SMA input that
is meant to be driven with a 50Ω source. The DC2183 is
populated with an input diplexer filter to provide a 50Ω
characteristic impedance over all frequencies. This can
be modified to produce different frequency responses
as needed.
In almost all cases, off-board absorptive filters will be
required on the analog input of the DC2183 to produce
data sheet SNR.
The off-board filter should be located close to the input
of the demo board to avoid reflections from impedance
discontinuities at the driven end of a long transmission line.
Most filters do not present 50Ω outside the passband. In
some cases, 3dB to 10dB pads may be required to make
the filter look more absorptive to obtain low distortion.
ENCODE CLOCk
Apply an encode clock to the SMA connector on the DC2183
demonstration circuit board marked J3. As a default the
DC2183 is populated to have a single ended clock input.
For the best noise performance, the encode input must
be driven with a very low jitter signal generator source.
The amplitude should be as large as possible up to 2V
or 10dBm.
The DC2183 demo board is designed to accept single
ended signals as a default. To modify the DC2183 to ac-
cept a differential signal, remove C31 and populate R18
with a 0Ω resistor. Changing the position of JP6 to CML,
LVDS, or LVPECL selects the proper termination for your
input signal. These SMAs are positioned 0.5" apart to
accommodate LTC differential clock boards.
P–P
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