Hardware Setup - Linear Technology DC2183A Demo Manual

Quick start proceDure

HARDwARE SETUP

SMAs:
J2: Analog Input. Apply a signal to J2 from a 50Ω driver.
Absorptive filters are required for data sheet performance.
J3: Encode Clock Input. Apply a clock signal to this SMA
connector from a 50Ω driver. A filter is required for data
sheet performance.
J4: Encode Clock Input For Differential Signals. By default
the DC2183 is defined to accept a single-ended clock sig-
nal. It can be modified to accept a differential clock signal
through J3 and J4. Some component changes are required,
see the Encode Clock section for more information.
MMCX Connectors:
J1: Optional Analog Input. As a default, this connector
is not populated. Standard MMCX connectors should be
used. To connect this connector to the input of the ADC,
populate R22 and remove J2 completely. By using this
connector, the DC2183 becomes fully compliant with the
FMC specification.
Turrets:
VIN: Positive Input Voltage for the ADC and Digital Buffers.
This voltage feeds a regulator that supplies the proper
voltages for the ADC and buffers. The voltage range for
this turret is 3.3V to 5V.
EXT REF: Optional Reference Voltage. This pin is connected
directly to the SENSE pin of the ADC. Connect EXT REF to
a 1.25V external reference and the external reference mode
is automatically selected. The external reference must be
1.25V ±25mV for proper operation. If no external voltage
is supplied, this pin will be pulled up to 2.5V through a
weak pull-up resistor.
GND: Ground Connection. This demo board only has a
single ground plane. This turret should be tied to the GND
terminal of the power supply being used.
DEMO MANUAL DC2183A
Jumpers:
The DC2183 demonstration circuit should have the fol-
lowing jumper settings as default positions (per Figure 1)
which configure the ADC in serial programming mode.
In the default configuration JP1-JP2 should be left in the
default locations. This will pull PAR/SER low, and the
required pins high through weak pull-up resistors so the
SPI commands can be sent from the PC. If JP1 is set to
PAR then jumpers JP1-JP2 can be configured manually.
JP1: PAR/SER: Selects Parallel or serial programming
mode (Default: Serial)
CMOS/LVDS: In Serial Programming Mode (SER), this
pin should be in the LVDS position to allow for serial data
transfer. (Default: LVDS or up) In the Parallel Program-
ming Mode (PAR), this pin controls the Digital Output
Mode. When this pin is in the CMOS position, the Full-Rate
CMOS Output Mode is enabled. When this pin is in the
LVDS position, the Double Data Rate LVDS Output Mode
(with 3.5mA output current) is enabled. Note: When using
the DC1371, parallel mode DDR LVDS must be selected.
JP2: PGA: In Serial Programming Mode (SER), this pin is
pulled high through a weak pull-up resistor to allow serial
data transfer. In the Parallel Programming Mode (PAR),
this pin controls the Programmable Gain Amplifier front-
end, PGA. In the 1x jumper position a front-end gain of
1x is selected, input range of 2.4V
position a front-end gain of 1.5x is selected, input range
. (Default: 3/2 or up)
of 1.6V
P-P
RAND: In Serial Programming Mode (SER), this pin
is pulled high through a weak pull-up resistor to allow
serial data transfer. In the Parallel Programming Mode
(PAR), this pin becomes the Digital Output Randomization
Control Bit. When this pin is in the OFF position, digital
output randomization is disabled. When this pin is in the
ON position, digital output randomization is enabled. To
decode the randomized data, exclusive-OR each bit with
the least significant bit. This is done for you in PScope
when the randomizer option is toggled. (Default: ON or up).
. In the 3/2 jumper
P-P
dc2183af
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