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LCD mode setting
LCD clock control
register (LCDMD)
register (LCDC)
SEGSET2 SEGSET1
SEGSET0 MDSET1
MDSET0
LCDC3 LCDC2 LCDC1 LCDC0
2
2
f
LCLK
f
/2
LCLK
f
/2
2
LCLK
Clock
generator for
boosting
Booster
circuit
LCD drive voltage controller
CAPH CAPL
Note 64-pin product only.
Figure 3-2. Block Diagram of LCD Controller/Driver
LCD display mode
register (LCDM)
LCDM2
LCDON
SCOC
VLCON
LCDM1
LCDM0
3
2
f
LCD
Prescaler
f
f
f
f
LCD
LCD
LCD
LCD
6
7
8
9
2
2
2
2
LCD
LCDCL
clock
selector
VLCON
Segment voltage
Common voltage
V
V
V
LC1
LC0
LC2
Internal bus
LCD voltage boost control
register 0 (VLCG0)
LCDSEG's 00H
CTSEL1 CTSEL0
GAIN
7
6 5
4
3 2 1 0
Timing
controller
3 2 1 0
selector
LCDON
controller
Segment
Common driver
driver
controller
COM0 COM1 COM2 COM3
S0
Display data memory
Display data memory
LCDSEG's 23H
LCDSEG's 24H
-------
7
6 5
4
3 2 1 0
7
6 5
4
3 2 1 0
-------
3 2 1 0
3 2 1 0
-------
selector
selector
LCDON
LCDON
-------
-------
-------
-------
Segment
Segment
-------
driver
driver
- - - - - - - - - -
S35
S36
Note
LCDSEG's 27H
-------
7
6 5
4
3 2 1 0
-------
3 2 1 0
-------
selector
LCDON
-------
-------
-------
-------
Segment
-------
driver
- - - - - - - - - -
Note
S39
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