Panasonic S-LINK V Instruction Manual page 14

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bit 3: "Error interruption" sets whether an interruption occurs or not when an error occurs.

When bit 3 is "1" an interruption occurs, and when bit 3 is "0" the interruption does not occur.

In case the error interruption is set to effective, the interruption occurs with OR operation

applied to all error occurrences.

For contents of error, check by "5) HML0 + 48: Error No. / Error state."

Error

Interruption

Note: In case bit 2 (Input change interruption) and bit 3 (Error interruption) are both "1," bit 3 (Error

interruption) has priority. Input change interruption does not occur.

12) HML0 + 50: Board No. setting (BSN)

BSN that is set at "2) Board No. setting switch (SW5)" under "3. Functional Description" can

be read out.

Error occurrence

Occurrence

In order to clear the interruption,

6) Command execution request register

7) Command completion response register

are used.

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