Racal Instruments 2251A Operator's Manual page 50

Universal timer/counter
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3.14.6
*ESE?
3.14.7
*ESR?
3.14.8
*SRE <NRf>Program the mask for the Status Request Enable Register. <NRf> is in the
3.14.9
*STB?
3.14.10 *OPC
3.14.11 *OPC?
3.14.12 *WAI
3.14.13 *TRG
3.14.14 *OPT?
3.14.15 *STA?
3.14.16 When commanded by a GPIB slot 0; The 2251A responds to the GPIB SDC (Selected
Device Clear) and DCL (Device Clear) commands by clearing its input and output buffers.
This aborts any command string processing taking place, and any pending commands are
lost.
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Query the Standard Event Enable Register.
programmed via the *ESE <NRf> command.
Query the Standard Event Status Register. The response will be a base 10
number from 0 to 255 (see Figure 3-1). The Active bits are: Power On,
User Request, Command Error, Execution Error, Query Error, and
Operation Complete.
range of 0 to 255. See Figure 3-1 for the bit value definition.
Query the Status Byte Register. The response will be a base 10 number
from 0 to 255 (see Figure 3-1). The Active Bits are: MSS/RQS, ESB,
MAV, and DDSB. The MSS/RQS, ESB, and DDSB bits are active only if
their corresponding masks are enabled.
This command will respond with the Operation Complete Bit in the ESR
being Set after the 2251A has completed all pending commands. Reading
the ESR will clear the OPC bit.
This command will respond with a 1 after the 2251A has completed all
pending commands.
Wait for the 2251A to complete all pending commands.
Trigger the 2251A to start a measurement. Used with the T1 Command and
the same as sending a T2 command.
Report the Channel C option status. The response is 0 if not installed and
1 if installed.
Return the 2251 (old status) Status byte. See Table 3.18 for the bit
description.
This mask register is
3-21

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