Digital Input/Output - Measurement Computing WebDAQ 316 User Manual

Digital input/output

Table 3. Digital input/output specifica ons
Parameter
Digital type
Number of I/O
Configura on
Power on
condi ons
Pull-up
configura on
Input frequency
range
Input high voltage
threshold
Input low voltage
threshold
Schmi trigger
hysteresis
Input high voltage
limit
Input low voltage
limit
Output voltage
range
Output off state
leakage current
Output sink
current capability
Output transistor
on-resistance
(drain to source)
Note 1. Applying a signal with a frequency higher than this specifica on will adversely affect system
performance and could cause errors.
Note 2. The external pull-up resistor is connected between the digital output bit and an external supply. Adding
an external pull-up resistor connects it in parallel with the internal 100 kΩ pull-up resistor of that par cular
digital input/output bit to the internal 5 V supply. Careful considera on should be made when considering the
external pull-up resistor value and the resultant pull-up voltage produced at the load.
Specifica on
CMOS (Schmi trigger) input / open drain output
One port of 4 bits
Each bit can be independently configured for input or output
Power on reset is input mode
Each bit is pulled up to 5 V with a 100 kΩ resistor
DC – 10 kHz (Note 1)
1.9 V min, 3.6 V max
2.3 V max, 1.0 V min
0.6 V min, 1.7 V max
15 V max
–0.5 V absolute min
0 V recommended min
0 V to +5 V (no external pull up resistor)
0 V to +15 V max (Note
10 µA max
100 mA max (con nuous) per output pin
1.6 Ω
WebDAQ 316 User's Guide
2)
page 23