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Rohm LAPIS SEMICONDUCTOR ML620Q503 User Manual (553 pages)

Brand: Rohm | Category: Microcontrollers | Size: 5 MB

Table of Contents
6
Chapter 1 Overview

18
- Features
  19
- Configuration of Functional Blocks
  23
- Pins
  24
  - Pin Layout
    24
    
    Pin Layout of ML620Q503/Q504 TQFP Package
    24
  - List of Pins
    25
    
    List of Pins of ML620Q503/Q504 TQFP Package
    25
  - Description of Pins
    28
  - Termination of Unused Pins
    31
Chapter 2 CPU and Memory Space

32
- General Description
  33
  - Features
    33
  - Notes When Executing SB/RB Instruction
    33
- Program Memory Space
  34
- Data Memory Space
  35
- Instruction Length
  37
- Data Type
  37
- Description of Registers
  37
  - List of Registers
    37
  - Data Segment Register (DSR)
    37
- Multiplication/Division Coprocessor
  38
Chapter 3 Reset Function

44
- Overview
  45
  - Features
    45
  - Configuration
    45
  - List of Pin
    45
- Description of Registers
  46
  - List of Registers
    46
  - Reset Status Register (RSTAT)
    47
- Description of Operation
  48
  - Cause of Reset
    48
  - Operation of System Reset Mode
    48
Chapter 4 Power Management

50
Chapter 5 Interrupts

70
Chapter 6 General Description

135
- Features
  135
- Configuration
  135
- List of Pins
  137
- Clock Configuration Diagram
  138
- Description of Registers
  139
- Description of Operation
  146
- Time Base Counter
  161
Chapter 7 Overview

162
- Features
  162
- Configuration
  162
- Description of Registers
  163
- Description of Operation
  168
  - Low-Speed Time Base Counter
    168
Chapter 8 Timers

170
- Overview
  171
  - Features
    171
  - Configuration
    171
- Description of Registers
  173
- Description of Operation
  181
  - Normal Timer Mode Operation
    181
  - One Shot Timer Mode Operation
    182
  - 16Bit Timer Mode
    182
Chapter 9 Function Timer(FTM)

183
- General Description
  184
  - Features
    184
  - Configuration
    185
  - List of Pins
    186
- Description of Registers
  187
- Description of Operation
  212
  - Common Sequence
    212
  - Counter Operation
    214
    
    Starting/Stopping Counting by Software
    214
    
    Starting/Stopping Counting by Triggerevent
    214
  - TIMER Mode Operation
    215
    
    Output Waveform in TIMER Mode
    215
  - PWM1 Mode Operation
    218
    
    Output Waveform in PWM1 Mode
    218
  - PWM2 Mode Operation
    220
    
    Outputwaveform in PWM2 Mode
    220
  - CAPTURE Mode Operation
    223
    
    Measurement Example in the Capturemode
    223
  - Event/Emergency Stop Trigger Control
    225
    
    Trigger Signal
    225
    
    Start/Stop Operations by Eventtrigger
    226
    
    Emergency Stopoperation
    227
  - Output at Counter Stop
    228
  - Changing Period, Event A/B, and Dead Time During Operation
    229
  - Interrupt Source
    230
Chapter 10 Watchdog Timer

231
- Overview
  232
  - Features
    232
  - Configuration
    232
- Description of Registers
  233
- Description of Operation
  236
  - The Process Example When Not Using Watchdog Timer
    238
Chapter 11 Synchronous Serial Port

239
- Overview
  240
  - Features
    240
  - Configuration
    240
  - List of Pins
    240
- Description of Registers
  241
  - List of Registers
    241
  - Serial Port Control Register (SIO0CON)
    241
  - Serial Port Mode Register (SIO0MOD)
    244
- Description of Operation
  246
  - Transmit Operation
    246
  - Receive Operation
    248
  - Transmit/Receive Operation
    250
Chapter 12 Synchronous Serial Port with FIFO (SSIOF)

251
- General Description
  252
  - Features
    252
  - Configuration
    253
- Description of Registers
  254
- Description of Operation
  270
  - Master Mode and Slave Mode
    270
  - Control of Polarity and Phase of Serial Clock
    270
  - Data Transfer Timing When SF0CPHA Is "0
    270
  - Serial Clock Baud Rate
    271
  - Transfer Size
    272
  - Transfer Interval Setting
    273
  - Transmit Operation (Master Mode)
    275
  - Receive Operation (Master Mode)
    276
  - FIFO Operation
    277
  - Write Overflow
    277
  - Overrun Error
    277
  - FIFO Clearance
    277
  - Mode Fault (MDF)
    279
  - Interrupt Source
    280
    
    SSIOF Interrupt Source
    280
    
    Clear SSIOF Interrupt
    280
    
    SSIOF Interrupt Timing
    280
    
    Interrupt Processing Flow
    281
  - Hi-Z Operation
    282
  - Interval from SF0MST Setting to Transfer Start
    282
  - Pin Settings
    282
Chapter 13 UART

283
- General Description
  284
  - Features
    284
  - Configuration
    284
- Description of Registers
  285
- Description of Operation
  294
  - Transfer Data Format
    294
  - Baud Rate
    295
  - Transmitted Data Direction
    296
  - Transmit Operation
    297
  - Receive Operation
    299
    
    Detection of Start Bit
    301
    
    Sampling Timing
    301
    
    Receive Margin
    302
Chapter 14 UART with FIFO (UARTF)

303
- General Description
  304
  - Features
    304
  - Configuration
    305
  - List of Pins
    306
- Description of Registers
  306
- Description of Operation
  319
  - Data Transmission
    319
  - Data Reception
    320
  - Baud Rate Clock Generation
    322
  - FIFO Mode
    323
  - FIFO Polled Mode
    324
  - Error Status
    325
  - Reset by Block Control Register
    326
Chapter 15 I 2 C Bus Interface

327
- General Description
  328
  - Features
    328
  - Configuration
    328
  - List of Pins
    328
- Description of Registers
  329
- Description of Operation
  338
  - Communication Operation Mode
    338
    
    Start Condition
    338
    
    Restart Condition
    338
    
    Slave Address Transmit Mode
    338
    
    Data Transmit Mode
    338
    
    Data Receive Mode
    338
    
    Control Register Setting Wait State
    339
    
    Stop Condition
    339
  - Operation Waveforms
    342
  - Pin Settings
    343
Chapter 16 Port XT

344
- General Description
  345
  - Features
    345
  - Configuration
    345
  - List of Pins
    345
- Description of Registers
  346
  - List of Registers
    346
  - Port XT Data Register (PXTD)
    347
  - Port XT Direction Register (PXTDIR)
    348
- Description of Operation
  349
  - Input Port Function
    349
  - Primary Function Other than Input Port
    349
Chapter 17 17. Port0 ............................................................................................................................................. 17-1

351
- Overview
  351
  - Features
    351
  - Configuration
    351
  - List of Pins
    352
- Description of Registers
  353
  - List of Registers
    353
  - Port 0 Data Register (P0D)
    354
  - Port 0 Direction Register (P0DIR)
    355
- Description of Operation
  360
Chapter 18 Port1

362
- Overview
  362
  - Features
    362
  - Configuration
    362
  - List of Pins
    363
- Description of Registers
  363
  - List of Registers
    363
  - Port 1 Data Register (P1D)
    364
  - Port 1 Direction Register (P1DIR)
    365
- Description of Operation
  367
  - Input/Output Port Function
    367
  - Other Function
    367
Chapter 19 Port2

368
- Overview
  369
  - Features
    369
  - Configuration
    369
- Description of Registers
  371
  - List of Registers
    371
  - Port 2 Data Register (P2D)
    372
  - Port 2 Direction Register (P2DIR)
    373
- Description of Operation
  378
Chapter 20 Port 3

379
- General Description
  380
  - Features
    380
  - Configuration
    381
  - List of Pins
    382
- Description of Registers
  383
  - List of Registers
    383
  - Port 3 Data Register (P3D)
    384
  - Port 3 Direction Register (P3DIR)
    386
  - Port 3 Control Register (P3CON)
    388
  - Port 3 Mode Register (P3MOD)
    391
- Description of Operation
  394
Chapter 21 Port 4

395
- General Description
  396
  - Features
    396
  - Configuration
    397
  - List of Pins
    398
- Description of Registers
  399
  - List of Registers
    399
  - Port 4 Data Register (P4D)
    400
  - Port 4 Direction Register (P4DIR)
    402
  - Port 4 Control Register (P4CON)
    403
  - Port 4 Mode Register (P4MOD)
    406
- Description of Operation
  409
Chapter 22 Port5

412
- Configuration
  412
- List of Pins
  413
- Description of Registers
  414
  - List of Registers
    414
  - Port 5 Data Register (P5D)
    415
  - Port 5 Direction Register (P5DIR)
    417
  - Port 5 Control Register (P5CON)
    419
  - Port 5 Mode Register (P5MOD)
    422
- Description of Operation
  425
  - Primary Function Other than Input/Output Port
    425
  - Secondary to Quartic Functions
    425
Chapter 23 Melody Driver

426
- Overview
  427
  - Features
    427
  - Configuration
    427
  - List of Pins
    427
- Description of Registers
  428
- Description of Operation
  433
  - Operation of Melody Output
    433
  - Example of Using Melody Circuit
    434
  - Tempo Codes
    435
  - Scale Codes
    437
  - Operations of Buzzer Output
    438
Chapter 24 RC Oscillation Type A/Dconverter (RC-ADC)

439
- General Description
  440
  - Features
    440
  - Configuration
    440
  - List of Pins
    441
- Description of Registers
  442
  - List of Registers
    442
  - RC-ADC Mode Register (RADMOD)
    445
  - RC-ADC Control Register (RADCON)
    447
- Description of Operation
  448
Chapter 25 Successive Approximation Type A/Dconverter (SA-ADC)

463
- General Description
  463
  - Features
    463
  - Configuration
    463
- Description of Registers
  465
- Description of Operation
  475
Chapter 26 26. Analog Comparator....................................................................................................................... 26-1

480
- Overview
  480
  - Features
    480
  - Configuration
    480
  - List of Pins
    480
- Description of Registers
  481
- Function Description
  485
  - Comparator Function
    485
  - Supervisor Mode
    485
  - Single Mode
    486
  - Singlemonitor Mode
    488
Chapter 27 Flash Memory Control

489
- General Description
  490
  - Features
    490
- Description of Registers
  491
  - Flash Data Register (FLASHD)
    493
  - Flash Control Register (FLASHCON)
    494
  - Flash Acceptor (FLASHACP)
    495
  - Flash Segment Register (FLASHSEG)
    495
  - Flash Self Register (FLASHSLF)
    496
  - Remap Address Register (REMAPADD)
    497
- Description of Operation
  498
  - Address Setting for Erase
    499
  - Data Flash Rewriting
    500
  - Program Memory Rewrite (ISP Function)
    500
  - Boot Area Remap Function by Software
    501
  - Boot Area Remap Function by Hardware
    502
  - Notes of the Program after Remapping
    503
  - Sample Program
    504
Chapter 28 Voltage Level Supervisor

505
- General Description
  506
  - Features
    506
  - Configuration
    506
- Description of Registers
  507
Chapter 29 29. LLD Circuit ..................................................................................................................................... 29-1

518
- General Description
  518
  - Features
    518
- Description of Resister
  518
- Description of Operation
  518
Chapter 30 On-Chip Debug Function

519
- Overview
  520
- Method of Connecting to On-Chip Debug Emulator
  520
- Flash Memory Rewrite Function
  521
- Appendixes
  522
Appendix A Registers

523
Appendix B Package Dimensions

532
Appendix C Electrical Characteristics

551
Appendix D Application Circuit Example

551
- Revision History
  552

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Rohm LAPIS SEMICONDUCTOR ML620Q503 Manuals

Rohm LAPIS SEMICONDUCTOR ML620Q503 User Manual (553 pages)

Table of Contents

Chapter 1 Overview

Chapter 2 CPU and Memory Space

Chapter 3 Reset Function

Chapter 4 Power Management

Chapter 5 Interrupts

Chapter 6 General Description

Chapter 7 Overview

Chapter 8 Timers

Chapter 9 Function Timer(FTM)

Chapter 10 Watchdog Timer

Chapter 11 Synchronous Serial Port

Chapter 12 Synchronous Serial Port with FIFO (SSIOF)

Chapter 13 UART

Chapter 14 UART with FIFO (UARTF)

Chapter 15 I 2 C Bus Interface

Chapter 16 Port XT

Chapter 17 17. Port0 ............................................................................................................................................. 17-1

Chapter 18 Port1

Chapter 19 Port2

Chapter 20 Port 3

Chapter 21 Port 4

Chapter 22 Port5

Chapter 23 Melody Driver

Chapter 24 RC Oscillation Type A/Dconverter (RC-ADC)

Chapter 25 Successive Approximation Type A/Dconverter (SA-ADC)

Chapter 26 26. Analog Comparator....................................................................................................................... 26-1

Chapter 27 Flash Memory Control

Chapter 28 Voltage Level Supervisor

Chapter 29 29. LLD Circuit ..................................................................................................................................... 29-1

Chapter 30 On-Chip Debug Function

Appendix A Registers

Appendix B Package Dimensions

Appendix C Electrical Characteristics

Appendix D Application Circuit Example

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