Fsin Domain Clocking; Fsout Domain Clocking; Figure 14.Fundamental Mode Crystal Configuration; Table 1. Common Dai_Mclk Frequencies - Cirrus Logic CS44800 Manual

4.3.1

FsIn Domain Clocking

Common DAI_MCLK frequencies and sample rates are shown in
Mode
(sample-rate range)
DAI_MCLK/LRCK Ratio −>
Single Speed
(4 to 50 kHz)
DAI_MCLK/LRCK Ratio −>
Double Speed
(50 to 100 kHz)
DAI_MCLK/LRCK Ratio −>
Quad Speed
(100 to 200 kHz)
4.3.2

FsOut Domain Clocking

To ensure the highest quality conversion of PWM signals, the CS44800 is capable of operating from a
fundamental mode or 3
to 54 MHz. If XTI is being directly driven by a clock signal, XTO can be left floating or tied to ground
through a pull-down resistor and the internal oscillator should be powered down using the PDN_XTAL bit
in register 02h.
Y1
DS632F1
Sample
Rate
(kHz)
256x
32 8.1920
44.1 11.2896
48 12.2880
128x
64 8.1920
88.2 11.2896
96 12.2880
64x
176.4 n/a
192 n/a

Table 1. Common DAI_MCLK Frequencies

rd
overtone crystal, or a clock signal attached to XTI, at a frequency of 24.576 MHz
Figure 14. Fundamental Mode Crystal Configuration
Table
DAI_MCLK (MHz)
384x 512x
12.2880 16.3840
16.9344 22.5792
18.4320 24.5760
192x 256x
12.2880 16.3840
16.9344 22.5792
18.4320 24.5760
96x 128x
n/a 22.5792
n/a 24.5760
XTI
C1
XTO
C2
CS44800
1.
768x 1024x
24.5760 32.7680
33.8688 45.1584
36.8640 49.1520
384x 512x
24.5760 32.7680
33.8688 45.1584
36.8640 49.1520
192x 256x
33.8688 45.1584
36.8640 49.1520
25