Table 16. Channel Delay Settings - Cirrus Logic CS44800 Manual

The Channel Delay bits allow delay adjustment of each of the PWMOUT differential signal pairs, PW-
MOUTAx+/PWMOUTAx- from the associated PWMOUTBx+/PWMOUTBx-. The value of this register de-
termines the amount of delay inserted in the output path. The effective delay is calculated by multiplying
the register value by the period of the PWM_MCLK. This parameter can only be changed when all mod-
ulators and associated logic are in the power-down state by setting the PDN bit in the register
figuration and Power Control (address 02h)" on page 51
PDN is not set will be ignored.
DS632F1
Binary Code Delay Setting(multiply by PWM_MCLK period)
00000
00110
11000
11111

Table 16. Channel Delay Settings

to a 1b. Attempts to write this register while the
0 - no delay
6
24
31
CS44800
"Clock Con-
71