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Bosch TTCAN User Manual

Ttcan ip module user's manual
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User's Manual

TTCAN

Revision 1.6
TTCAN
IP Module
User's Manual
Revision 1.6
11.11.02
Robert Bosch GmbH
Automotive Electronics
Semiconductors and Integrated Circuits
Digital CMOS Design Group
11.11.02
BOSCH

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Summary of Contents for Bosch TTCAN

  • Page 1: Ttcan

    User’s Manual TTCAN Revision 1.6 TTCAN IP Module User’s Manual Revision 1.6 11.11.02 Robert Bosch GmbH Automotive Electronics Semiconductors and Integrated Circuits Digital CMOS Design Group 11.11.02 BOSCH...
  • Page 2 User’s Manual TTCAN Revision 1.6 Copyright Notice and Proprietary Information Copyright © 1998, 1999, 2002 Robert Bosch GmbH. All rights reserved. This software and manual are owned by Robert Bosch GmbH, and may be used only as authorized in the license agreement controlling such use.

  • Page 3: Table Of Contents

    TTCAN ........
  • Page 4 TTCAN 3.4. Message Handler Registers ......... . 27 3.4.1.
  • Page 5 5.7. TTCAN Interrupt and Error Handling ........

  • Page 6: About This Document

    1.3 Scope This document describes the TTCAN IP module and its features from the application programmer’s point of view. All information necessary to integrate the TTCAN IP module into an user-defined ASIC is located in the ‘Module Integration Guide’. 1.4 References This document refers to the following documents.

  • Page 7: Terms And Abbreviations

    TTCAN 1.5 Terms and Abbreviations This document uses the following terms and abbreviations. Term Meaning Controller Area Network Bit Stream Processor Bit Timing Logic Cyclic Redundancy Check Register Data Length Code Error Management Logic Frame Synchronisation Entity Finite State Machine...

  • Page 8: Functional Description

    2. Functional Description 2.1 Functional Overview The TTCAN is a CAN IP module that can be integrated as stand-alone device or as part of an ASIC. It is described in VHDL on RTL level, prepared for synthesis. It consists of the components (see figure 1) CAN_Core, Message RAM, Message Handler, Control Registers,...

  • Page 9: Block Diagram

    Message RAM. Module Interface Up to now the TTCAN module is provided with three different interfaces. An 8-bit interface for the Motorola HC08 controller a 16-bit interface to the TI TMS470 controller, and two 16-bit interfaces to the AMBA APB bus from ARM. They can easily be replaced by a user-defined module interface.

  • Page 10: Operating Modes

    Configuration Mode requires that both bits Init and CCE are set. 2.3.2 CAN Message Transfer Once the TTCAN is initialized and Init is reset to zero, the TTCAN’s CAN_Core synchronizes itself to the CAN bus and starts the message transfer in the configured TTMode.

  • Page 11: Disabled Automatic Retransmission

    When a transmission failed (lost arbitration or error) bit NewDat remains set. To restart the transmission the CPU has to set TxRqst back to one . Note : It is not necessary to set DAR if the TTCAN is in time triggered operating mode. 2.3.4 Test Mode The Test Mode is entered by setting bit Test in the CAN Control Register to one .

  • Page 12: Disable Watchdog Mode

    Register bit WdOff to one and the Application_Watchdog_Limit AppWdL to 0x00. When bit Test in the CAN Control Register is reset, WdOff is also reset if the TTCAN is in time triggered operating mode; if the TTCAN is in event driven CAN mode, WdOff is remains set and the TT Application Watchdog remains disabled (emulating the C_CAN function).

  • Page 13: Loop Back Mode

    Silent to one at the same time. This mode can be used for a “Hot Selftest”, meaning the TTCAN hardware can be tested without affecting a running CAN system connected to the pins CAN_TX and CAN_RX. In this mode the CAN_RX pin is disconnected from the CAN_Core and the CAN_TX pin is held recessive .

  • Page 14: Software Control Of Pin Can_Tx

    ‘0’. The No Message RAM Mode is a hardware test mode that allows to evaluate the TTCAN IP RTL code in FPGA types that do not support the TTCAN’s Message RAM structure.

  • Page 15: Programmer's Model

    TTCAN 3. Programmer’s Model The TTCAN module allocates an address space of 256 bytes. The registers are organized as 16-bit registers, with the high byte at the odd address and the low byte at the even address. The two sets of interface registers (IF1 and IF2) control the CPU access to the Message RAM.

  • Page 16: Hardware Reset Description

    Figure 5: TTCAN Register Summary 3.1 Hardware Reset Description After hardware reset, the registers of the TTCAN hold the values described in figure 5. Additionally the Bus_Off state is reset and the output CAN_TX is set to recessive (HIGH). The value 0x0001 (Init = ‘1’) in the CAN Control Register enables the software initialisation.

  • Page 17: Can Protocol Related Registers

    TTCAN 3.2 CAN Protocol Related Registers These registers are related to the CAN protocol controller in the CAN Core. They control the operating modes and the configuration of the CAN bit timing and provide status information. 3.2.1 CAN Control Register (addresses 0x01 & 0x00)

  • Page 18: Status Register (Addresses 0X03 & 0X02)

    TTCAN 3.2.2 Status Register (addresses 0x03 & 0x02) BOff Bus_Off Status one The CAN module is in Bus_Off state. zero The CAN module is not Bus_Off. EWarn Warning Status one At least one of the error counters in the EML has reached the error warning limit of 96.

  • Page 19: Status Interrupts

    TTCAN The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to ‘0’ when a message has been transferred (reception or transmis- sion) without error. The unused code ‘7’ may be written by the CPU to check for updates.

  • Page 20: Brp Extension Register (Addresses 0X0D & 0X0C)

    This register is only writable if bits CCE and Init in the CAN Control Register are set. Note : The width of BRPE may be increased to more than its default width of 4 bits in particular imple- mentations of the TTCAN IP module width a high module clock frequency. 3.3 Message Interface Register Sets...

  • Page 21: Ifx Command Mask Registers

    TTCAN single transfer. This transfer, performed in parallel on all selected parts of the Message Object, guarantees the data consistency of the CAN message. Figure 6 shows the structure of the two Interface Register sets. The function of the two Interface Register sets is identical (except for test mode NoRAM). The second interface register set is provided to serve application programming.

  • Page 22: Direction = Read

    TTCAN ClrIntPnd Clear Interrupt Pending Bit Note : When writing to a Message Object, this bit is ignored. TxRqst/NewDatAccess Transmission Request Bit set TxRqst bit zero TxRqst bit unchanged Note : If a transmission is requested by setting TxRqst/NewDat in the IFx Command Mask Register, bit TxRqst in the IFx Message Control Register will be ignored.

  • Page 23: Ifx Message Buffer Registers

    TTCAN 6 CAN_CLK periods, the transfer between the Interface Register and the Message RAM has completed and the Busy bit is cleared to ‘0’. The upper limit of the wait time occurs when the message transfer coincides with a CAN message transmission, acceptance filtering, or message storage.

  • Page 24: Ifx Message Control Registers

    TTCAN 3.3.3.3 IFx Message Control Registers IF1 Message Control Register (addresses 0x1D & 0x1C) NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst EoB MSC2-0 DLC3-0 IF2 Message Control Register NewDat MsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst EoB MSC2-0 DLC3-0 (addresses 0x4D &...
  • Page 25 Note : The Message Status Count is status information that is generated for periodic Message Objects in Time Triggered Communication (ISO11898-4). It has no function in Event Driven CAN Com- munication (ISO11898-1) and for arbitrating Message Objects in TTCAN. BOSCH User’s Manual...
  • Page 26 This Message Object is not waiting for transmission. Note : In TTCAN mode, there are two types of transmit Message Objects. When NewDat is set and TxRqst is reset, the message will be transmitted periodically at each Transmit_Trigger for this message, without changing NewDat or TxRqst.

  • Page 27: Message Handler Registers

    Object’s interrupt priority decreases with increasing message number. A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status Interrupt is cleared by reading the Status Register. The TTCAN Interrupt is cleared by reading the TTCAN Interrupt Vector Register.

  • Page 28: Transmission Request Registers

    TTCAN 3.4.2 Transmission Request Registers Transmission Request 1 Register (addresses 0x81 & 0x80) Transmission Request 2 Register (addresses 0x83 & 0x82) TxRqst32-1Transmission Request Bits (of all Message Objects) The transmission of this Message Object is requested and is not yet done.

  • Page 29: Message Valid 1 Register

    3.5.2 IF1 Data B1 and B2 Registers for Trigger Memory Access The trigger data of the TTCAN system matrix is stored in the Trigger Memory. The Trigger Memory is accessed via the IF1 Data B1 and B2 Registers. The data transfer is controlled by the Trigger Memory Access Register.

  • Page 30: Tt Operation Mode Register (Addresses 0X29 & 0X28)

    The node is a (potential) Time Master. The node will never be a Time Master. The priority of this node (0 is highest priority). The node operates in TTCAN Level 2. The node operates in TTCAN Level 1. - 30/77 - Revision 1.6...

  • Page 31: Tt Matrix Limits1 Register (Addresses 0X2B & 0X2A)

    Note : The CPU may write to the TT Operation Mode register only during initialisation (Init and CCE are set). Configuration Mode enables the write access to the other TTCAN configuration regis- ters. The whole CAN module remains in initialisation mode while TTMode is TTMode_1, “Con- figuration Mode”, even if Init is reset.

  • Page 32: Tt Application Watchdog Limit Register (Addresses 0X2F & 0X2E)

    The application watchdog is served by reading the high byte of the register. When the watchdog is not served in time, the bit Bark is set, all TTCAN communication is stopped, and the TTCAN module is set into silent mode. The TTCAN module is restarted by writing Bark to ‘0’...
  • Page 33 TTCAN Any number of bits may be written to ‘0’ (cleared) at the same time. Bits that are written to ‘1’ remain unchanged. ApW WTr Config Error Set when an error is found in the Trigger List. Application Watchdog Set when the application watchdog was not served in time.

  • Page 34: Tt Global Time Register (Addresses 0X35 & 0X34)

    Global_Time Global Time of the TTCAN network 0x0000-0xFFFF Actual Global Time value. 3.5.10 TT Cycle Time Register (addresses 0x37 & 0x36) Cycle_Time Cycle Time of the TTCAN basic cycle 0x0000-0xFFFF Actual Cycle Time value. 3.5.11 TT Local Time Register (addresses 0x39 & 0x38) Local_Time Local Time of the TTCAN node 0x0000-0xFFFF Actual Local Time value.

  • Page 35: Tt Cycle Count Register (Addresses 0X3D & 0X3C)

    ‘1’. Note : The actual value of TUR may be changed by the clock drift compensation function of TTCAN Level 2 in order to adjust the node’s local view of the NTU to the time master view of the NTU.

  • Page 36: Tur Denominator Configuration Register (Addresses 0X59 & 0X58)

    0x0F000-0x20FFF NumAct[17 0]. 0x21000 There is no drift compensation in TTCAN Level 1, NumAct = NumCfg. In TTCAN Level 2, the drift between local clock and the time master’s local clock is calculated. The drift is compensated when the Synchronisation Deviation (difference between NumCfg and the...

  • Page 37: Tt Global Time Preset Register (Addresses 0X65 & 0X64)

    Local clock speed not synchronised to Time Master clock speed. Global Time in phase with Time Master. Global Time not valid (always true in TTCAN Level 1). The automatic clock calibration in TTCAN Level2 is enabled. The automatic clock calibration in TTCAN Level2 is disabled.

  • Page 38: Tt Sync_Mark Register (Addresses 0X69 & 0X68)

    TTCAN Time Mark Compare Disable External Time Mark Port zero External Clock Synchronisation The External Clock Synchronisation takes effect when ‘1’ is written to ECS. ECS will always be read as ‘0’ Stop Watch Source (when edge is detected at the STOP_WATCH_TRIGGER pin)

  • Page 39: Tt Time Mark Register (Addresses 0X6D & 0X6C)

    TTCAN 3.5.22 TT Time Mark Register (addresses 0x6D & 0x6C) TMark Time Mark 0x0000-0xFFFF An interrupt is generated when the time base indicated by TMC Note : The Time Mark register can only be written while the time mark interrupt is disabled by TMC 3.5.23 TT Gap Control Register (addresses 0x6F &...
  • Page 40 User’s Manual TTCAN Revision 1.6 basic cycle will continue until its last time window. The time after the last time window is the Gap time. In nodes that are time slaves, the Gap bit will remain at ‘0’. In the actual time master and in potential time masters, the Gap bit will be set when the last basic cycle has finished and the...

  • Page 41: Can Application

    TTCAN 4. CAN Application The TTCAN module can emulate a C_CAN module in ordinary event driven ISO 11898-1 CAN communication. C_CAN software can also be used for the TTCAN, provided that the TTCAN’s application watchdog is disabled in the configuration phase, as described in chapter 2.3.4.2.

  • Page 42: Transmission Of Messages In Event Driven Can Communication

    (NewDat = ‘0’) since the start of the transmission, the TxRqst bit will be reset. If TxIE is set, IntPnd will be set after a successful transmission. If the TTCAN has lost the arbitration or if an error occurred during the transmission, the message will be retransmitted as soon as the CAN bus is free again.

  • Page 43: Acceptance Filtering Of Received Messages

    TTCAN 4.1.3 Acceptance Filtering of Received Messages When the arbitration and control field (Identifier + IDE + RTR + DLC) of an incoming message is completely shifted into the shift register of the CAN_Core, the Message Handler FSM starts the scanning of the Message RAM for a matching valid Message Object.

  • Page 44: Receive / Transmit Priority

    The configuration of the bit timing requires that the CCE bit in the CAN Control Register is set additionally to Init. This is not required for the configuration of the Message Objects. The configuration of the TTCAN functions (see chapter 5) requires that TTMode is set to “Configuration Mode”.

  • Page 45: Configuration Of The Bit Timing

    Point. The (Re-)Synchronisation Jump Width (SJW) defines how far a resynchronisation may move the Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase errors. BOSCH User’s Manual . The TTCAN’s system clock f Nominal CAN Bit Time Phase_Seg1 - 45/77 - Revision 1.6...

  • Page 46: Propagation Time Segment

    TTCAN A given bit rate may be met by different bit time configurations, but for the proper function of the CAN network the physical delay times and the oscillator’s tolerance range have to be considered. Parameter Range Sync_Seg Prop_Seg Phase_Seg1...

  • Page 47: Phase Buffer Segments And Synchronisation

    (Prop_Seg to short) that causes sporadic bus errors. Some CAN implementations provide an optional 3 Sample Mode The TTCAN does not. In this mode, the CAN bus input signal passes a digital low-pass filter, using three samples and a majority logic to determine the valid bit value.
  • Page 48 TTCAN When the phase error of the edge which causes Resynchronisation is negative, Phase_Seg2 is shortened. If the magnitude of the phase error is less than SJW, Phase_Seg2 is shortened by the magnitude of the phase error, else it is shortened by SJW.
  • Page 49 TTCAN In the first example an edge from recessive to dominant occurs at the end of Prop_Seg. The edge is “ late ” since it occurs after the Sync_Seg. Reacting to the “ late ” edge, Phase_Seg1 is lengthened so that the distance from the edge to the Sample Point is the same as it would have been from the Sync_Seg to the Sample Point if no edge had occurred.

  • Page 50: Oscillator Tolerance Range

    125 kBit/s (bit time = 8 s) with a bus length of 40 m. 4.2.1.5 Configuration of the CAN Protocol Controller In most CAN implementations and also in the TTCAN, the bit timing configuration is programmed in two register bytes. The sum of Prop_Seg and Phase_Seg1 (as TSEG1) is combined with Phase_Seg2 (as TSEG2) in one byte, SJW and BRP are combined in the other byte (see figure 13).

  • Page 51: Calculation Of The Bit Timing Parameters

    flag, or idle) is called the Information Processing Time (IPT). The IPT is application specific but may not be longer than 2 t ; the TTCAN’s IPT is 0 t . Its length is the lower limit of the programmed length of Phase_Seg2. In case of a synchronisa- tion, Phase_Seg2 may be shortened to a value less than IPT, which does not affect bus timing.

  • Page 52: Example For Bit Timing At High Baudrate

    TTCAN If more than one configuration is possible, that configuration allowing the highest oscillator tolerance range should be chosen. CAN nodes with different system clocks require different configurations to come to the same bit rate. The calculation of the propagation time in the CAN network, based on the nodes with the longest delay times, is done once for the whole network.

  • Page 53: Example For Bit Timing At Low Baudrate

    TTCAN 4.2.1.8 Example for Bit Timing at low Baudrate In this example, the frequency of CAN_CLK is 2 MHz, BRP is 1, the bit rate is 100 KBit/s. delay of bus driver delay of receiver circuit delay of bus line (40m)

  • Page 54: Configuration Of A Transmit Object For Data Frames

    TTCAN The CPU may poll all MessageObject’s NewDat and TxRqst bits in parallel, in the New Data x Registers and in the Transmission Request x Registers. Polling is made easier if all Transmit Objects are grouped at the low numbers, all Receive Objects are grouped at the high numbers.

  • Page 55: Configuration Of A Fifo Buffer

    TTCAN The Arbitration Registers (ID28-0 and Xtd bit) are given by the application. They define the identifier and type of accepted received messages. If an 11-bit Identifier (“Standard Frame”) is used (Xtd = ‘0’), it is programmed to ID28 - ID18, ID17 - ID0 can then be disregarded. When a Data Frame with an 11-bit Identifier is received, ID17 - ID0 will be set to ‘0’.

  • Page 56: Can Communication

    Message Object. 4.3 CAN Communication When the initialisation is finished, the TTCAN module synchronises itself to the traffic on the CAN bus. It does an acceptance filtering on received messages and stored those frames that are accepted into the designated Message Objects. The application program has to update the data of the messages to be transmitted and has to enable and request their transmission.

  • Page 57: Updating A Transmit Object

    User’s Manual TTCAN Revision 1.6 The interrupt identifier IntId in the Interrupt Register indicates the cause of the interrupt. When no interrupt is pending, the register will hold the value zero . If the value of the Interrupt Register is different from zero , then there is an interrupt pending and, if IE is set, the interrupt line to the CPU is active.

  • Page 58: Changing A Transmit Object

    TTCAN 4.3.3 Changing a Transmit Object In an application for that the number of Message Objects in the TTCAN module is not sufficient, the Transmit Objects may be managed dynamically. The CPU writes the whole message (Arbitration, Control, and Data) into the Interface Register. The Command Mask Register is set to 0x00B7 for the transfer of the contents into the designated Message Object.
  • Page 59 TTCAN Status Change Interrupt Handling Figure 17: CPU Handling of a FIFO Buffer (Interrupt Driven) BOSCH User’s Manual START Message Interrupt Read Interrupt Pointer case Interrupt Pointer 0x8000h else IFx Command Mask = 0x007F MessageNum = Interrupt Pointer Write MessageNum to IFx Command Request...

  • Page 60: Ttcan Application

    In TTCAN Level 1 NTU is the nominal CAN bit time. In TTCAN Level 2 NTU is a fraction of the physical second. The length of the NTU is defined by the Time Unit Ratio, TUR. TUR is the ratio between the length of an NTU and the length of the FSE specific basic time unit, the system clock period.

  • Page 61: Message Scheduling

    Time Master fails, should correspond to their master priority, even with maximum clock drift. L2 decides whether the node operates in TTCAN Level 1 or in TTCAN Level 2. In one network, all potential Time Masters have to operate in the same level. Time Slaves may operate on Level 1 in a Level 2 network, but not vice versa.

  • Page 62: Trigger Memory

    RDLC specifies the Data Length Code of the Reference Messages transmitted by a potential Time Master. It has to be at least 0x1 for TTCAN Level 1 and 0x4 for TTCAN Level 2. TEW specifies the length of the Tx_Enable Window in NTUs. The Tx_Enable Window is that period of time at the beginning of a Time Window where a transmission may be started.
  • Page 63 Reference Message measured in NTU. The length of the Basic Cycle is Tx_Ref_Trigger’s Time_Mark+(1NTU+1CAN bit time). The Trigger List will be different for all nodes in the TTCAN network, each node knows only the Tx_Triggers for its own transmit messages, the Rx_Triggers for those receive messages that are processed by this node, and the Triggers concerning the Reference Messages.

  • Page 64: Message Objects

    Message. When a Reference Message is transmitted, the last three bits of the Identifier, the DLC, and the first data byte (TTCAN Level 1) or the first three data bytes (TTCAN Level 2) will be provided by the FSE, the rest of the Reference Message is provided by the first Message Object.

  • Page 65: Event Driven Transmit Message

    Message Object. 5.2 TTCAN Schedule Initialisation The synchronisation to the TTCAN message schedule starts when the Operation Mode is switched from Configuration Mode to either Strictly Time Triggered Operation or to Event Synchronised Time Triggered Operation.

  • Page 66: Ttcan Message Handling

    Rx_Trigger(s) and gives additional means to check whether the received data arrived on time. 5.3.2 Message Transmission In TTCAN, the handling of message to be transmitted is similar as in “Event driven CAN Communication”, see chapter 4.1.2. The differences for periodic messages and event driven messages are described in the following sections.

  • Page 67: Ttcan Gap Control

    Message Object that is not transmitted successfully is lost. 5.4 TTCAN Gap Control In the mode Event Synchronised Time Triggered Operation, the TTCAN message schedule of the System Matrix may be interrupted by Gaps. In those Gaps, all transmissions are stopped and the CAN bus remains idle.
  • Page 68 Ref_Mark and the local time is the cycle time (Cycle Time= Local Time– Ref_Mark). The Global Time exists for TTCAN Level 2 only, in Level 1 it is invalid. After Configuration, a Potential Time Master will use its own Local Time as Global Time. The time master establishes its own local time as global time by transmitting its own Ref_Marks in the Reference Message, as Master_Ref_Marks.

  • Page 69: Ttcan Interrupt And Error Handling

    Time Unit Ratio Figure 20: TTCAN Level 2 Drift Compensation Figure 20 describes how in TTCAN Level 2 each time receiving node compensates the drift between its own local clock and the Time Master’s clock by comparing the length of a Basic Cycle in Local Time and in Global Time.

  • Page 70: Configuration Example

    This is a configuration example for a TTCAN system consisting of three nodes (M0, M1, and S0) operating in TTCAN level 2 at a bit rate of 1 MBit/s. All three nodes have a system clock frequency of 10 MHz, the network time unit NTU is 1 s. Two nodes (M0 and M1) are potential time masters, the third node S0 is operating as a time slave.
  • Page 71 TTCAN The general configuration of the three nodes is identical, there are differences in the Operation Mode, the TT Matrix Limits, the Message RAM, and the Trigger Memory. Note that the CPU has to wait after each write access to the IF1 Command Request Register for the requested transfer to be completed (check of Busy bit).
  • Page 72 TTCAN Register Line 37 1C IF1 Message Control 38 10 IF1 Command Request 39 10 IF1 Command Request 40 10 IF1 Command Request 41 10 IF1 Command Request 42 1A IF1 Arbitration2 43 1C IF1 Message Control 44 10 IF1 Command Request...
  • Page 73 TTCAN Register Line 77 24 IF1 Message Data B2 78 0E Trigger Memory Access 79 22 IF1 Message Data B1 80 24 IF1 Message Data B2 81 0E Trigger Memory Access 82 22 IF1 Message Data B1 83 24 IF1 Message Data B2...
  • Page 74 The application has to serve the Application Watchdog at least once in 65 ms, else the ApW interrupt is set and the TTCAN module enters TT Error Level “Fatal Error”, stopping all communication. This error requires a re-configuration. The Application Watchdog may be disabled during software development.

  • Page 75: Cpu Interface

    6. CPU Interface The interface of the TTCAN module consist of two parts (see figure 21). The Generic Interface which is a fixed part of the TTCAN module and the Customer Interface which can be adapted to the customers requirements.

  • Page 76: Timing Of The Wait Output Signal

    Enabled Interrupt Flag set Figure 23: Timing of interrupt signal CAN_INT. If several interrupt flags of the TTCAN module are set (status interrupt, message interrupts), all interrupt flags have to be reset before the CAN_INT returns to passive level. BOSCH User’s Manual...

  • Page 77: Appendix

    Figure 20: TTCAN Level 2 Drift Compensation ........

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