Texas Instruments ADSDeSer-50EVM User Manual
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Texas Instruments ADSDeSer-50EVM User Manual

Texas Instruments ADSDeSer-50EVM User Manual

Evaluation module
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ADSDeSer 50EVM
Evaluation Module
User's Guide
January 2004
High-Speed Converter Products
SBAU091

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Summary of Contents for Texas Instruments ADSDeSer-50EVM

  • Page 1 ADSDeSer 50EVM Evaluation Module User’s Guide January 2004 High-Speed Converter Products SBAU091...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...
  • Page 3 EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods.
  • Page 4 EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2004, Texas Instruments Incorporated...
  • Page 5 Preface Read This First About This Manual This manual describes the ADSDeSer-50EVM evaluation fixture and how to use it. Throughout this document, the abbreviation EVM and the term evalua- tion module are synonymous with the ADSDeSer-50EVM. Related Documentation From Texas Instruments The following documents provide information regarding Texas Instruments integrated circuits used in the assembly of the ADSDeSer-50EVM.
  • Page 6 Contents FCC Warning This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to sub- part J of part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference.

  • Page 7: Table Of Contents

    Contents Contents Overview ............... . Introduction .
  • Page 8 Contents Figures 2−1. ADSDeSer-50EVM Overview 2−2. Default and Alternate Configurations for Programming the ADSDeSer-50EVM 2−3. Default Configurations for FPGA Pins on the ADSDeSer-50EVM 2−4. Output Connectors for the ADSDeSer-50EVM 2−5. Orientation of Ground Connections for the ADSDeSer-50EVM 3−1. ADSDeSer-50EVM—Layer 1 (Top) 3−2.

  • Page 9: Overview

    Chapter 1 Overview The ADSDeSer-50EVM is an evaluation fixture designed for the ADS527x family of data converters. It is an eight-channel LVDS deserializer. Topic Page Introduction ..........

  • Page 10: Introduction

    Introduction 1.1 Introduction The ADSDeSer-50EVM is designed to interface to the TI low voltage differen- tial signal (LVDS) output data converters with an operating frequency of up to 50MHz and up to eight simultaneous data channels. The ADSDeSer-50EVM provides an easy way to examine the serialized data output from the serialized LVDS data converters by deserializing the data and converting to a standard parallel data port.

  • Page 11: Power Supply

    Power Supply 1.3 Power Supply The ADSDeSer-50EVM requires two supplies for operation: a +3.3V supply for the main board power, and a +1.8V to +3.3V supply for the output driver supply. An onboard regulator supplies +1.5V to power the FPGA.

  • Page 12: Board Configuration

    Chapter 2 Board Configuration This chapter describes the inputs, controls, and circuit design of the ADSDeSer-50EVM in detail. Topic Page I/O Connectors ..........

  • Page 13: I/O Connectors

    I/O Connectors 2.1 I/O Connectors The positions and functions of the ADSDeSer-50EVM connectors are dis- cussed in the following sections. Figure 2−1. ADSDeSer-50EVM Overview JTAG BYPAS S PROG RAM PIN S PUSHBUTTON C ONFIGURATIO N PINS FPG A RESET PUSHBUTTON 2.1.1...

  • Page 14: Fpga And Prom Bypass And Configuration

    J11 and J12 can be used to bypass the PROM and/or bypass the FPGA when programming. The following diagram shows the default and different configu- rations for programming. Figure 2−2. Default and Alternate Configurations for Programming the ADSDeSer-50EVM PROM J 11 J 12...

  • Page 15: Fpga Configuration Pins

    HSWAP_EN 2.1.5 Pushbuttons The ADSDeSer-50EVM has two pushbuttons. S1 (PROGRAM) is used to download from the PROM to the FPGA. When the program is finished down- loading, indicator DS2 will turn on. S2 (FPGA_RST) is used to reset the down-...

  • Page 16: Output Connectors

    Figure 2−4. Output Connectors for the ADSDeSer-50EVM The next diagram shows the orientation of the ground connections with re- spect to the board layout. Figure 2−5. Orientation of Ground Connections for the ADSDeSer-50EVM FPGA Board Configuration...

  • Page 17: Start-Up Sequence

    Step 2: Connect the clock and data outputs to a data capture system (analyzer). Step 3: Apply power to the ADSDeSer-50EVM board and look for the Power On (DS1) LED and DS2 LED to illuminate. If DS2 does not illuminate, press the Program (S1) pushbutton.

  • Page 18: Schematic And Layout

    Chapter 3 Schematic and Layout This chapter contains the complete printed circuit board (PCB) layout, schematic diagram, and bill of materials for the ADSDeSer-50EVM. Note: Board layouts are not to scale. These are intended to show how the board is laid out; they are not intended to be used for manufacturing ADSSer-50EVM PCBs.

  • Page 19: Board Layout

    Board Layout 3.1 Board Layout Figure 3−1. ADSDeSer-50EVM—Layer 1 (Top)
  • Page 20 Board Layout Figure 3−2. ADSDeSer-50EVM—Layer 2 (Power) Schematic and Layout...
  • Page 21 Board Layout Figure 3−3. ADSDeSer-50EVM—Layer 3 (Mid Signal)
  • Page 22 Board Layout Figure 3−4. ADSDeSer-50EVM—Layer 4 (Ground) Schematic and Layout...
  • Page 23 Board Layout Figure 3−5. ADSDeSer-50EVM—Layer 5 (Bottom)

  • Page 24: Schematic

    Schematic 3.2 Schematic Figure 3−6. —Schematic ADSDeSer-50EVM BANK 7 BANK 6 Schematic and Layout...

  • Page 25: Bill Of Materials

    Bill of Materials 3.3 Bill of Materials Table 3−1. Bill of Materials Quantity Comment Description Reference Designator Samtec QSH 040−01−L−D−DP−A Con1 0.1µF Multilayer Ceramic—0402 size C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36,...

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