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Summary of Contents for Teledyne Lecroy PCI Express 2.0 Mid-Bus Probe
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Protocol Solutions Group ® PCI Express 2.0 Mid-Bus Probe for Summit Analyzers Installation and Usage Manual Manual Version 1.1 Generated on: 2/7/2018 6:25 PM...
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The information contained in this document has been carefully checked and is believed to be reliable. However, no responsibility can be assumed for inaccuracies that may not have been detected. Teledyne LeCroy reserves the right to revise the information presented in this document without notice or penalty.
Mid-Bus Probe User Manual. Teledyne LeCroy makes two versions of mid-bus probes, one for Gen1/2 (2.5 and 5 GT/s data rates) and one for Gen3 (2.5, 5 and 8 GT/s data rates). This manual covers only the Gen2 mid-bus probe. See other user manuals for the other mid-bus probes.
The Intel-based mid-bus footprint specification only supplies differential lane signaling and ground reference. Should a reference clock (RefClk) be required a separate connection must be made. Teledyne LeCroy PCI Express protocol analyzers can use a reference clock probe in conjunction with the mid-bus analysis. Each mid-bus probe is equipped with one clock probe.
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 Mechanical Design This section describes footprint dimensions, keepout volumes, and probe pin assignments. 3.1 Probe Footprints The Summit T24 Mid-bus Probe is fully compatible with the standardized mid-bus footprint recommended by the Intel guideline, as shown in the following figures.
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Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 Note: All dimensions are in inches...
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Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 A typical layout of a mid-bus footprint might look something like the following two pictures: Gen1 Mid-Bus Layout Gen2 Mid-Bus Layout PCB Layout...
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Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 Note: All dimensions are in inches...
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Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 A typical layout of a mid-bus footprint might look something like the following two pictures: Gen1 Mid-Bus Layout Gen2 Mid-Bus Layout PCB Layout...
The bus signals captured by the mid-bus probe are connected to a mid-bus probe pod for amplification. This reduces the load imposed by the mid-bus probe on the target system, while allowing a longer cable to attach to the Teledyne LeCroy PCI Express protocol analyzer.
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 3.5 Reference Clock Probe Attachment Should SSC clocking be used in the system under test or if the link varies the bit rate by more than 300ppm, a reference clock tap may be required.
An equivalent Spice model is available via the Teledyne LeCroy Protocol Systems Group support team (psgsupport@teledynelecroy.com) With this unique design, the Teledyne LeCroy mid-bus probes can capture bus traffic signals with amplitudes specified by the PCI Express standard, while introducing only the loss and added jitter that are within the recommended specification in the PCI Express Mid-Bus Probing Footprint and Pinout.
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 4.3 Pin Assignments for x16 Lane Widths For x16 lane widths, two full-size headers are required. The diagrams below show the recommended pin assignments for x16 configurations (keep in mind that any of modifications mentioned in Section 4.2 can be applied, and in addition the lane swizzling feature of the Summit T3-16 and T2-16 systems noted in Section 4.2).
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Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 x16 (in Two Bi-directional Footprints) Mid-Bus Probe Pinout on two Full-size Headers (Summit only)
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 4.4 Pin Assignments for x8 Lane Widths For x8 lane widths, one full-size header is required. The diagram below shows the recommended pin assignments for x8 configurations (keep in mind that any of modifications mentioned in Section 4.2 can be applied, and in addition the lane swizzling feature of the Summit T3-16 and T2-16 systems noted in Section 4.2).
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 4.5 Pin Assignments for x4 Lane Widths For x4 lane widths, a half-size header can be used. The diagram below shows the recommended pin assignments for x4 configurations (keep in mind that any of modifications mentioned in Section 4.2 can be applied.
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 4.6 Pin Assignments for x2 Lane Widths For x2 lane widths, a half-size header can be used. The diagram below shows the recommended pin assignments for x2 configurations. x2 (Bi-directional) Mid-Bus Probe Pinout...
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 4.7 Pin Assignments for x1 Lane Widths For x1 lane widths, a half-size header can be used. The diagram below shows the recommended pin assignments for x1 configurations. x1 (Bi-directional) Mid-Bus Probe Pinout...
5 Installation of the Universal (2-piece) Gen2 Mid-bus Probe Retention Module The Teledyne LeCroy Universal Retention Module is designed for use in Gen2 (or Gen1) mid-bus probe applications. The module comes in two sections, which allows the same module for either full-size or half-size mid-bus probe footprints.
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Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 4. Turn the board over to ensure that the pins from the module end are visible and accessible on the bottom surface of the board. Note: the pins of the Universal Gen2 Retention Module are intended to accommodate PCB thicknesses up to 125 mils (3.175 mm).
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 5.1 Attaching the Probe head to the Retention Module The probe design is not keyed, to allow probing of different mid-bus signal assignments. The probe head has labels indicating side A (Upstream) and side B (Downstream). Side B also has an LED indicator to show connection.
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Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 If you intend to use the analyzer's reference clock, connect the three pin clock cable to the port marked "CLK In" (Reference Clock In) on the mid-bus probe pod. Connect the other end of the clock cable to the three-pin reference clock header on the PCI Express board.
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 5.2 Cables The following cables are used . 5.2.1 iPass x4 to x8 Straight Cable 5.2.2 Half-size Gen2 Mid-bus Probe Cable and Header Assembly...
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 5.2.3 Reference Clock Cable The Reference Clock Cable (PE014UCA-X) connects the Mid-Bus Pod to the DUT so that the pod can use the clock from the DUT. The cable has a 3-pin micro socket at one end that attaches to a 3-pin header (0.050”...
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 6 Dual Probe Pod Setup Using External Clocking The steps outlined above describe a single Probe/single analyzer configuration. In a dual analyzer setup, a second probe may need to be added depending on the type of link that is being recorded.
Once you have set up the mid-bus probe, please note that the Break Connection button in the analyzer software does not function. This button is intended for use with the Teledyne LeCroy interposers that have link disconnect functionality (Gen1 slot interposers).
Teledyne LeCroy PCI Express Mid-Bus Probe for Summit Analyzers Version 1.1 8 Ordering Information Use the following table of part numbers and descriptions to order components of the Mid-bus probes. Gen2 Analyzer Mid-bus Probes Mid-bus Pod –one (1) G2 Mid-bus pod and one (1) power supply...
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