Supermicro X11DAi-N User Manual page 89

Chapter 4: UEFI BIOS
tCCD_L Relaxation
If this feature is set to Enable, SPD (Serial Presence Detect) will override tCCD_L ("Column
to Column Delay-Long", or "Command to Command Delay-Long" on the column side.) If
this feature is set to Disable, tCCD_L will be enforced based on the memory frequency.
The options are Auto, Enable and Disable.
tRWSR (Read to Write turnaround time for Same Rank) Relaxation
Select Enable to use the same tRWSR DDR timing setting among all memory channels,
and in which case, the worst case value among all channels will be used. Select Disable
to use different values for the tRWSR DDR timing settings for different channels as trained.
The options are Auto, Disable, and Enable.
Enable ADR
Select Enable for ADR (Async DIMM Self-Refresh) support to enhance memory performance.
The options are Disable and Enable.
Data Scrambling for NVDIMM
Select Enable to enable data scrambling support for onboard NVDIMM memory to improve
system performance and security. The options are Auto, Disable, and Enable.
Erase-Arm NVDIMMs
If this feature is set to Enable, the function that arms the NVDIMMs for safe operations in
the event of a power loss will be removed. The options are Enable and Disable.
Restore NVDIMMs
Select Enable to restore the functionality and the features of NVDIMMs. The options are
Enable and Disable.
Interleave NVDIMMs
If this item is set to Enable, all onboard NVDIMM modules will be configured together as
a group for the interleave mode. If this item is set to Disable, individual NVDIMM modules
will be configured separately for the interleave mode. The options are Enable and Disable.
Reset Trigger ADR (Async DIMM Self-Refresh)
Upon system power loss, an ADR sequence will be triggered to allow ADR to flush the
write-protected data buffers in the memory controller and place the DRAM memory in self-
refresh mode. When this process is complete, the NVDIMM will then take control of the
DRAM memory and transfer the contents to the onboard Flash memory. After the transfer is
complete, the NVDIMM goes into a zero power state. The data transferred will be retained
for the duration specified by the flash memory. The options are Enable and Disable.
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