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MX100IIXG
• M37700SAFP (XI286A00) CPU, PK-CTL
ANO.P70
P67
P66
P65
P64
P63
P62
P61
P60
P57
P56
P55
P54
P53
P52
P51
P50
P47
P46
P45
P44
P43
P42
/RDY. P41
/HOLD. P40
BYTE
CNVss
/RES
XIN
XOUT
/E
Vss
/HLDA. P33
ALE
/BHE. P31
R/W
D7
D6
D5
D4
25
Port 7, Analog input
Port 6
Port 5
Port 4
Ready
Hold request
Byte enable
Processor mode control
Reset
Clock
Enable
Ground
Hold acknowledge
Address latch enable
Byte high enable
Read write control
Data bus
D3
D2
Data bus
D1
D0
A15
A14
A13
A12
A11
A10
A3
A8
Address bus
A7
A6
A5
A4
A3
A2
A1
A0
TXD1. P87
Transfer data channel 1
RXD1. P86
Receive data channel 1
P85
Port 8
/CTS1. /RTS1
Clear to send channel 1/
Request to send channel 1
TXD0. P83
Transfer data channel 0
RXD0. P82
Receive data channel 0
Port 8
P81
Clear to send channel 0/
CTS0. /RTS0
Request to send channel 0
Vcc
Power supply
AVCC
Analog power supply
VREF
Reference voltage
AVSS
Analog ground
Vss
Ground
P77
AN6. P76
AN5. P75
AN4. P74
Port 7
AN3. P73
AN2. P72
AN1. . P71
Analog input
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