Receive Digital Processing; Demultiplexing; Receive Line Equalization; Unipolar-To-Bipolar Code Conversion - NEC PASOLINK Training Course

FUNCTIONAL OPERATION
2.5

Receive Digital Processing

2.5.1 Frame Synchronization
2.5.2 Descrambling
2.5.3

Demultiplexing

2.6

Receive Line Equalization

2.6.1 Demultiplexing
2.6.2

Unipolar-to-Bipolar Code Conversion

2-22
This section describes the frame synchronization, descrambling and
demultiplexing.
FS bits which are multiplexed at the transmitting end are detected and
comparing to establish the frame synchronizer.
To recover original data streams from received data streams, descrambling
is performed by using the same frame pattern as the transmitting end.
The two descrambled data streams enter the demultiplexer (DEMUX).
The DEMUX circuit extracts the frame pattern, multiframe pattern, ASC
and DSC signal bits, etc. from overhead bits with a clock produced at the
TIM GEN.
This section describes the demultiplexing and unipolar-to-bipolar code
conversion.
From received data streams, the alarm information, AIS RCVD, loopback
control/answer and stuff information bits, etc. are extracted by the
Demultiplexer (DEMUX) circuit. Then, 2.048 Mbps x N unipolar data/
CLK signals are fed to the next U/B CONV circuit.
To provide the associated DTE with the original data stream in bipolar
pulse format, the unipolar-coded 2.048 Mbps data streams are converted
into 2.048 Mbps data streams in the specified bipolar pulse format (HDB3)
by the U-B CONV circuit on the INTFC section.
ROI-S04488