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FIGURE A-2:
CURIOSITY LPC DEVELOPMENT BOARD SCHEMATIC REV 4 (1 OF 4)
USB2_HS
D_P
D_N
5V0_USBGOOD
5V0_nUSBFLT
VBUS_DETECT
VPP_GND
USB2_HS
D_P
D_N
5V0_USBGOOD
5V0_nUSBFLT
VBUS_DETECT
2015-2020 Microchip Technology Inc.
Main Micro
R13
R14
(DW_RX)
TIOA0
TP8
UTIL_SDA
UTIL_SCL
SYS_ID1
STRONG_PULLUP_EN
RX0
TX0
SYS_ID2
SYS_ID3
SYS_ID4
ISP_SPI_SS
DATA_EN
CLK_EN
VPP_ON
VBUS_DETECT
((U)PDI_RXD1)
PDI_RXD1
(TAUX_TAR)
PDI_SCK1
TAUX_DIR
TMS_DIR
TDI_DIR
TP11
5V0_USBGOOD
D_P
D_N
PKOB4_nRST
R20
USB_VBIAS
SPI1_NPCS0
ISP_SPI_SS
ICSP_FORCE_SPI_SS
CTS0_SPI1_SS
74LVC1G3157
C9
USB High Speed
J1
D_N
D_P
C2
D1
D8
C4
R9
R10
R11
C5
R12
DGI_IO0
DGI_IO1
DGI_IO2
DGI_IO3
5V0_nUSBFLT
ACTIVE
STATUS
DGI_IO3_DIR
DGI_IO2_DIR
DGI_IO1_DIR
STREAM_RXD2
(TDI_IN)
STREAM_TXD2
(TMS_IN)
STREAM_SCK2
(TAUX_IN)
ICSP_SPI0_MISO
(ICSP_SDI)
ICSP_SPI0_MOSI
(ICSP_SDO)
ICSP_SPI0_SPCK
(ICSP_SCK)
DGI_IO0_DIR
DW_RX
DW_TX
DGI_I2C_SDA
DGI_I2C_SCL
ISP_SPI1_MISO
ISP_SPI1_MOSI
(TDI_TAR)
CTS0_SPI1_SS
(SPI0_NPCS0)
SPI1_NPCS0
(TMS_TAR)
PDI_TXD1
((U)PDI_TXD1)
PKOB4_TDO
PKOB4_SWDIO
PKOB4_SWCLK
ICSP_FORCE_SPI_SS
XIN
ERASE
ISP_SPI1_SPCK
(SCK_IN)
UTIL_SCL
XIN
UTIL_SDA
ACTIVE
ERASE
STATUS
PKOB4_TDO
PKOB4_nRST
PKOB4_SWDIO
PKOB4_SWCLK
C1
R21
U1
R2
R400
5V0_nUSBFLT
R6
R7
C3
3.3V LDO
PIC VDD
U2
C7
C8
PG_SYSTEM
Schematic
VCP
ICSP
ICSP_SPI0_MISO
ICSP_SPI0_MOSI
ICSP_SPI0_SPCK
ISP_SPI1_SPCK
ICSP
CLK_EN
DATA_EN
TVDD_GOOD
Curiosity LPC
Designed with
R3
R5
5V0_USBGOOD
R8
FB1
C6
Curiosity LPC
Designed with
DS40001804D-page 16
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