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SCHEMATICS
6
SCHEMATICS
The following figures are the schematics for the TRF4903.
A
TP1
TP3
TP5
GND
GND
GND
TP_GRN
TP_GRN
TP_GRN
D9
SW6
BAT1
1
BAT−S W
1
BAT
2
+
2 X AAA
4
2
3
MBRM120LT3
−
PCB MT
EG1218
2468
VCC
VCC_CPU
C57
C37
C33
C31
C34
C30
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
J5
3
13
11
9
7
5
3
1
HDR 7X2X2MM
RF
STROB
STROB
DATA
DATA
MODE
MODE
CLK
CLK
STDBY
STDBY
TX−D ATA
2
TX−DATA
LOCK−DET
LOCK−DET
RF
J1
1
U4
6
RS232OUT
2
14
T1OUT
RS232IN
7
13
R1IN
3
8
7
T2OUT
4
8
R2IN
9
5
2
V+1
4
C2+
1
CONNECTOR DB9
5
C2−
C45
.1uF
6
V−
C43
.1uF
C46
MAX3232−SOIC16
.1uF
A
22
TRF4903 With MSP430 Demonstration and Development Evaluation Kit
B
TP2
VSS 3.5−6.0 VDC
VCC
VCC_RF
TP_RED
R31
R56
0
0
LDO REGULATOR
JP2
U3
HEADER 3
BAT−SW2
1
5
IN
OUT
3.0V@150mA
3
2
EN GND
C42
C32
+
22uF
TPS76330DBV
+
22uF
DEMO
EVK
−20+80%
DNP
−20+80%
16V
16V
P6.5
P6.4
P6LED3
P6LED2
P6LED1
P6LED0
14
12
P5.7
59
10
P5.7/R33
P5.6
58
8
P5.6/R23
P5.5
57
6
P5.5/R13
P5.4
55
4
P5.4/COM3
P5.3
54
2
53
P5.3/COM2
P5.2
12
P5.2/COM1
P5.1
13
P5.1/S0
P5.0
P5.0/S1
P4.7
46
P4.7/S34
P4.6
47
P4.6/S35
48
P4.5
P4.5/S36
P4.4
49
P4.4/S37
P4.3
50
P4.3/S38
P4.2
51
R58
62
P4.2/S39
R45
100
63
P4.1 P4.0
100
R46
64
P3.7
R47
100
65
P3.6
R48
100
66
P3.5
100
67
P3.4
R50
P3.3
68
100
P3.2
P3.3/UCLK0
69
P3.1
70
P3.2/SOMI0
71
P3.1/SIMO0
P3.0/STE0
R53
10K
UTXD0
URXD0
11
T1IN
12
R1OUT
IO
VCC
10
T2IN
Fsel1
9
R2OTU
Fsel2
Fsel3
16
VCC
Fsel4
1
C1+
3
C1−
C44
NOTES: UNLESS OTHERWISE SPECIFIED.
15
GND
.1uF
1. INTERPERT DRAWING IAW MIL−STD−100.
2. RESISTANCE VALUES ARE IN OHMS.
3. CAPACITANCE VALUES ARE IN FARADS.
4. PARTIAL REFERENCE DESIGNATIONS ARE SHOWN
FOR COMPLETE DESIGNATION, PREFIX WITH UNIT
NUMBER, ASSY. DESIGNATION AND SUBASSEMBLY
DESIGNATION.
B
Figure 12. Schematic (Page 1)
C
ZONE
ALL
OPTIONAL,DNP
Y3
VCC
4.9152MHZ
C35
C36
10pF
10pF
R57
10K
VCC
XTAK2O UT
R30
82K
XTAL1IN
XTAL/TCLK
TDO/TDI
TDI
TMS
TCK
/RST
R42
VCC_CPU
0
61
DVSS2
99
DVSS1
98
AVSS
11
VREF−
10
VeREF+
7
VREF+
45
S33
44
S32
43
S31
42
S30
41
S29
MSPF449
40
S28
39
S27
38
S26
U6
37
S25
36
S24
35
S23
34
S22
33
S21
32
S20
31
S19
30
S18
29
S17
28
S16
27
S15
26
S14
25
S13
24
S12
IO
DWN
RICH WILLIAMS
5. DNP = DO NOT PLACE.
CHK
X
APRVD
EXCEPT AS MAY BE OTHERWISE PROVIDED BY CONTRACT, THIS
DRAWING OR SPECIFICATION IS THE PROPRIETARY PROPERTY OF
X
CNOWIRE TECHNOLOGY INC. IT IS ISSUED IN STRICT CONFIDENCE
APRVD
AND SHALL NOT BE REPRODUCED OR COPIED OR USED (PARTIALL Y OR
WHOLLY) IN ANY MANNER WITHOUT PRIOR EXPRESS WRITTEN
X
AUTHORIZA TION OF CNOWIRE TECHNOLOGY INC.
C
SWRU010A – October 2004 – Revised May 2005
www.ti.com
D
E
REVISIO NS
REV
DESCRIPTION
DATE
A
INITIAL RELEASE
7−9−04
Y4
VCC
32.768KHZ
R29
0
J2
1
2
3
4
5
6
7
8
9
10
11
12
VCC
13
14
HEADER 7X2
VCC
VCC
J3
1
2
3
4
P3.2
P3.3
5
6
P5.4
P3.1
7
8
R03
VREF−
P5.5
9
10
VeREF+
P5.7
P5.6
11
12
VREF+
P5.2
P5.3
13
14
R41
P4.2
COM0
15
16
P4.4
P4.3
0
17
18
S33
C47
P4.6
P4.5
19
20
S32
22uF
P1.3
P4.7
+
21
22
S31
−20+80%
P1.1
P1.2
23
24
S30
16V
/RST
P1.0
25
26
S29
P6LED1
P6LED0
27
28
S28
P6LED3
P6LED2
29
30
S27
P6.5
P6.4
31
32
S26
VREF+
33
34
S25
VREF−
VeREF+
35
36
S24
P5.0
P5.1
37
38
S23
39
40
S22
S21
S20
HEADER 20X2
VCC
S19
S18
J4
S17
S16
2
1
S15
URXD0
UTXD0
4
3
S14
S32
S33
6
5
S13
S30
S31
8
7
S12
S28
S29
10
9
S26
S27
12
11
S24
S25
14
13
S22
S23
16
15
S20
S21
18
17
S18
S19
20
19
S16
S17
22
21
S14
S15
24
23
S12
S13
26
25
S10
S11
28
27
S8
S9
30
29
S6
S7
32
31
S4
S5
34
33
S2
S3
36
35
38
37
40
39
HEADER 20X2
DATE
CNOWIRE Technology
7−6−09
1400 Coleman Ave.,Bldg G−22
, Santa Clara, CA. 95050
XX/XX/ XX
Title
TRF4903/MSP4310F437
DEMO
XX/XX/ XX
Size
Document Number
B
100014SCH−01
XX/XX/ XX
Date:
Wednesday, March 09, 2005
Sheet
1
D
E
APPROVED
RPW
4
3
VCC
2
1
Rev
A
of
3
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