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An ATM connection transfers raw bits of information to a destination router/host. The ATM router
takes the common part convergence sublayer (CPCS) frame, carves it up into 53-byte cells, and
sends these cells to the destination router or host for reassembly. Forty-eight bytes of each cell are
used for the CPCS data; the remaining 5 bytes are used for cell routing. The 5-byte cell header
contains the destination VPI/VCI, payload type, cell loss priority (CLP), and header error control.
Unlike a LAN, which is connectionless, ATM requires certain features to provide a LAN
environment to the users. One such feature is broadcast capability. Protocols wishing to broadcast
packets to all stations in a subnet must be allowed to do so with a single call to Layer 2. In order to
support broadcasting, the router allows the user to specify a particular VC as a broadcast VC. When
the protocol passes a packet with a broadcast address to the ATM driver, the packet is duplicated and
sent to each VC marked as a broadcast VC. This method is known as pseudobroadcasting.
What Is the AIP?
The ATM interface processor (AIP) (see Figure 1) provides a single ATM network interface for
Cisco 7000 series and Cisco 7500 series routers.
Figure 1
The AIP provides a direct connection between the high-speed Cisco Extended Bus (CxBus and
CyBus) and external ATM networks. A physical layer interface module (PLIM) on the AIP
determines the type of ATM connection. There are no restrictions on slot locations or sequence; you
can install an AIP in any available interface processor slot.
Note
the system bus; this would cause packets to be dropped. Two AIP modules per chassis is considered
to be a practical limit.
The AIP provides the ATM connection between your router and an ATM switch. (To configure your
ATM switch, refer to its user documentation.)
The AIP supports the following features:
•
Multiple rate queues.
•
Reassembly of up to 512 buffers simultaneously. Each buffer represents a packet.
•
Up to 2,048 virtual circuits.
ATM Interface Processor (AIP)
U111, microcode ROM
Traffic from multiple ATM network interfaces could theoretically exceed the bandwidth of
Asynchronous Transfer Mode Interface Processor (AIP) Installation and Configuration
TX
RX
What Is the AIP?
5
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