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Actel Core1553 User Manual

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Core1553 Development Kit
User's Guide

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  • Page 1 Core1553 Development Kit User’s Guide...
  • Page 2 Actel Corporation. Trademarks Actel, IGLOO, Actel Fusion, ProASIC, Libero, Pigeon Point and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective...

  • Page 3: Table Of Contents

    1 Core1553 Development Kit Hardware........

  • Page 5: Introduction

    (Figure 1) without having to create a complete MIL-STD-1553B- compliant system. You can use the files included with the Core1553 Development Kit to program a Fusion Advanced Development Kit and create a 1553 bus controller, remote terminal, and bus monitor compliant with the MIL-STD-1553B standard. The targeted FPGA (M1AFS1500) is mounted...

  • Page 6: Core1553 Development Kit Web Resources

    • RTL: FPGA example design source files Note: Core1553BRM source files are not provided in the CORE1553 Development Kit design files. Core1553BRM IP must be purchased separately. User’s Guide Contents This user’s guide describes the contents, architecture, and guidelines for working with the Core1553 Development Kit demonstration and the Core1553 Development Kit.

  • Page 7: Required Items

    User’s Guide Contents Required Items The following items are required in order to run the Core1553 Development Kit demonstration: • HyperTerminal or similar serial communication program ® • PC system running Windows XP operating system or later • FlashPro software, v8.5 or later Optional Items •...

  • Page 9: Core1553 Development Kit Hardware

    (BM or MT). Core1553BRM can be configured to provide all three 1553 functions or any combination thereof. The core is supported in all recent Actel flash, antifuse, and radiation-tolerant product families. A typical system implementation using Core1553BRM is shown Figure 1-1.

  • Page 10: Core1553 Development Kit

    Core1553 Development Kit The Core1553 Development Kit includes the Fusion Advanced Development Kit board and the Core1553 Daughter Card. This section describes the board components briefly. The CD contains the board schematic and other required files. Fusion Advanced Development Kit Board Description...
  • Page 11 5 V Power 3.3 V Power 9 V Jack CAN Interface Core1553 Interface Connector to M1AFS-ADV-DEV-KIT Buffers Figure 1-3 • Core1553 Daughter Card Table 1 • Core1553 Daughter Card Components Component Part Number Manufacturer Location 1553B transceiver BU-63147F3-320 Data Device Corporation...
  • Page 12 JP17 Jumper to select either external 5 V or 5 V provided Pin 1–2 through legacy connector V3P3 V5V_EXT V3P3_EXT V3P3_COMM V5V_COMM JP11 JP11 JP17 JP17 10uF 16V 10uF 16V 10uF 16V 10uF 16V Figure 1-5 • Core1553 Daughter Card...

  • Page 13: Core1553Brm Demonstration Design

    (monitor terminal) functions of the core (Figure 2-1). In addition, the design allows for the monitoring of 1553B bus activity using Actel Silicon Explorer II hardware. FPGA Design The demonstration design contained within the M1AFS1500 FPGA consists of the following blocks: •...
  • Page 14 1553 bus without any external transceivers and transformers. This block also allows the Core1553BRM blocks to interface to an off-chip 1553B bus transceiver that is fitted on the Core1553 Daughter Card. Memory Interface The memory interface ties the internal data bus to the on-board external memories, allowing each core to interface its dedicated memory space.
  • Page 15 FPGA Design shows DIP switch bank. These switches are wired to inputs of the FPGA so that open will correspond to logic 1 (4.7 K pull-up to 3.3 V) and closed will correspond to logic 0 (GND). V3P3 R145 4.7K R146 4.7K R155...
  • Page 16 Core1553BRM Demonstration Design Switches 3 and 4 (Auto Mode) In Auto mode, switches 3 and 4 control which Core1553BRM core is the bus controller. 01: BRM 1 is the BC, BRM 2 is RT 2. 10: BRM 2 is the BC, BRM 1 is RT 1. 11: No BC, BRM 1 is RT1, and BRM 2 is RT 2.

  • Page 17: Interpreting The Hyperterminal Display

    Interpreting the HyperTerminal Display Table 2-1 • Demonstration Board LEDs Board Location Function Heartbeat, flashes at 2 KHz Not used BRM core 1 busy BRM core 2 busy Data compare error Message of failure interrupt SRAM1 byte High enable SRAM1 byte Low enable SRAM2 byte High enable SRAM2 byte Low enable SRAM1 and SRAM2 output enable...
  • Page 18 Core1553BRM Demonstration Design • ZZ indicates the settings for switches 6 to 8, but does not affect operation. Example display: Core1553BRM NT00 Qualification Testing mode While in Qualification Testing mode: • X: Q = Qual mode; P = Qual mode, RT address parity error detected •...

  • Page 19: Script Mode Demonstration Design

    Script Mode Demonstration Design Script Mode Demonstration Design The DIP switch setting allows setting the core in script mode. In this mode the BRM cores are not initialized. The core is set up via the UART interface. Setting Up the Demonstration Design The Core1553BRM Development Kit boards come preprogrammed with demonstration designs.
  • Page 20 Core1553BRM Demonstration Design – 115,200 bits per second – 8 data bit – Parity set to none – 1 stop bit – Flow control set to none Running the Demonstration Design in Script Mode 1. Turn the power switch SW7 on the board to the ON position. 2.
  • Page 21 Script Mode Demonstration Design transmit vector commands. At the conclusion of the script, BC memory values are compared to verify that the three messages completed correctly (Figure 2-7). Figure 2-7 • HyperTerminal Window – Success Message The HyperTerminal session will echo the commands sent to configure various register and memory settings.

  • Page 22: Auto Mode Demonstration Design

    Core1553BRM Demonstration Design memory or register compare instructions failed (Figure 2-8). LED D5 will light to indicate a memory or register compare failure. Use RSTN and ESC to re-enter the command if an error is made. Figure 2-8 • HyperTerminal Window – Failed Message Auto Mode Demonstration Design The DIP switch setting enables you to set the core in Auto mode.
  • Page 23 Auto Mode Demonstration Design 2. Connect one end of a 9 V power supply to power input J3 on the M1AFS-ADV-DEV-KIT board (Figure 2-9) and plug the supply into an electrical outlet. Figure 2-9 • Connecting the USB and 9 V Power Supplies on the M1AFS-ADV-DEV-KIT Board 3.

  • Page 24: Monitoring 1553B Message Traffic Using Silicon Explorer Ii

    To monitor message traffic: 1. If you do not have the latest version of Silicon Explorer, download the software from the Actel website (www.actel.com/download/program_debug/se/default.aspx) and install it. 2. Connect Silicon Explorer II to your PC using a serial cable. 3. Connect the 22-pin cable supplied with Silicon Explorer II (for 18 channels, a clock, V...

  • Page 25: Interrupt Status Messages

    Interrupt Status Messages Figure 2-11 • J5 Connector on M1AFS-ADV-DEV-KIT Board 4. Power up Silicon Explorer and start the Silicon Explorer software. In the Silicon Explorer software, set Silicon Explorer to sample at 33 MHz, Center (50/50%), and trigger on falling edge on Ch2.

  • Page 26: Subaddresses

    Core1553BRM Demonstration Design Interpreting Interrupt Status Messages The meaning of each of the first four interrupt messages is given below: 2.80E4.0400.4A00 • 2.80e4: IAW = RT SA25 RX • 0400: IIW = Sub address accessed • 4A00 : 9 words bus A •...

  • Page 27: Modifying The Demonstration Design Through Script

    Script Core1553BRM Verification Testbench Actel has developed a Core1553BRM verification testbench to verify the core performance per the MIL-STD-1553B specification. The testbench is coded in VHDL and includes several Core1553BRM cores connected to a 1553 bus and backend interfaces. A procedural testbench controls the various blocks and implements various test protocols.

  • Page 29: A Programming The Fusion Fpga On M1Afs-Adv-Dev-Kit

    A-1). Figure A-1 • Connect J1 Pins on M1AFS-ADV-DEV-KIT Board 2. Connect one end of the USB mini B cable to the Actel programming stick and the other end to the PC. 3. Connect one end of a 9 V power supply to the power input (Power1) on the M1AFS-ADV- DEV-KIT board.

  • Page 31: B Communication From Hyperterminal To M1Afs-Adv-Dev-Kit

    Fusion FPGA device. For more information about the USB-to-UART bridge and device drivers, refer to the Fusion Embedded Development Kit page: www.actel.com/products/hardware/devkits_boards/fusion_embedded.aspx. Installing the M1AFS-ADV-DEV-KIT Board USB Serial Driver 1. Use WinZip to extract all files stored in the CP210x_Drivers.zip archive.

  • Page 33: C Product Support

    Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the Actel web site. Website You can browse a variety of technical and non-technical information on Actel’s home page, at www.actel.com. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center from 7:00 a.m.
  • Page 34 The phone hours are from 7:00 a.m. to 6:00 p.m., Pacific Time, Monday through Friday. The Technical Support numbers are: 650.318.4460 800.262.1060 Customers needing assistance outside the US time zones can either contact technical support via email (tech@actel.com) or contact a local sales office. Sales office listings can be found at www.actel.com/company/contact/default.aspx.

  • Page 35: Index

    33 CORE1553 Development Kit contents 5 Core1553BRM 9 demonstration design 13 CORE1553-SA 5 Core15553 Development Kit Core1553 Daughter Card 11 Fusion Advanced Development Kit 10 customer service 33 demonstration design Auto mode 22 Script mode 19 M1AFS1500 5...
  • Page 36 Actel, IGLOO, Actel Fusion, ProASIC, Libero, Pigeon Point and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. Actel is the leader in low-power FPGAs and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions.
  • Page 37 Actel, IGLOO, Actel Fusion, ProASIC, Libero, Pigeon Point and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions.
  • Page 38 Мы молодая и активно развивающаяся компания в области поставок электронных компонентов. Мы поставляем электронные компоненты отечественного и импортного производства напрямую от производителей и с крупнейших складов мира. Благодаря сотрудничеству с мировыми поставщиками мы осуществляем комплексные и плановые поставки широчайшего спектра электронных компонентов.

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