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shows DIP switch bank. These switches are wired to inputs of the FPGA so that open will
correspond to logic 1 (4.7 K pull-up to 3.3 V) and closed will correspond to logic 0 (GND).
V3P3
Figure 2-2 • DIP Switch Schematic
Switches 1 and 2
Switches 1 and 2 control the basic operating modes of the demonstration design.
00: Qualification testing mode. Not used for the demonstration design.
01: Script mode (non-initialization mode). The BRM core is not initialized. The core is set up via the
UART interface.
10: Auto mode. Sets one Core1553BRM core as bus controller and the other as remote/monitor
terminal and gets the data from internal data generator. Upon power-up, the state machine within
the control sequencer steps through the following set of commands to be sent to the two BRM
cores:
1. Sends configuration setting through UART.
2. Sets frame time to 0.75 seconds.
3. RT to BC transfer (SA = 25, WC = 9). RT to transmit the data from Data generator block.
4. BC generates an interrupt.
5. BC to RT transfer (SA = 2, WC = 9). BC will transmit its Data generator block data.
6. BC to RT transfer (SA = 1). BC transmits test data.
7. Waits for frame time to complete and then jumps to state 3.
8. End of frame
When the interrupt in state 4 occurs, the control sequencer increments the state 6 word count by 2.
This should be observable on HyperTerminal and the bus traffic acquired by Silicon Explorer II or
any logic analyzer. If a 1553 message fails, then the control sequencer will jump to state 8 and stop.
SA stands for 1553B subaddress; WC stands for word count.
11: Reserved
R145
4.7K
R146
4.7K
R155
4.7K
R140
4.7K
R141
4.7K
R142
4.7K
R143
4.7K
R144
4.7K
S1
S1
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
SW DIP-8
SW DIP-8
Mfr P/N :76SB08ST
Mfr: Grayhill Inc
FPGA Design
DIP1 {5}
DIP2 {5}
DIP3 {5}
DIP4 {5}
DIP5 {5}
DIP6 {5}
DIP7 {5}
DIP8 {5}
15
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