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2 – Core1553BRM Demonstration Design
The Core1553BRM demonstration design implements two complete Core1553BRM cores into a
single M1AFS1500 FPGA and allows you to evaluate the 1553 bus controller, remote terminal, and
bus monitor (monitor terminal) functions of the core
the monitoring of 1553B bus activity using Actel Silicon Explorer II hardware.
FPGA Design
The demonstration design contained within the M1AFS1500 FPGA consists of the following blocks:
•
Two complete Core1553BRM cores
•
1553B bus interface
•
Memory interface
•
Bus arbiter
•
Control sequencer
•
UART
•
DIP switches
•
LEDs
•
Data generator
•
External memory
Controller
Sequencer
Data
Generator
UART
Terminal
DIP
Switch
Figure 2-1 • Core1553BRM Demo Design Architecture
M1AFS1500
Core1553BRM
UNIT2
Core1553BRM
UNIT1
Bus Arbiter
LEDs
(Figure
2-1). In addition, the design allows for
1553B
Interface
Memory
Interface
1553B
Transceiver
Memory
2 Pages Each
64 K×16
1553 Bus
13
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