Actel Core1553 User Manual page 14

Core1553BRM Demonstration Design
Core1553BRM
Each Core1553BRM block can be configured as a bus controller or a remote/monitor terminal and
operates off 16 MHz clock. This 16 MHz clock is generated using a PLL from an on-board 50 MHz
clock. The two blocks are configured to share CPU and memory busses. Each core has access to its
own 64 K words of memory within the off-chip memory. The demo design allows configuring one
core as a bus controller and the other as remote/monitor terminal, depending on dip switch
settings.
1553B Bus Interface
The 1553B bus interface block allows the Core1553BRM blocks to be connected and form a
complete 1553 bus without any external transceivers and transformers. This block also allows the
Core1553BRM blocks to interface to an off-chip 1553B bus transceiver that is fitted on the
Core1553 Daughter Card.
Memory Interface
The memory interface ties the internal data bus to the on-board external memories, allowing each
core to interface its dedicated memory space.
Bus Arbiter
This block allows the control sequencer block and the two Core1553BRM cores to access the
internal bus.
Control Sequencer
The control sequencer connects to the BRM CPU interfaces and replaces the CPU in a typical system.
This block handles system interrupts and provides user interfaces via an external terminal over a
serial interface.
UART
The UART block implements a simple RS-232 interface running at 115,200 baud, tied to the off-chip
USB-to-UART interface. The USB-to-UART interface enables HyperTerminal on a PC to communicate
with the Fusion FPGA. HyperTerminal is a serial communications application program that can be
installed in the Windows operating system. With a USB driver properly installed, and the correct
COM port and communication settings selected, you can use the HyperTerminal program to
communicate with a design running on the Fusion FPGA device.
DIP Switches
Configuration of the demonstration design is handled by the 8-position DIP switch located at
position S1. Setting the DIP switch controls the operating mode of each Core1553BRM, sets the
remote terminal address, and can enable the bus loopback logic internal to the FPGA. Figure 2-2
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