Tektronix 5440 Instruction Manual page 49

Zeros
L
ogic and M emory . T h e Zeros
L
ogic an d M emory column decoder t h roug h Q1056 to a dd o n e unit of current
stage, 01060, stores d ata encoded by t h e p lug-i n units to at t h e input of t h e column decoder . T h is p roduces α zero
p
rovi d e zeros-ad d ing an d
p
refix-s h ifting logic for t h e after t h e c h aracter dis p layed on t h e crt d uring TS-4 .
readout system . T h e strobe
p
ulse at
p
in 15 goes
p
ositive During TS-6, memory Β is interrogated to see if anot h er
w h e n t h e d ata h as stabilize d an d can be ins pected . T h is zero s h ould be ad d e d . If anot h er zero is necessary, α
activates t h e zeros logic an d memory stage so it can store secon d positive out p ut is p roduced at pin 7, w h ic h again
t h e enco d e d d ata . Α bloc k re p resentation of t h e memory
results in α column 1 output from t h e column d ecoderand
se q uence is s h own in
F
ig . 3-8 . If t h e plug-in unit encodes
α second zero in t h e crt d is p lay .
data for column 1, 2, 3, 4, or 10 of row 3, t h e a p p ropriate
memory (or memories) is set .
F
inally, memory C is i n terrogate d d uring TS-8 to obtain
information on w h et h er t h e p refix s h oul d be reduced, or
If data is enco d e d , α negative-going
p
ulse is co nn ected left at t h e value w h ic h was encoded . If data
h
as been
to t h e base of 01050 in t h e dis p lay-s k i p generator to e n co d e d
w
h ic h calls for α re d uctio n in
p
refix, α negative-
produce α
d
isplay-s k i p out p ut . Since t h e i n formation t h at
going output level is
p
roduced at p
in 7 . T h is negative level
is enco d e d is only
p
rovi d e d to set t h e memories an d not subtracts one unit of column current from t h e d ata at t h e
i n ten d ed to be dis p laye d on t h e crt at t h is time, t h e dis p lay- in p ut to t h e column decoder .
N
otice on t h e c h aracter
s k i p out p ut prevents α readout d isplay if t h is encodi n g selection matrix of
F
ig . 3-6 t h at α re d uction of one column
occurs in TS-1 . w h en row 4 is
p
rogrammed results i n α one
u
nit reduction
of t h e
p
refix .
F
orexample, wit h
t
h e 100 μ V program, if d ata
was received from t h e p lug-in calling for α re d uction in
Duri n g TS-5, memory Α is interrogate d . If information prefix, t h e crt read out would be c h anged to 1 m V (zeros
is store d in t h is memory, α
p
ositive-going output is
delete d by
p
rogram ; see
E
nco d ing t h e Data, d iscusse d
p ro d uce d at
p
in 7 . T h is
p
ulse is connected to
p
in 10 of t h e
earlier in t h is sectio n ) .
Colum n 1
Col u m n 2 13
Col umn 3
10
M
emo
r
y
C
(
R
e
du
ce
Col u mn 4
11 prefix)
Col u m n 10
12
14
R
ow 3 16 4~ --fi-
E
nab le to all memories
W
or d Trigger 9 <
R
eset to all
m
em or ies
I n te rr ogatio n pu lses
Ti m e-Slot 5
Time-Slot 6 Ti m e-Slot 8
Time-Slot 1
M
e mo r y
Α
(Add '0')
Β Ί
(Add '0')
ι ι
Memory
D
F
ig . 3-8 .
B
loc k r e pr ese n tatio n of memory sequence i n 01060 .
Circuit Description-5440
(Blank)
3- 1 3