Timing Of Host Interface(Ultra Dma) - Toshiba SD-R6112 Product Specification

6.2.4.Timing of Host Interface (Ultra DMA )
Figure 15 shows the Host Interface Ultra DMA word Timings
DMARQ
DMACK-
STOP
DMARDY
tZIORDY
STROBE
DD (15:0)
Sender
tZIORDY
STROBE
DD (15:0)
Recipient
In all timing diagrams, the low line indicator negated, and the upper line indicators asserted.
Ultra DMA Mode 2
Timing parameters min (ns) max (ns)
Typical Sustained Average Cycle time
t2CYC
Two cycle time (from rising edge to next rising edge of
from falling edge to next falling edge of STROBE)
tCYC Cycle time allowing
tDVS Data valid Setup time
tDVH Data valid Hold time
tUI Unlimited Interlock time
tACK Setup and Hold Time for DMACK-
tENV Envelope time
tZAD Minimum Delay time for Driver
tZIORDY Minimum time for DMACK-
tFS First STROBE time
tRFS Ready-to-Final STROBE time
tRP Ready-to-Pause time
tLI Limited Interlock time
tMLI Interlock with minmum
tDS Data setup time (at recipient)
tDH Data hold time (at recipient)
tUI
t2CYC
tFS
tACK
tCYC
tENV
tZAD
tDVS tDVH tDVS
tZAD
tDS t D H
tDS
Figure 15 Host Interface Timing (Ultra DMA Mode 2)
tRP
tCYC
t2CYC
tRFS
tDVH
tDVS tDVH
tDH tDS
tDH
19/28
tMLI
tACK
tLI
tDVS tDVH
CRC
tDS tDH
CRC
Min time (ns)
120
117
55
34
6
0
20
20
0
20
0
100
0
20
7
5
SD-R6112 Rev.1.0
Max time (ns)
70
170
50
150