Timing Of Host Interface (Ultra Dma) - Toshiba R6472 - DVD±RW Drive - IDE Specifications

6.2.4. Timing of Host Interface (Ultra DMA)

Figure 11 shows the timings of the host interface Ultra DMA word.
tUI
DMARQ
DMACK-
tACK
STOP
tENV
DMARDY
tZIORDY
STROBE
DD (15:0)
Sender
tZIORDY
STROBE
*1: In all timing diagrams, the low line indicator is negated and the upper line indicators asserted.
Ultra DMA Mode 2
Timing parameters min (ns) max (ns)
Typical Sustained Average Cycle time
Two cycle time (from rising edge to next rising edge of
t2CYC
from falling edge to next falling edge of STROBE)
tCYC Cycle time allowing
tDVS Data valid Setup time
tDVH Data valid Hold time
tUI Unlimited Interlock time
tACK Setup and Hold Time for DMACK-
tENV Envelope time
tZAD Minimum Delay time for Driver
tZIORDY Minimum time for DMACK-
tFS First STROBE time
tRFS Ready-to-Final STROBE time
tRP Ready-to-Pause time
tLI Limited Interlock time
tMLI Interlock with minimum
tFS
t2CYC
tCYC
tZAD
tDVS tDVH
tDVS tDVH
tZAD
Figure 11 Timings of Host Interface (Ultra DMA Mode 2)
tRP
tCYC
t2CYC
tRFS
tDVS tDVH
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tMLI
tLI
tDVS tDVH
CRC
Min time (ns) Max time (ns)
120
117
55
34
6
0
20
20 70
0
20
0 170
50
100
0 150
20
TS-L532A (SD-R6472) Rev.1.1
tACK