Relay Control; Power-On Safeguard - Keithley 7015-S Instruction Manual

IDCLK
IDDATA
Figure 5-9
Start and stop sequences
IDCLK
IDDATA
(Data output
from mainframe
or ROM)
IDDATA
(Data output
from mainframe
or ROM)
Figure 5-10
Transmit and acknowledge sequence

5.5.3 Relay control

Card relays are controlled by serial data transmitted via the
relay DATA line. A total of five bytes for each card are shift-
ed in serial fashion into latches located in the card relay driv-
er ICs, U100-U103, U105. The serial data is clocked in by
the CLK line. As data overflows one register, it is fed out the
Q'S line of the register down the chain.
Once all five bytes have shifted into the card, the STROBE
line is set high to latch the relay information into the Q out-
puts of the relay drivers, and the appropriate relays are ener-
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Start Bit
1
Start
Stop Bit
8
Acknowledge
gized. Note that a relay driver output goes low to energize the
corresponding relay.

5.5.4 Power-on safeguard

Upon power-up, the relay driver outputs are inhibited for
about 200msec to avoid random engagement. The output en-
able (OE) signal is generated by circuitry located in the
mainframe.
Service Information
9
5-15