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Summary of Contents for Texas Instruments SLVU013
- Page 1 High Density Synchronous Buck Converter Design Using TPS56xx Controllers User’s Guide June 1999 Mixed-Signal Linear Products SLVU013...
- Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
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Page 3: Read This First
About This Manual This user’s guide describes techniques for designing synchronous buck converters using TI’s SLVP1111–114 evaluation modules (EVM) and TPS56xx ripple regulator controllers. How to Use This Manual This document contains the following chapters: Chapter 1 Introduction Chapter 2 Design Procedure Chapter 3 Test Results Information About Cautions and Warnings This book may contain cautions and warnings. -
Page 4: Related Documentation From Texas Instruments
Operation of this equipment in other en- vironments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. Trademarks TI is a trademark of Texas Instruments Incorporated. -
Page 5: Table Of Contents
Introduction ..............Synchronous Buck Regulator Operation Hysteretic Control Operation Design Strategy... - Page 6 Running Title—Attribute Reference Figures 1–1 Simplified Synchronous Buck Converter Schematic 1–2 Simplified Hysteretic Controlled Output Voltage Waveform 1–3 SLVP111–114 EVM Converter Schematic Diagram 1–4 Top Assembly ............. . . 1–5 Bottom Assembly (Top View) 1–6...
- Page 7 3–27 SLVP113 Measured Start-Up (V 3–28 SLVP113 Measured Load Transient Waveforms 3–29 SLVP114 Measured Load Regulation 3–30 SLVP114 Measured Efficiency 3–31 SLVP114 Measured Power Dissipation 3–32 SLVP114 Measured Switching Frequency 3–33 SLVP114 Measured Switching Waveforms 3–34 SLVP114 Measured Start-Up (INHIBIT) Waveforms 3–35 SLVP114 Measured Start-Up (V 3–36...
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Page 9: Introduction
TI’s SLVP111–114 EVMs and TPS56xx ripple regulator controllers. Synchronous buck converters provide an elegant power supply solution for rapidly transitioning DSP loads (such as the Texas Instruments TMS320C62x/67x family), fast memory, and similar processors. An order of magnitude improvement in dynamic response of this converter over standard control methods reduces hold-up capacitance needs near the transitioning loads, thus saving cost and board space. -
Page 10: Synchronous Buck Regulator Operation
Synchronous Buck Regulator Operation 1.1 Synchronous Buck Regulator Operation The synchronous buck converter is a variation of the traditional buck converter. The main switching device is usually a power MOSFET and is driven in the same manner as in a traditional buck converter. The freewheeling rectifier, usually a Schottky device, is replaced by a power MOSFET and is driven in a complementary or synchronous fashion relative to the main switching device;... -
Page 11: Hysteretic Control Operation
1.2 Hysteretic Control Operation Hysteretic control, also called bang-bang control or ripple regulator control, maintains the output voltage within the hysteresis band centered about the internal reference voltage. Figure 1–2 shows a simplified example of a hysteretic controlled output voltage using the TPS5625 with a reference voltage of 2.500 V and a hysteresis band of 50 mV. -
Page 12: Design Strategy
Design Strategy 1.3 Design Strategy The SLVP111–114 evaluation modules (EVMs) are optimized for 5-V main input voltage and 6-A output current. The EVMs need an additional low current 12-V (30 mA max) input voltage for the controller. TI’s application report, Providing a DSP Power Solution from 5 V or 3.3 V Only Systems , TI literature number SPRA525 describes how one can implement a simple boost circuit for 5-V only input voltage applications. -
Page 13: Design Specification Summary
1.4 Design Specification Summary This section summarizes the design requirements of the EVM converters. Although every attempt was made to accurately describe the performance of the EVM converters and the TPS56xx controllers, in case of conflicts, the TPS56xx data sheet takes precedence over this document. The TPS56xx family of controllers provides the necessary regulation functions. -
Page 14: Design Specification Summary
Design Specification Summary Table 1–2. EVM Converter Operating Specifications (Continued) Specification Output ripple SLVP111 (3.3 V) SLVP112 (2.5 V) SLVP113 (1.8 V) SLVP114 (1.5 V) Efficiency, 6 A load SLVP111 (3.3 V) SLVP112 (2.5 V) SLVP113 (1.8 V) SLVP114 (1.5 V) Efficiency, 4 A load SLVP111 (3.3 V) SLVP112 (2.5 V) -
Page 15: Schematic
1.5 Schematic Figure 1–3 shows the EVM converter schematic diagram. The schematic diagrams for the other EVM converters are identical except for the controller IC used. Figure 1–3. SLVP111–114 EVM Converter Schematic Diagram BOOT LOWDR HUGHDR DRVGND BOOTLO LOHIB HISENSE LODRV LOSENSE BIAS... -
Page 16: Bill Of Materials
Bill of Materials 1.6 Bill of Materials Table 1–3 lists materials required for the SLVP111–114 EVMs. Table 1–3. SLVP111–114 EVMs Bill of Materials Ref Des Part Number 10TPA33M 6TPB150M 6TPB150M 6TPB150M GRM39X7R104K016A GRM39X7R104K016A GRM42–6Y5V105Z016A GRM42–6Y5V105Z016A GRM42–6Y5V225Z016A 4TPC150M 4TPC150M 4TPC150M 4TPC150M GRM235Y5V106Z016A GRM42-6Y5V103Z025A GRM42–6Y5V105Z016A... - Page 17 Table 1–3. SLVP111–114 EVMs Bill of Materials (Continued) Ref Des Part Number TPS5633PWP TPS5625PWP TPS5618PWP TPS5615PWP Description Resistor, Chip, 1 k , 1/16W, 5% Resistor, Chip, 100 , 1/16W, 1% Resistor, Chip, 11 k , 1/16W, 5% Resistor, Chip, 100 , 1/16W, 1% Resistor, Chip, 20 k , 1/16W, 1% Resistor, Chip, 4.7 , 1/16W, 5% Resistor, Chip, 750 , 1/16W, 5%...
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Page 18: Board Layout
Board Layout 1.7 Board Layout Figures 1–4 through 1–7 show the board layouts for the SLVP111–114 evaluation modules. Figure 1–4. Top Assembly Figure 1–5. Bottom Assembly (Top View) Figure 1–6. Top Layer 1-10 Top Assembly Bottom Assembly (Top View) Top Layer... -
Page 19: Bottom Layer (Top View)
Board Layout Figure 1–7. Bottom Layer (Top VIew) Bottom Layer (Top View) Introduction 1-11... - Page 20 1-12...
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Page 21: Design Procedure
The SLVP111–114 are dc-dc synchronous buck converter evaluation modules (EVMs) that provide a regulated output voltage at up to 6 A with a power input voltage range of 4.5 V to 6 V. A low power 12-V, 20-mA source is also required to power the TPS56xx controller. -
Page 22: Tps56Xx Functions
TPS56xx Functions 2.1 TPS56xx Functions The functional block diagram of the TPS56xx family of controllers is given in Figure 2–1. The controller has the following main features: 1% reference over 0 C to125 C junction temperature range. Synchronous-buck gate drivers with adaptive deadtime control High-side MOSFET driver voltage rating of 30 V MOSFET driver peak current rating of 2 A Hysteretic comparator: 250-ns propagation delay to gate driver outputs,... -
Page 23: Vcc Undervoltage Lockout
Figure 2–1. TPS56xx Functional Block Diagram INHIBIT UVLO 10 V V CC Deglitch 100mV Deglitch VOVP 1.15 VREF VSENSE Analog Bias I VREFB SLOWST Shutdown CM Filters Bandgap VREF Hysteresis VREFB AGND2 VREFB VHYST This section describes the functions governed by the TPS556xx. A procedure is given to determine the values of components used in the example design given in Figure 1–3. -
Page 24: Inhibit
TPS56xx Functions 2.1.2 Inhibit The inhibit circuit is a comparator with a 2.1-V start voltage and a 100-mV hysteresis. When inhibit is low, the output drivers are low and the slowstart capacitor is discharged. When inhibit is above the start threshold, the short across the slowstart capacitor is released and normal operation begins. -
Page 25: Hysteresis Setting
+ 3.3 V VREFB This value is used to determine the values of R10 and R14 that set the hysteresis level. The equations above can be used to derive a simplified relationship for the slowstart time as shown: SLOWSTART start-up waveforms for different reference voltage settings are given in Figures 3–7, 3–8, 3–9, 3–16, 3–17, 3–18, 3–25, 3–26, 3–27, 3–34, 3–35, and 3–36 in the test results section, showing that slowstart time is independent of the reference voltage. - Page 26 TPS56xx Functions Note that V To calculate V given in Section 2.2.4.2. They are repeated here for convenience: L = 1.5 H ESR = 10 m = 400 ns Now calculate V Since V does not depend on the output voltage setting, V tion of the total output voltage ripple for lower output voltages.
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Page 27: Noise Suppression
2.1.5 Noise Suppression Hysteretic regulators, by nature, have a fast response time to V and are thus inherently noise sensitive due to the very high bandwidth of the controller. Noise suppression circuits were added to the TPS56xx to improve the noise immunity, as shown in Figure 2–2. Internal low-pass filters with a pole frequency of 5 MHz were added to the inputs of the hysteretic comparator. -
Page 28: Vds Sensing Circuit
TPS56xx Functions Figure 1–3). This arrangement improves efficiency over solutions having a separate current sensing resistor. The drain of the high-side MOSFET is connected to HISENSE (pin 19). The source of the high-side MOSFET is connected to LOSENSE (pin 20). When the high-side MOSFET is on, a TPS56xx internal switch is also on and samples the source voltage of the high-side MOSFET. - Page 29 resistor-divider network is designed so that the voltage applied to OCP is 100 mV for the desired output current limit point. If the voltage on OCP exceeds 100 mV, a fault latch is set and the output drivers are turned off. The latch remains set until VCC (pin 15) goes below the undervoltage lockout value.
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Page 30: Overvoltage Protection
TPS56xx Functions An alternate current sensing scheme is to insert a current sense resistor in series with the drain of Q1. Higher accuracy may be obtained at the expense of lower efficiency. 2.1.7 Overvoltage Protection If V exceeds Vref by 15%, a fault latch is set and the output gate drivers are turned off. -
Page 31: Gate Driver Block Diagram
Figure 2–4. Gate Driver Block Diagram TPS56xx Synchronous-Buck Controller V CC 8 V Drive Regulator 12 V V REF LOWDR Adaptive Deadtime Control Figure 2–5 gives an I–V sweep of the low-side driver during sinking. The Rds(on) of the MOS transistors for the sink stage is 5 for the source stage. -
Page 32: I-V Characteristic Curve For Low-Side Gate Drivers
TPS56xx Functions Figure 2–5. I–V Characteristic Curve for Low-Side Gate Drivers The high-side gate driver is a bootstrap configuration with an internally integrated Schottky bootstrap diode. The voltage rating of the BOOT pin to DRVGND is 30 V. The gate drivers are biased from an internal 8-V drive regulator to minimize the gate drive power losses that are dissipated inside the TPS55xx. - Page 33 LOHIB (pin 11) is an inhibit input for the low-side MOSFET driver. This input has to be logic low before the low-side MOSFET is allowed to be turned on, i.e., a logic high on LOHIB prevents the low-side MOSFET driver from turning on the low-side MOSFET.
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Page 34: External Component Selection
External Component Selection 2.2 External Component Selection This section shows the procedure used in designing and selecting the power stage components to meet the performance parameters shown in Table 1–2 for the example circuit shown in Figure 1–3. 2.2.1 Duty Cycle Estimate An estimate of the duty cycle is used frequently in the following sections. - Page 35 External Component Selection performance in response to fast load transients encountered when supplying power to current- and next-generation microprocessors. A secondary consideration is the switching frequency resulting from the output filter component values. This section discusses important considerations when selecting/designing the output filter elements. A detailed analysis of the output voltage ripple characteristics is also presented, resulting in an expression for predicting the power supply switching frequency.
- Page 36 External Component Selection for the particular application. In addition, the capacitor(s) must have an ample ripple current rating to handle the applied ripple current. This ripple current is dependent on the ripple current in the output inductance that is calculated in the next section.
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Page 37: Switching Frequency Analysis
Where: = the voltage applied across the output inductor, TRAN t = the desired response time. For a load step from light load to heavy load, the voltage applied across the inductor can be assumed to be V is 100% as the output voltage is corrected. Alternatively, for a load step from heavy load to light load, the voltage across the inductor can be assumed to be . -
Page 38: Output Ripple Voltage Detail
External Component Selection Figure 2–6. Output Ripple Voltage Detail I AC V ESR V ESL t del V ripple Vp–p H yst t del t t off t on Figures 3–6, 3–15, 3–24, and 3–33 show the phase voltage (voltage at junction of high-side MOSFET with low-side MOSFET), and output voltage ripple waveforms for the example circuit of Figure 1–3. - Page 39 Peak to peak value of the inductor current I is given by the following equation: – Io DS ( on ) D I + Where: =the input voltage = the output voltage Ts = the switching period ) Io DS ( on ) is the duty cycle which is defined as : and t is the on time of the high-side MOSFET.
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Page 40: Power Mosfet Selection
External Component Selection of power losses and additional voltage drops through non-ideal components. Equation (4) should be sufficiently accurate for the first frequency estimate at the beginning of a design. 2.2.5 Power MOSFET Selection The TPS56xx is designed to drive N-channel power MOSFETs in a synchronous rectifier configuration. -
Page 41: Test Results
This chapter shows the test setups used, and the test results obtained, in designing the SLVP111–114 EVMS. Topic Test Summary ..........Test Setup . -
Page 42: Test Summary
Test Summary 3.1 Test Summary The detailed test results and waveforms are presented in Figures 3–2 to 3–10 for the SLVP111, Figures 3–11 to 3–19 for the SLVP112, Figures 3–20 to 3–28 for the SLVP113 and Figures 3–29 to 3–37 for the SLVP114. The following are summarized results. -
Page 43: Frequency Variation
in a linear fashion. There is no discernable overshoot in the waveforms. In this application, output voltage rise time is set to approximately 9 mS with an external capacitor. Although the EVMs have been tested with a very short Vcc rise time, (see Figures 3–26 and 3–35) it is recommended to keep the rise time of Vcc longer than 3mS as shown in Figures 3–8 and 3–17. -
Page 44: Conclusion
Test Summary 3.1.8 Conclusion The test results of the SLVP111/112/113/114 EVMs demonstrate the advantages of TPS56xx controllers to meet stringent supply requirements to power supplies, especially for powering DSPs and microprocessors. The power system designer has a good solution to optimize system for his particular application. -
Page 45: Test Setup
3.2 Test Setup Follow these steps for initial power up of the SLVP112: 1) Connect an electronic load from Vout to PwrGND (J1-15, -16, 2) Connect a 12-V lab power supply to the 12-V input (J1-7 3) Connect another lab power supply to the 5 V dc input of the 4) Turn on the 12-V lab supply. -
Page 46: Test Setup
Test Setup Figure 3–1. Test Setup 5V Power Supply – – – Load 12-V Power Supply... -
Page 47: Test Results
3.3 Test Results Figures 3–2 to 3–102 show test results for the SLVP111. Figure 3–2. SLVP111 Measured Load Regulation SLVP111 MEASURED LOAD REGULATION 3.305 3.295 3.29 3.285 Figure 3–3. SLVP111Measured Efficiency SLVP111 MEASURED EFFICIENCY Vin = 5 V Vin = 5.5 V Vin = 4.5 V I O –... -
Page 48: Slvp111Measured Power Dissipation
Test Results Figure 3–4. SLVP111Measured Power Dissipation SLVP111 MEASURED POWER DISSIPATION Figure 3–5. SLVP111Measured Switching Frequency SLVP111 MEASURED SWITCHING FREQUENCY Vin = 4.5 V Vin = 5 V Vin = 5.5 V I O – A Vin = 5.5 V Vin = 5 V Vin = 4.5 V I O –... -
Page 49: Slvp111 Measured Switching Waveforms
Figure 3–6. SLVP111 Measured Switching Waveforms 20 mV/div Figure 3–7. SLVP111Measured Start-Up (INHIBIT) Waveforms 2 V/div C3 Pk–Pk 50.8 mV C3 Frequency 130.088 kHz Low Signal V DS Q2 Amplitude 2 V/div C4 Max 5.20 V C4 + Duty 70.4% 2.5 s/div C3 Pk–Pk 3.36 V... -
Page 50: Slvp111 Measured Start-Up
Test Results Figure 3–8. SLVP111 Measured Start-Up (V 2 V/div Figure 3–9. SLVP111Measured Start-Up (V 2 V/div 3-10 ) Waveforms C3 Pk–Pk 3.36 V C3 Rise 7.300 ms Low Signal V CC (12 V) Amplitude 5 V/div C3 + Over 2.5% UVLO Threshold... -
Page 51: Slvp111 Measured Load Transient Waveforms
Figure 3–10. SLVP111 Measured Load Transient Waveforms Figure 3–11. SLVP112 Measured Load Regulation SLVP112 MEASURED LOAD REGULATION 2.51 2.505 2.495 100 mV/div C3 Pk–Pk 208 mV C2 High 6.5 V 5 A/div 6.5 A 2.5 s/div Vin = 5 V Vin = 5.5 V Vin = 4.5 V I O –... -
Page 52: Slvp112 Measured Efficiency
Test Results Figure 3–12. SLVP112 Measured Efficiency SLVP111 MEASURED EFFICIENCY Vin = 4.5 V Vin = 5.5 V Figure 3–13. SLVP112 Measured Power Dissipation SLVP111 MEASURED POWER DISSIPATION Vin = 5 V 3-12 Vin = 5 V I O – A Vin = 5.5 V Vin = 4.5 V I O –... -
Page 53: Slvp112 Measured Switching Frequency
Figure 3–14. SLVP112 Measured Switching Frequency SLVP112 MEASURED SWITCHING FREQUENCY Figure 3–15. SLVP112 Measured Switching Waveforms 20 mV/div Vin = 5.5 V Vin = 5 V Vin = 4.5 V I O – A C3 Pk–Pk 43.2 mV C3 Frequency 218.800 kHz Low Signal V DS Q2... -
Page 54: Slvp112 Measured Start-Up (Inhibit) Waveforms
Test Results Figure 3–16. SLVP112 Measured Start-Up (INHIBIT) Waveforms 1 V/div Figure 3–17. SLVP112 Measured Start-Up (V 2 V/div 3-14 C3 Pk–Pk 2.64 V C3 Rise 7.885 ms INHIBIT 1 V/div C3 + Over 3.2% 2.5 ms/div ) Waveforms C3 Pk–Pk 2.56 V C3 Rise 7.995 ms... -
Page 55: Slvp112 Measured Load Transient Waveforms
Figure 3–18. SLVP112 Measured Start-Up (V 1 V/div Figure 3–19. SLVP112 Measured Load Transient Waveforms 100 mV/div 2 A/div ) Waveforms C3 Pk–Pk 2.60 V C3 Rise 7.635 ms V IN (5 V) 1 V/div C3 + Over 3.2% 2.5 ms/div C3 Pk–Pk 200 mV C2 High... -
Page 56: Slvp113 Measured Load Regulation
Test Results Figure 3–20. SLVP113 Measured Load Regulation SLVP113 MEASURED LOAD REGULATION 1.805 Vin = 5.5 V 1.8025 Vin = 4.5 V 1.7975 1.795 Figure 3–21. SLVP113 Measured Efficiency SLVP113 MEASURED EFFICIENCY Vin = 4.5 V 3-16 Vin = 5 V I O –... -
Page 57: Slvp113 Measured Power Dissipation
Figure 3–22. SLVP113 Measured Power Dissipation SLVP113 MEASURED POWER DISSIPATION Vin = 5 V Figure 3–23. SLVP113 Measured Switching Frequency SLVP113 MEASURED SWITCHING FREQUENCY Vin = 5.5 V Vin = 4.5 V I O – A Vin = 5.5 V Vin = 5 V Vin = 4.5 V I O –... -
Page 58: Slvp113 Measured Switching Waveforms
Test Results Figure 3–24. SLVP113 Measured Switching Waveforms 20 mV/div Figure 3–25. SLVP113 Measured Start-Up (INHIBIT) Waveforms 1 V/div 3-18 C3 Pk–Pk 34.8 mV C3 Frequency 285.52 kHz Low Signal V DS Q2 Amplitude 2 V/div C5 Max 5.80 V C4 + Duty 40.4% 1 s/div... -
Page 59: Slvp113 Measured Start-Up
Figure 3–26. SLVP113 Measured Start-Up (V 2 V/div Figure 3–27. SLVP113 Measured Start-Up (V ) Waveforms C3 Pk–Pk 1.84 V C3 Rise 7.195 ms Low Signal V CC (12 V) Amplitude 5 V/div C3 + Over 2.3% 2.5 ms/div ) Waveforms C3 Pk–Pk 1.88 V 1 V/div... -
Page 60: Slvp113 Measured Load Transient Waveforms
Test Results Figure 3–28. SLVP113 Measured Load Transient Waveforms 100 mV/div Figure 3–29. SLVP114 Measured Load Regulation SLVP114 MEASURED LOAD REGULATION 1.499 1.498 1.497 1.496 1.495 1.494 Vin = 4.5 V 1.493 1.492 1.491 1.49 3-20 C3 Pk–Pk 112 mV C2 High 3.64 V 5 A/div... -
Page 61: Slvp114 Measured Efficiency
Figure 3–30. SLVP114 Measured Efficiency SLVP114 MEASURED EFFICIENCY Vin = 5 V Figure 3–31. SLVP114 Measured Power Dissipation SLVP114 MEASURED POWER DISSIPATION Vin = 4.5 V Vin = 5.5 V I O – A Vin = 5.5 V Vin = 5 V Vin = 4.5 V I O –... -
Page 62: Slvp114 Measured Switching Frequency
Test Results Figure 3–32. SLVP114 Measured Switching Frequency SLVP114 MEASURED SWITCHING FREQUENCY Figure 3–33. SLVP114 Measured Switching Waveforms 20 mV/div 3-22 Vin = 5.5 V Vin = 5 V Vin = 4.5 V I O – A C3 Pk–Pk 30.8 mV C3 Frequency 337.82 kHz V DS Q2... -
Page 63: Slvp114 Measured Start-Up (Inhibit) Waveforms
Figure 3–34. SLVP114 Measured Start-Up (INHIBIT) Waveforms 1 V/div Figure 3–35. SLVP114 Measured Start-Up (V 1 V/div C3 Pk–Pk 1.56 V C3 Rise 6.990 ms INHIBIT Low Signal 1 V/div Amplitude C3 + Over 2.8% 2.5 ms/div ) Waveforms C3 Pk–Pk 1.56 V C3 Rise 7.090 ms... -
Page 64: Slvp114 Measured Start-Up
Test Results Figure 3–36. SLVP114 Measured Start-Up (V 1 V/div Figure 3–37. SLVP114 Measured Load Transient Waveforms 3-24 ) Waveforms C3 Pk–Pk 1.56 V C3 Rise 7.07 ms Low Signal V IN (5 V) Amplitude 1 V/div C3 + Over 2.7% 2.5 ms/div 50 mV/div...
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