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Super X11SDD-8C/18C-F User's Manual
Hardware Prefetcher
If set to Enable, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L2 cache to improve CPU performance. The options are Disabled
and Enabled.
Adjacent Cache Line Prefetch
The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enabled. The
options are Disabled and Enabled.
DCU Streamer Prefetcher (Available when supported by the CPU)
Select Enable to enable the DCU (Data Cache Unit) Streamer Prefetcher, which will stream
and prefetch data and send it to the Level 1 data cache to improve data processing and
system performance. The options are Enable and Disable.
DCU IP Prefetcher (Available when supported by the CPU)
Select Enable for DCU (Data Cache Unit) IP Prefetcher support, which will prefetch IP
addresses to improve network connectivity and system performance. The options are Enable
and Disable.
LLC Prefetch
If set to Enable, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L3 cache to improve CPU performance. The options are Disable
and Enable.
Extended APIC (Advanced Programmable Interrupt Controller)
Based on the Intel Hyper-Threading technology, each logical processor (thread) is assigned
256 APIC IDs (APIDs) in 8-bit bandwidth. When this feature is set to Enable, the APIC ID
will be expanded from 8 bits to 16 bits to provide 512 APIDs to each thread to enhance CPU
performance. The options are Disable and Enable.
AES-NI
Select Enable to use the Intel Advanced Encryption Standard (AES) New Instructions (NI) to
ensure data security. The options are Disable and Enable.
Advanced Power Management Configuration
CPU P State Control
This feature allows the user to configure the following CPU power settings:
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