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PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor Free USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit...
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RSL10 Hardware Reference 11.4.1.1 Frame Signal Configuration and Timing ....326 11.4.1.2 Data Serial Input and Output Configuration ....329 11.4.2 PCM Interrupt Configuration.
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ON Semiconductor 12.1.1.7 CRC_ADD_32 ......354 12.1.1.8 CRC_FINAL ......354 12.2 Direct Memory Access (DMA) Controller...
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ON Semiconductor 14.3.4 Debug Fault Status Register ..... . 413 14.3.5 ARM Cortex-M3 Processor Debug Port Specific Control and Configuration Registers .
Bluetooth and other RF-based communication applications that make use of an RSL10 SoC. People who are developing local interfaces between an external device and RSL10, as well as those interested in the details of the audio, power supply and clocking components, will find this manual particularly helpful as it focuses on the configuration and use of system components.
Chapter 3: ARM Cortex-M3 Processor, provides an overview of the general-purpose ARM Cortex-M3 processor, its use in the RSL10 system, and its control and configuration registers. • Chapter 4: LPDSP32 Processor, provides an overview of the LPDSP32 DSP, its use in the RSL10 system, and its control and configuration registers. •...
YSTEM RCHITECTURE RSL10 is an ultra-low-power, highly flexible multi-protocol 2.4 GHz SoC specifically designed for use in high−performance wearable and medical applications, or any other applications that can benefit from low-power wireless connectivity. With its ARM Cortex-M3 Processor and LPDSP32 DSP core, RSL10 supports Bluetooth low energy technology and any 2.4 GHz proprietary protocol stacks, without sacrificing power consumption.
LE 2 Mb PHY feature first defined in the Bluetooth core 5.0 technology release, and all optional features of Bluetooth low energy technology that were also defined in earlier core releases. The RSL10 baseband stack is supplemented by support structures that enable implementation of ON Semiconductor and customer designed custom protocols.
OWER The RSL10 SoC is supplied from the VBAT pin, with a supply voltage in the range from 1.1 to 3.6 V in typical operating conditions. This supply is regulated by a DC-DC converter consisting of a low dropout voltage regulator (LDO) and a buck converter (can be used for VBAT >...
ARM Cortex-M3 processor through one or more of the processor’s standard buses. This structure supports the control and configuration of all of the components of an RSL10 SoC in any system, and simplifies control of the LPDSP32, the RF front-end and Bluetooth protocol baseband hardware.
SoCs, support components such as external non-volatile storage, and sensors. The RSL10 system uses a DIO (Digital Input/Output) concept, where any DIO pad can be configured in software at any time to connect with any interface input or output. The only exception is the debug SWD-JTAG interface, which has dedicated pads for the serial-wire inputs.
For more information about the peripherals, see Chapter 12, “Peripherals” on page 351 and Chapter 14, “Private Peripherals” on page 401. 2.8 A UDIO OMPONENTS The RSL10 SoC provides a set of interfaces and peripherals to assist in applications that have an audio component. This includes: • An Asynchronous Sample Rate Converter (ASRC) •...
RSL10 Hardware Reference Table 1. Microcontroller Identification Register Field Name Description Byte The chip technology family to which the microcontroller AHBREGS_CHIP_ID_NUM_CHIP_FAMILY belongs. Version number for the microcontroller. Used to indicate AHBREGS_CHIP_ID_NUM_CHIP_VERSION major updates that might not be backwards compatible. An update of the major revision number indicates updates...
3.1 I NTRODUCTION The ARM Cortex-M3 processor plays a role as the central controller for the RSL10 microcontroller system.The ARM Cortex-M3 processor provides users with an interface for configuring and controlling all of the other system components. Following a power-on reset (POR), the system starts executing the Boot ROM on the ARM Cortex-M3 processor, and uses this ROM application to validate and initialize a system application.
ON Semiconductor 3.1.1.1 SYSCTRL_CSS_LOOP_CACHE_CFG Bit Field Field Name Description CSS loop cache enable CSS_LOOP_CACHE_ENABLE Field Name Value Symbol Value Description Hex Value CSS loop cache disabled 0x0* CSS_LOOP_CACHE_ENABLE CSS_LOOP_CACHE_DISABLE CSS loop cache enabled CSS_LOOP_CACHE_ENABLE 3.2 D EBUG All applications executing on the ARM Cortex-M3 processor can be debugged through the SWJ-DP which can be configured to either serial wire or JTAG debug port communications.
RSL10 Hardware Reference To switch the SWJ-DP into serial wire mode, follow this initialization sequence: Send at least 50 clock cycles on SWCLK with the SWDIO pad held high. This ensures that the current interface is in its reset state.
SYSCTRL_DBG_LOCK lock key (0x4C6F634B). At startup and whenever the RSL10 system is reset, the debug port defaults to this locked status. After start-up and system initialization, the Program ROM then loads the value from the word stored to LOCK_INFO_SETTING in the flash NVR3 sector into the register.
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Unlock debug port access DBG_LOCK_WR DBG_ACCESS_UNLOCK Lock debug port access 0x4C6F634B DBG_ACCESS_LOCK Debug port access is unlocked DBG_LOCK_RD DBG_ACCESS_UNLOCKED Debug port access is locked 0x1* DBG_ACCESS_LOCKED 3.3.1.2 SYSCTRL_DBG_LOCK_KEY Bit Field...
ON Semiconductor 3.4.1.1 SYSCTRL_CNT_CTRL Bit Field Field Name Description Activity counters status bit CNT_STATUS Clear activity counters CNT_CLEAR Stop activity counters CNT_STOP Start activity counters CNT_START Field Name Value Symbol Value Description Hex Value Activity counters stopped 0x0* CNT_STATUS CNT_STOPPED...
ON Semiconductor 4.4 I NTERRUPT ANDLING To coordinate execution of data-processing functions on the LPDSP32 processor with data that is available to be processed, the LPDSP32 is supported by two sets of interrupts that can trigger execution on the LPDSP32: Each DMA channel can issue one application-defined command, triggered by the DMA channel’s enabled...
RSL10 Hardware Reference To enable the LPDSP32 debug port, set the bit from SYSCTRL_LPDSP32_DEBUG_CFG_LPDSP32_DEBUG_ENABLE register. To allow the LPDSP32 debug port to force the core into an enabled state SYSCTRL_LPDSP32_DEBUG_CFG when halted over the debug port, set the from the SYSCTRL_LPDSP32_DEBUG_CFG_LPDSP32_EXIT_POWERDOWN_WHEN_HALTED register.
ON Semiconductor Bit Field Field Name Description Write a 1 to issue DSS command 2 DSS_CMD_2 Write a 1 to issue DSS command 1 DSS_CMD_1 Write a 1 to issue DSS command 0 DSS_CMD_0 Field Name Value Symbol Value Description...
UPPLY VERVIEW The power supply is a critical component of the RSL10 system. Supplied power has significant effects on both RF and other types of system performance. The components that make up the power supply can be divided into two types of supply voltages: Power supply input voltages, described further in Section 5.2, “Power Supply Inputs”...
Section 5.4, “Power Modes” on page 51 5.2 P OWER UPPLY NPUTS 5.2.1 Battery Supply Voltage (VBAT) The primary voltage supplied to an RSL10 SoC is the battery supply voltage. This supply is used as the source for: www.onsemi.com...
The System Supply Voltage (VCC) is used as the source for all of the internally generated supply voltages in the RSL10 SoC, and is supplied from VBAT. This power supply is used to reduce the battery voltage from a high voltage range (from 1.1 to 3.6 V) down to a supply voltage in the range from 1.0 to 1.32 V.
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ACS_VCC_CTRL_BUCK_ENABLE ACS_VCC_CTRL register. In this mode, the RSL10 SoC only uses VBAT or the internal LDO to supply VCC. Use of this mode requires an external VCC filtering capacitor, but does not require an external DC-DC converter inductor. The DC-DC converter is a buck converter used to reduce the battery voltage from a high value (from 1.4 to 3.6 V) to a lower VCC voltage value (from 1.0 to 1.32 V) with high efficiency.
In this mode, the output ripple increases as VBAT decreases towards VCC - which might cause additional noise within the RSL10 system. To limit charge current in the DC-DC converter, the default setting of 80 mA (maximum output of 40 mA) is recommended. If the power supervisory circuit is resetting the system when using the DC-DC converter in the user circuit and under the user application’s operating conditions,...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Charge pump max current to 16 mA ICH_TRIM VCC_ICHTRIM_16MA Charge pump max current to 32 mA VCC_ICHTRIM_32MA Charge pump max current to 64 mA VCC_ICHTRIM_64MA Charge pump max current to 80 mA...
RSL10 Hardware Reference 5.3.2.1.1 ACS_BG_CTRL Bit Field Field Name Description 12:8 Temperature coefficient trimming SLOPE_TRIM Reference voltage trimming (2.5 mV steps) VTRIM Field Name Value Symbol Value Description Hex Value Temperature dependency 0 ppm/C 0xB* SLOPE_TRIM BG_SLOPE_TRIM_VALUE 0.6750 V VTRIM BG_TRIM_0P675V 0.6775 V...
ON Semiconductor , in the register, is the bit that controls the power amplifier ACS_VDDPA_CTRL_VDDPA_SW_CTRL ACS_VDDRF_CTRL supply, setting the output to HIZ in disable mode, and connecting the switched output to the VDDRF regulator (the Enable bit must be reset in this case). The...
1.06 V VDDPA_TRIM_1P06V 1.59 V 0x36 VDDPA_TRIM_1P59V 1.60 V 0x37* VDDPA_TRIM_1P60V 1.61 V 0x38 VDDPA_TRIM_1P61V 1.68 V 0x3F VDDPA_TRIM_1P68V 5.3.4 Digital Supply Voltages The RSL10 SoC includes internally regulated digital supply voltages, for which the calibrated settings are strongly recommended: www.onsemi.com...
ON Semiconductor • VDDC is the core digital voltage that is used for most of the RSL10 system’s digital components. • VDDCRET replaces VDDC in power modes that use state retention of the RSL10 system’s digital components. • VDDM is the memory digital voltage that is used for memories and memory-mapped elements of the RSL10 system.
RSL10 Hardware Reference 5.3.4.1.1 ACS_VDDC_CTRL Bit Field Field Name Description 21:16 VDDC standby voltage trimming (10 mV steps) STANDBY_VTRIM Low power mode control ENABLE_LOW_BIAS Sleep mode clamp control SLEEP_CLAMP Output voltage trimming configuration in 10 mV steps VTRIM Field Name...
ON Semiconductor Bit Field Field Name Description Sleep mode clamp control SLEEP_CLAMP Output voltage trimming configuration in 10 mV steps VTRIM Field Name Value Symbol Value Description Hex Value 0.75 V STANDBY_VTRIM VDDM_STANDBY_TRIM_0P75V 0.76 V VDDM_STANDBY_TRIM_0P76V 1.0 V 0x19 VDDM_STANDBY_TRIM_1P00V 1.08 V...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value VDDMRET trimming value 0x3* VDDMRET_VTRIM VDDMRET_TRIM_VALUE The VDDMRET retention regulator is 0x0* VDDMRET_ENABLE VDDMRET_DISABLE disabled The VDDMRET retention regulator is VDDMRET_ENABLE enabled VDDTRET trimming value 0x3* VDDTRET_VTRIM VDDTRET_TRIM_VALUE The VDDTRET retention regulator is...
The available power modes in RSL10 consist of Standby Mode, Sleep Mode, and Run Mode. Before entering Sleep Mode, RSL10 can be configured by the user to wake up from retention memory. RSL10 effectively uses power modes between RF events, while maintaining a Bluetooth low energy connection, and minimizing power consumption while in Standby Mode for duty cycled applications.
ROM and Flash are powered off, and used RAMs are placed in Retention Mode. The VDDC and VDDM regulator output voltages are set to their standby voltages. IMPORTANT: For an RSL10 SoC in standby, the 48 MHz crystal oscillator, RF block and STANDBY_VTRIM settings contribute significantly to the current of the battery (IBAT).
ON Semiconductor enables or disables the DC-DC overload flag’s wakeup functionality. ACS_WAKEUP_CFG_DCDC_OVERLOAD_EN bit controls whether wakeup occurs on the wakeup pad’s rising edge, ACS_WAKEUP_CFG_WAKEUP_PAD_POL enabling a pull-down, or on the falling edge, with a pull-up enabled. The bit (where * is ACS_WAKEUP_CFG_DIO*_POL 0 to 3) controls the wakeup polarity on DIO pads 0 to 3.
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Wait for 1 clock cycle DELAY WAKEUP_DELAY_1 Wait for 2 clock cycles WAKEUP_DELAY_2 Wait for 4 clock cycles WAKEUP_DELAY_4 Wait for 8 clock cycles WAKEUP_DELAY_8 Wait for 16 clock cycles WAKEUP_DELAY_16 Wait for 32 clock cycles (typ.10 us)
WAKEUP_DUE_TO_DIO0 5.4.5 Sleep Mode When operating in Sleep Mode, RSL10 will exhibit the lowest current consumption. Only the wakeup logic (see Section 5.4.4.1, “Wakeup Sources” on page 52 for sources of wakeup) is kept powered. The bandgap, regulators, RF block, etc. are disabled. The digital core and the memories can optionally be powered at low voltage.
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RSL10 Hardware Reference determines whether the reboot mode flag is set. ACS_WAKEUP_CTRL_BOOT_FLASH_APP_REBOOT controls whether the startup RC oscillator is at 3 or 12 MHz. ACS_WAKEUP_CTRL_RC_CLOCK_MULT bit configures whether or not the oscillators are treated as calibrated. ACS_WAKEUP_CTRL_RC_FTRIM_FLAG indicates whether the XTAL will start at boot.
ON Semiconductor The digital reset is released, enabling boot PROM execution unless the VDDC retention regulator is enabled. To use the RTC timer as wakeup source, refer to Section 6.3.5, “Real-Time Clock (RTC)” 5.4.5.1 Wakeup from Retention Memory in Sleep Mode...
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RSL10 Hardware Reference NOTE: To verify the wakeup pad value, read from the SYSCTRL_WAKEUP_PAD_WAKEUP_PAD_VALUE in the register (see Section 5.4.9, “SYSCTRL_WAKEUP_PAD” on SYSCTRL_WAKEUP_PAD page 63). IMPORTANT: To configure the memory retention, the following operations are required: • -> ACS_VDDRET_CTRL VDDMRET_VTRIM •...
ON Semiconductor Table 6. Possible Wakeup Restore Addresses Location Address DSP_DRAM0_END 0x20007FE8 DSP_DRAM1_END 0x20009FE8 DSP_DRAM2_END 0x2000BFE8 DSP_DRAM3_END 0x2000DFE8 DSP_DRAM4_END 0x2000FFE8 DSP_DRAM5_END 0x20011FE8 BB_DRAM0_END 0x20013FE8 BB_DRAM1_END 0x20015FE8 5.4.6 ACS_WAKEUP_CTRL Bit Field Field Name Description Enable / Disable the Retention Mode of the pads...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Disable the pad Retention Mode 0x0* PADS_RETENTION_EN PADS_RETENTION_DISABLE Enable the pad Retention Mode PADS_RETENTION_ENABLE The reboot mode flag is not set 0x0* BOOT_FLASH_APP_REBOOT BOOT_FLASH_APP_REBOOT_DISABLE The reboot mode flag is set (ROM will...
ON Semiconductor Field Name Value Symbol Value Description Hex Value DIO0 has not triggered a wakeup 0x0* DIO0_WAKEUP WAKEUP_DIO0_EVENT_NOT_SET event DIO0 has triggered a wakeup event WAKEUP_DIO0_EVENT_SET at least once Reset the sticky DCDC_OVERLOAD_CLEAR WAKEUP_DCDC_OVERLOAD_CLEAR WAKEUP_DCDC_OVERLOAD flag Reset the sticky...
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RSL10 Hardware Reference Bit Field Field Name Description PRAM1 access configuration PRAM1_ACCESS PRAM0 access configuration PRAM0_ACCESS Flash access configuration FLASH_ACCESS PROM access configuration PROM_ACCESS Field Name Value Symbol Value Description Hex Value DSP DRAM5 access disabled 0x0* DSP_DRAM5_ACCESS DSP_DRAM5_ACCESS_DISABLE DSP DRAM5 access enabled...
ESETS The RSL10 SoC contains a variety of reset sources that can be used to reset the entire RSL10 system, or a set of its system components. A system reset causes the system to restart, and status bits to be set for each of the relevant reset causes.
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RSL10 Hardware Reference their encoding can be seen in Figure 5, which also shows the ordering of reset flags. These flags remain set until cleared by writing to their associated clear flags. IMPORTANT: To clear the status bits that indicate the source of a reset, the...
• The dedicated NRESET pad: if a reset using this pad occurs, the bit will be set. PAD_RESET_FLAG Partial resets supported by the RSL10 system include: • The watchdog timer (see Section 12.4, “Watchdog Timer” on page 376): • If the ARM Cortex-M3 processor is still running when the watchdog reset occurs, the bit will be set.
RSL10 Hardware Reference 5.5.1.1 DIG_RESET_STATUS Bit Field Field Name Description Reset the sticky LOCKUP flag LOCKUP_RESET_FLAG_CLEAR Reset the sticky Watchdog time-out reset flag WATCHDOG_RESET_FLAG_CLEAR Reset the sticky ARM Cortex-M3 processor software reset flag CM3_SW_RESET_FLAG_CLEAR Reset the sticky ACS reset flag...
ON Semiconductor 5.5.2 ACS_RESET_STATUS Bit Field Field Name Description Sticky flag that detects that a timeout in the power up sequence occurred TIMEOUT_RESET_FLAG Sticky flag that detects that a clock detector reset occurred CLK_DET_RESET_FLAG Sticky flag that detects that a VDDA reset occurred (triggered by vdda_ready =...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value The VDDC reset has not triggered at VDDC_RESET_FLAG VDDC_RESET_FLAG_NOT_SET least once The VDDC reset was triggered at least 0x1* VDDC_RESET_FLAG_SET once since this status bit was last cleared The NRESET pad reset has not...
ON Semiconductor DIO0 can be used to output the RTC clock to control an external device. This mode is configured using the register, which has the following configurable bit-fields: ACS_AOUT_CTRL configures the RTC clock to be output to DIO0 starting at the defined interval, RTC_CLOCK_DIO0_START between 125 ms and 8 s.
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value No start event (DIO0 not driven) 0x0* RTC_CLOCK_DIO0_START DIO0_RTC_CLK_DISABLE Start to output RTC clock every 125 ms 0x1 DIO0_RTC_CLK_125MS Start to output RTC clock every 250 ms 0x2 DIO0_RTC_CLK_250MS...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Flash TM0 connected to AOUT 0x13 (continued) TEST_AOUT AOUT_TM0 Bandgap ready on AOUT (digital signal 0x14 AOUT_BG_READY using VSSA and VCC states) vcc_ready on AOUT (digital signal 0x15 AOUT_VCC_READY using VSSA and VCC states)
6.1 O VERVIEW All clocks and clock domains in the RSL10 system are derived from the system clock (SYSCLK) or the standby clock (STANDBYCLK). Because of its importance to the functioning of RSL10 and the execution of applications, SYSCLK can be generated from one of five different sources for maximum flexibility.
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RSL10 Hardware Reference Figure 6. Clock Distribution www.onsemi.com...
6.2.3 Standby RC Oscillator The standby RC oscillator is a ring oscillator that produces a trimmable output clock that can be used by the RSL10 system as a source for STANDBYCLK, and hence as a source for the RTC. This oscillator produces a nominal output...
RSL10 Hardware Reference frequency of 32 kHz. Enable the standby RC oscillator by setting the bit from the ACS_RCOSC_CTRL_RC_OSC_EN register. ACS_RCOSC_CTRL The frequency of the standby RC oscillator is trimmed using the bit-field from the ACS_RCOSC_CTRL_FTRIM_32K register. The trimming range for this oscillator can be shifted down by approximately 25%...
6.2.6 Debug Port Clock The JTCK signal from the SWJ-DP interface in the RSL10 system can be used as an external input clock source that supplies SYSCLK. Prior to use in clocking the system, this clock is prescaled using the bit-field from the register.
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value The startup RC Oscillator is at 3 MHz 0x0* CLOCK_MULT RC_START_OSC_3MHZ The startup RC Oscillator is at 12 MHz 0x1 RC_START_OSC_12MHZ The 32kHz RC Oscillator is disabled 0x0* RC_OSC_EN...
LOCK ISTRIBUTION 6.3.1 System Clock (SYSCLK) The system clock (SYSCLK) is the primary clock for the RSL10 system and all other clocks except STANDBYCLK. The internal clock structures for the RF front-end are derived from SYSCLK. bit field from the...
6.3.2 Standby Clock (STANDBYCLK) The RSL10 system includes a standby clock (STANDBYCLK) that is used as the source for the RTC (see Section 6.3.5, “Real-Time Clock (RTC)”), and can be used as the source for SYSCLK in standby operating modes.
ON Semiconductor • Further divided forms of SLOWCLK (SLOWCLK_DIV2, SLOWCLK_DIV32), which are used as the source for: • The general purpose timers, which select between SLOWCLK_DIV2 and SLOWCLK_DIV32 (see Section 12.3, “Timers” on page 373) • The watchdog timer, which uses SLOWCLK_DIV32 (see Section 12.4, “Watchdog Timer” on page 376)
The user clock is an output clock that you can use as a clock source for the PCM interfaces or for any external components. This clock is not used internally by the RSL10 system, so its usage can depend entirely on the outside needs of the larger system containing RSL10.
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The PCM interface does not have its own divided clock, but is asynchronously clocked relative to the clock input provided at the PCM clock input pad. This clock source can be provided by the RSL10 system by routing a clock output to the same DIO that is acting as the PCM clock input (see Section 10.2, “Functional Configuration”...
ON Semiconductor 6.3.9.2 CLK_DIV_CFG0 Bit Field Field Name Description 27:16 Prescale value for the USR clock (1 to 4096 in steps of 1) USRCLK_PRESCALE 10:8 Prescale value for the Baseband peripheral clock (1 to 8 in steps of 1) BBCLK_PRESCALE...
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RSL10 Hardware Reference Bit Field Field Name Description 13:8 Prescale value for the PWM1 peripheral clock (1 to 64 in steps of 1) PWM1CLK_PRESCALE Prescale value for the PWM0 peripheral clock (1 to 64 in steps of 1) PWM0CLK_PRESCALE Field Name...
ON Semiconductor 6.3.9.4 CLK_DIV_CFG2 Bit Field Field Name Description Charge pump clock disable CPCLK_DISABLE 13:8 Prescale value for the charge pump clock from the SLOWCLK clock (1 to 64 in CPCLK_PRESCALE steps of 1) DC-DC converter clock disable DCCLK_DISABLE Prescale value for the DC-DC converter clock (1 to 64 in steps of 1)
RSL10 Hardware Reference 6.3.9.5 ACS_RTC_CFG Bit Field Field Name Description 31:0 Start value for the RTC timer counter (counts from start_value down to 0) START_VALUE Field Name Value Symbol Value Description Hex Value Divide by 1 START_VALUE RTC_CNT_START_0 Divide by 2...
ON Semiconductor Field Name Value Symbol Value Description Hex Value RTC alarm is disabled 0x0* ALARM_CFG RTC_ALARM_DISABLE RTC alarm on counter bit 7 rising edge RTC_ALARM_7P8125MS (7.8125 ms) RTC alarm on counter bit 8 rising edge RTC_ALARM_15P625MS (15.625 ms) RTC alarm on counter bit 9 rising edge RTC_ALARM_31P25MS (31.25 ms)
4 kHz. This clock selection is automatically controlled by the underlying power-supply state machines of the RSL10 SoC, selecting the following clock sources for each mode: System startup RC oscillator (see Section 6.2.1, “RC Oscillator”...
ON Semiconductor When enabled, the clock detector can be used to trigger the interrupt. Configuration of this interrupt CLKDET_IRQ uses the bit field from the register, which can be configured to CLK_DET_CFG_CLK_DET_INT_SEL CLK_DET_CFG cause an interrupt if: • The monitored clock source becomes active •...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value No clock detected 0x0* CLK_DET_ENABLE CLK_DET_DISABLE Clock detected CLK_DET_ENABLE 6.4.3.2 CLK_DET_STATUS Bit Field Field Name Description Clock detector interrupt status (cleared when read) CLK_DET_INT_STATUS Clock detector status CLK_DET_STATUS Field Name...
All memories are accessible through the ARM Cortex-M3 processor, although some interfaces and peripherals provide additional access paths to specific memory elements. The connections to the components that make up the memory for the RSL10 system are shown in Figure 7. Private Peripheral Registers...
ON Semiconductor Table 7. RSL10 Memory Instances (Continued) Instance Name Size (bytes) Type Start Address Non-Volatile Record (NVR) 4 1024 Flash 0x00081800 (Manufacturing Test) Program RAM (x4) 4 x 8192 0x00200000 DSP (Program RAM) 4 x 10240 0x00220000 Data RAM...
SAGE 7.2.1 ARM Cortex-M3 Processor Memory Usage The memory provided on the RSL10 SoC is divided into five distinct areas with distinct uses. These areas are mapped into the RSL10 memory map, as shown in Figure 8 on page 97.
Shared RAM Instances Other Memory Mapped Areas These sections are mapped into the RSL10 memory map, as shown in Figure 8 on page 97. The address ranges are in hexadecimal format. The following subsections provide a brief description and usage of each.
NOTE: The system library provides the function to support reading the NVR4 sector. Sys_ReadNVR4() See the RSL10 Firmware Reference manual for more information. IMPORTANT: NVR 1-2-3 sectors are only guaranteed for 1,000 program and erase cycles versus 100,000 programming cycles for all other memory sectors.
SystemCoreClock function from the CMSIS library is executed (for more information see the RSL10 SystemCoreClockUpdate() Firmware Reference). IMPORTANT: A minimum SYSCLK frequency of 1 MHz is required to safely complete a flash memory operation.
ON Semiconductor • When used as program memory or flash memory overlay by the ARM Cortex-M3 processor, the DSP PRAM is seen as 32-bit words and appears in reversed order on the ARM Cortex-M3 processor memory map. Since the memory is 40-bit native, the upper byte each word is not used. The main purpose of the DSP PRAM is to mirror the frequently used functions of the software stack and the application stored in the flash memory.
RSL10 Hardware Reference 7.2.4 Other Memory Mapped Areas 7.2.4.1 Peripherals and Interfaces Memory-mapped registers on the peripheral bus are addressed between 0x4000 0000 and 0x400F FFFF (1 MB). This region contains the registers that are used to control various peripherals, interfaces, and other system components.
IMPORTANT: The flash memory library contains functions that the user application can use to perform writes. Refer to the RSL10 Firmware Reference for more information. NOTE: While writing to or erasing any flash memory, no flash memory instance can be accessed from the I-Code or D-Code buses.
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RSL10 Hardware Reference Table 8. Flash Low-Level Commands (Continued) Command Description Execute a non-sequential programming access: CMD_PROGRAM_NOSEQ • If ECC is enabled, a pair of 32-bit words is written to flash memory. • If ECC is disabled, a single 36-bit word is written to flash memory.
ON Semiconductor 7.3.2 Low Power Read Mode • By setting the bit of the configuration register, it is only possible to read the flash LP_MODE FLASH_IF_CTRL memory when its power supply voltage VDDA is between 2.25 V and 2.75 V with reduced power consumption.
RSL10 Hardware Reference 10. The command cannot be executed while the ARM Cortex-M3 processor runs a program CMD_PROGRAM_SEQ from the flash memory. 7.3.4 Locking / Unlocking Mechanism 7.3.4.1 Locking Mechanism A locking mechanism is included with the flash memory write hardware to prevent inadvertent writes to the flash memories.
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ON Semiconductor : indicates how many words are to be written to the destination (copier mode), or the FLASH_COPY_WORD_CNT number of words to be read and verified (comparator mode). : configures (copier or comparator), flash memory access (40-bit FLASH_COPY_CFG_MODE MODE...
RSL10 Hardware Reference flash memory copier acts as a DMA access regarding the priority handling between the flash memory copier, ARM Cortex-M3 processor, LPDSP32 and baseband controller. NOTE: While the flash memory copier is running, it constantly tries to read from the flash memory and write to its destination memory.
ON Semiconductor Field Name Value Symbol Value Description Hex Value DSP_PRAM2 is not mapped on the 0x0* DSP_PRAM2_OVERLAY_CFG DSP_PRAM2_OVERLAY_DISABLE Flash addressing range DSP_PRAM2 is also mapped on the DSP_PRAM2_OVERLAY_ENABLE Flash addressing range DSP_PRAM3 is not mapped on the 0x0* DSP_PRAM3_OVERLAY_CFG...
RSL10 Hardware Reference Field Name Value Symbol Value Description Value No baseband memory error detected 0x0* BB_MEM_ERROR BB_MEM_NO_ERROR_DETECTED Baseband has accessed an isolated BB_MEM_ERROR_DETECTED memory No Flash copier memory error 0x0* FLASH_COPIER_MEM_ERROR FLASH_COPIER_MEM_NO_ERROR_DETECTED detected Flash copier has accessed an isolated...
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ON Semiconductor Bit Field Field Name Description Flash power configuration FLASH_POWER PROM power configuration PROM_POWER Field Name Value Symbol Value Description Hex Value DSP DRAM5 power disabled DSP_DRAM5_POWER DSP_DRAM5_POWER_DISABLE DSP DRAM5 power enabled 0x1* DSP_DRAM5_POWER_ENABLE DSP DRAM4 power disabled DSP_DRAM4_POWER...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value PRAM1 power disabled PRAM1_POWER PRAM1_POWER_DISABLE PRAM1 power enabled 0x1* PRAM1_POWER_ENABLE PRAM0 power disabled PRAM0_POWER PRAM0_POWER_DISABLE PRAM0 power enabled 0x1* PRAM0_POWER_ENABLE Flash power disabled 0x0* FLASH_POWER FLASH_POWER_DISABLE Flash power enabled...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value DSP DRAM5 access disabled 0x0* DSP_DRAM5_ACCESS DSP_DRAM5_ACCESS_DISABLE DSP DRAM5 access enabled DSP_DRAM5_ACCESS_ENABLE DSP DRAM4 access disabled 0x0* DSP_DRAM4_ACCESS DSP_DRAM4_ACCESS_DISABLE DSP DRAM4 access enabled DSP_DRAM4_ACCESS_ENABLE DSP DRAM3 access disabled 0x0* DSP_DRAM3_ACCESS...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Flash access disabled 0x0* FLASH_ACCESS FLASH_ACCESS_DISABLE Flash access enabled FLASH_ACCESS_ENABLE PROM access disabled PROM_ACCESS PROM_ACCESS_DISABLE PROM access enabled 0x1* PROM_ACCESS_ENABLE 7.5.6 SYSCTRL_MEM_RETENTION_CFG Bit Field Field Name Description DSP PRAM5 retention configuration...
ON Semiconductor Field Name Value Symbol Value Description Hex Value DSP DRAM1 Normal Mode DSP_DRAM1_RETENTION DSP_DRAM1_NORMAL_MODE DSP DRAM1 Retention Mode 0x1* DSP_DRAM1_RETENTION_MODE DSP DRAM0 Normal Mode DSP_DRAM0_RETENTION DSP_DRAM0_NORMAL_MODE DSP DRAM0 Retention Mode 0x1* DSP_DRAM0_RETENTION_MODE DSP PRAM3 Normal Mode 0x0* DSP_PRAM3_RETENTION...
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RSL10 Hardware Reference Bit Field Field Name Description 19:18 DSP PRAM1 arbiter configuration DSP_PRAM1_ARBITER 17:16 DSP PRAM0 arbiter configuration DSP_PRAM0_ARBITER 11:10 Baseband DRAM1 arbiter configuration BB_DRAM1_ARBITER Baseband DRAM0 arbiter configuration BB_DRAM0_ARBITER DRAM1 and DRAM2 arbiter configuration DRAM12_ARBITER DRAM0 arbiter configuration...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value DSP has priority access to the DSP 0x0* DSP_PRAM2_ARBITER DSP_PRAM2_DSP_PRIORITY PRAM2 (above ARM Cortex-M3 core and DMA) ARM Cortex-M3 core has priority DSP_PRAM2_CM3_PRIORITY access to the DSP PRAM2 (above DSP and DMA)
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value ARM Cortex-M3 core has priority 0x0* DRAM12_ARBITER DRAM12_CM3_PRIORITY access to the DRAM1 and DRAM2 (above DSP and DMA) DSP has priority access to the DRAM1 DRAM12_DSP_PRIORITY and DRAM2 (above ARM Cortex-M3...
ON Semiconductor 7.6 F LASH EMORY EGISTERS Register Name Register Description Address Flash Interface Control Register 0x40000500 FLASH_IF_CTRL Flash Main Write Unlock Register 0x40000504 FLASH_MAIN_WRITE_UNLOCK Flash Main Write Control Register 0x40000508 FLASH_MAIN_CTRL Flash, Memory and RF Power-Up Delay Configuration 0x40000510...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Not pre-fetch the n+1 address on 0x0* PREFETCH_D_BUS FLASH_PREFETCH_D_BUS_DISABLE D-Bus Pre-fetch the n+1 address on D-Bus FLASH_PREFETCH_D_BUS_ENABLE Not pre-fetch the n+1 address on I-Bus 0x0* PREFETCH_I_BUS FLASH_PREFETCH_I_BUS_DISABLE Pre-fetch the n+1 address on I-Bus...
ON Semiconductor 7.6.3 FLASH_MAIN_CTRL Bit Field Field Name Description Authorize write access to the high part of the Flash Main block through the MAIN_HIGH_W_EN FLASH_IF registers. Authorize write access to the middle part of the Flash Main block through the MAIN_MIDDLE_W_EN FLASH_IF registers.
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value FLASH_DELAY_CTRLx set for a SYSCLK_FREQ FLASH_DELAY_FOR_SYSCLK_3MHZ SYSCLK = 3 MHz FLASH_DELAY_CTRLx set for a FLASH_DELAY_FOR_SYSCLK_4MHZ SYSCLK = 4 MHz FLASH_DELAY_CTRLx set for a 0x2* FLASH_DELAY_FOR_SYSCLK_5MHZ SYSCLK = 5 MHz...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Idle command 0x0* COMMAND CMD_IDLE Wakeup the Flash CMD_WAKE_UP Load patch and trimming values from CMD_LOAD_TRIM NVR4 Execute a read cycle CMD_READ Execute a non-sequential CMD_PROGRAM_NOSEQ programming cycle Starts a sequential programming...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value All NVR4 CBD0-CDB7 contents are 0x0* TRIMMED_STATUS FLASH_UNTRIMMED equal to 0xFFFF. eFlash untrimmed. Some registers CBD0-CBD7 contents FLASH_TRIMMED are not equal to 0xFFFF. eFlash trimmed. Flash can be accessed (isolation...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Indicates that the high part of the Flash 0x0* MAIN_HIGH_W_UNLOCK FLASH_MAIN_HIGH_W_LOCKED main section is protected against write accesses by the Flash interface Indicates that the high part of the Flash...
RSL10 Hardware Reference Bit Field Field Name Description Authorize Write access to the Flash NVR2 sector through the FLASH_IF NVR2_W_EN registers. Authorize Write access to the Flash NVR1 sector through the FLASH_IF NVR1_W_EN registers. Field Name Value Symbol Value Description...
ON Semiconductor Field Name Value Symbol Value Description Hex Value FLASH_DATA[1:0] compare with 0x0* COMP_MODE COMP_MODE_CONSTANT eFlash DOUT Odd address compare with COMP_MODE_CHBK FLASH_DATA[1:0], even address compare with inverse FLASH_DATA[1:0] Copy Flash to memory 0x0* COPY_DEST COPY_TO_MEM Copy Flash to CRC...
RSL10 Hardware Reference 7.6.16 FLASH_COPY_WORD_CNT Bit Field Field Name Description 16:0 Number of words to copy / compare COPY_WORD_CNT 7.6.17 FLASH_ECC_CTRL Bit Field Field Name Description 15:8 Select the number of corrected errors before sending a ARM Cortex-M3 core ECC_COR_CNT_INT_THRESHOLD...
ON Semiconductor Bit Field Field Name Description Reset the Flash address of the last detected error ECC_ERROR_ADDR_CLEAR FLASH_ECC_ERROR_COR_CNT status ECC_COR_ERROR_CNT_STATUS FLASH_ECC_ERROR_UNCOR_CNT status ECC_UNCOR_ERROR_CNT_STATUS Field Name Value Symbol Value Description Value Reset the Flash corrected errors ECC_COR_ERROR_CNT_CLEAR FLASH_ECC_COR_ERROR_CNT_CLEAR counter Reset the Flash uncorrected errors...
CHAPTER 8 RF Front-End 8.1 O VERVIEW The RF front-end (RFFE) transceiver is an ultra low-power 2.4 GHz radio, handling data rates up to 2 Mbps. It supports several wireless protocols such as Bluetooth low energy technology, custom, or proprietary protocols. The RF front-end communicates with: •...
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RSL10 Hardware Reference Figure 11. RFFE Block Diagram The RF front-end implements a full transceiver, with the following digital features: • FSK modem with programmable pulse shape and modulation index • Data-rate programmable from 3 Mbps to 62.5 kbps (4 Mbps with 4-FSK) •...
The RFFE implements the physical layer requirements of Bluetooth low energy technology, as accessed through the Bluetooth baseband hardware (see Chapter 9, “Bluetooth Low Energy Baseband” on page 203). It can also be used for a variety of standard (e.g., 802.15.4-based) protocols, proprietary protocols, and user- or ON Semiconductor-defined custom protocols.
RSL10 Hardware Reference • 00: the digital baseband is off (no clock). • 01: the clock is generated but the blocks are reset (Tx, Rx, FIFOs and finite state machine (FSM)). • 10: the digital baseband is frozen. • 11: working •...
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ON Semiconductor The RFFE has an internal SPI and 10 GPIOs; for more information see Section 11.8, “Support Interfaces” on page 348. The RFFE has a number of GPIOs that can be configured to assist in monitoring IRQs and other signals while debugging protocol implementations that use the RFFE.
RSL10 Hardware Reference RF_TXFIFO_IRQ Interrupt is raised when the is high. TXFIFO_NEAR_UNDERFLOW Since the IRQ is tied to the “near underflow” flag of the FIFO, it can be cleared by filling the FIFO with enough data. RF_RXFIFO_IRQ Interrupt is raised when the is high.
ON Semiconductor bit of the register. Pattern detection can accept some errors: this is useful with EN_PATTERN PACKET_HANDLING very short preambles, since the clock recovery is not yet complete. The maximum number of errors accepted in pattern recognition is located in the field of the register.
RSL10 Hardware Reference of the register to 1; in such a case, the RS accepts the normal address and the ADDRESS_RX_BR ADDRESS_CONF_EN broadcast address during reception. Confirmation of broadcast address reception is found in the field IS_ADDRESS_BR of the register.
ON Semiconductor Table 12. Bluetooth CRC24 Algorithm Parameters CRC Parameter Parameter Value Polynomial (hex) 0x00065B Initial Value (hex) 0x555555 or protocol defined Final XOR Value (hex) 0x000000 This hardware CRC implementation works on the serialized stream, so the bit order depends on the value.
RSL10 Hardware Reference During the reception of a message, many events can occur: for instance, a CRC error, or a packet length error. In all cases, the data must be stored in the FIFO, at least temporarily. If an event occurs, there are two choices: keep the data in the FIFO and let the external controller examine the content, or simply flush the received data.
ON Semiconductor Table 14. Supported Encoding and Decoding Options (Continued) Option Description Bit Order in Quadrature Modulations The bit order in quadrature modulation (especially O-QPSK) can be determined by the , and bits of the modulation. EVEN_BEFORE_ODD OFFSET I_NQ_DELAYED CODING...
RSL10 Hardware Reference 19 21 ----------------------------- - center_frequency refTx The RFFE chip has the option of having two different clock references, depending on the operational mode: Tx or Rx. The Tx reference clock is five times larger than the Rx clock. So to have the same frequency in Rx and Tx, the digital central frequency needs to be changed.
ON Semiconductor If the bit of the register is set to 1, the second half of the pulse shape is inverted. PULSE_NSYM MOD_TX NOTE: The modulation is obtained by converting both the convolution of the pulse shape and the data-stream into a series of pulses (not rectangles). In the case of a GFSK modulation, the specified pulse shape is not the impulse response of an exponential filter, but the convolution of this response with a rectangle that is 1 symbol long.
RSL10 Hardware Reference This value must be split into mantissa and exponent. The exponent is the floor of the log of M, which is 2. The resulting mantissa is 13. 2 ----- - 7.25 In the case of a 4-FSK modulation, the definition of index modulation must be considered to be the same, but this results in the additional deviations being at +3 and -3 times the nominal deviation.
ON Semiconductor 8.4.3 Rx Specific Configuration 8.4.3.1 Channel Filter Configuration The channel filter is not a digital block, but is digitally configurable, and its configurations might affect the digital baseband fine tuning. It is a polyphase filter, so its transfer function is not symmetrical; therefore, it rejects the image. Its central frequency and its bandwidth can be configured with three parameters.
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RSL10 Hardware Reference Interpolator Decimator ↑ ↓ phase in phase out deriv deriv Figure 14. Simplified Block Diagram of the Resampler Block for the Phase Note that in Figure 14, acc stands for “accumulator”, and deriv stands for “derivator”. While the RSSI can be resampled without any major problems, there might be an issue with the phase with this configuration if the signals are not handled correctly.
ON Semiconductor ---------- These gain are compensated for, through the : this variable is an unsigned word. The gain is RESAMPLE_PH_GAIN given by: resample_ph_gain 7 – -resample_rssi_g1 On the RSSI side, an additional gain is added after the interpolator. This gain is given by 2 .
RSL10 Hardware Reference The time constant of the fine carrier recovery block is found in the register. The block is TAU_PHASE_RECOV enabled by setting the bit of the register. EN_FINE_RECOV CARRIER_RECOVERY 8.4.3.3.3 Carrier Recovery Boundaries The carrier recovery block can recover the carrier in a specified range. Theoretically the range is expected to be as wide as possible, but there are some limitations.
ON Semiconductor 2 --- - 0 8 , It is easy to calculate that the closest values are e = -1 and m = 5: these values give K = 0.8125, and a carrier recovery range of ±152 kHz. So freq_lim_man(2:0) = 0b101 and freq_lim_exp(2:0) = 0b111 (the prefix 0b means a binary representation).
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RSL10 Hardware Reference Carrier Offset Estimation This is always performed; the only way to block it is to disable RSSI detection. Carrier offset estimation is carried out by accumulating the actual frequency for a variable number of samples. The number of samples is chosen using the...
ON Semiconductor give a false value, since the early estimation is made on data not yet corrected. The functionality is activated by the bit of the register being set to 1. EN_MIN_MAX_MF DEMOD_CTRL Fast Clock Recovery On the 4-FSK modulation, clock recovery is critical because the horizontal eye is quite close. In order to have a clock recovery that performs well, the time constant needs to be increased to filter the excessive noise on the zero crossings.
RSL10 Hardware Reference In the case of an FSK modulation, the phase signal at the input of the filter is converted to frequency, and goes through the FIR. In the case of a PSK modulation, the phase is converted to the linear domain by a simple look-up table (LUT), and the I and Q signals go through the filter.
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ON Semiconductor Table 15. Data-Rate Recovery Search Range dr_limit Search Range ±3.125% ±6.25% ±12.5% NOTE: For small data-rate mismatches – for example, if only ppm of crystal oscillators are responsible for a DR mismatch – a simple clock recovery is enough. Also, there is a potential issue in data-rate recovery if carrier recovery is not performed correctly.
RSL10 Hardware Reference This means that the time constant for the 4-FSK modulation needs to be increased in order to achieve better filtering and be more precise regarding the sampling time. The latter is especially important because, as can be seen in Figure 16, if the sampling time is not exact, there may be a wrong decision regarding the level.
ON Semiconductor • agc_level(8:7) — load of the intermediate frequency amplifier • 00: 16 k, max gain • 01: 8 k, 6dB of attenuation • 10: 4 k, 12dB of attenuation • 11: 2 k, 18dB of attenuation • agc_level(10:9) — select the LNA bias current.
The following steps describe how to use register settings to configure a CW signal output, for Tx or Rx, at a rate of either 1 Mbps or 2Mbps: Load the hci_app hex file into flash memory, and then reset the RSL10 Evaluation and Development Board. This ensures that the RF registers are set correctly.
ON Semiconductor When working in CW configuration, use your own preferred settings for VDDRF, VDDPA enabling, VCC, VDDPA, DCCLK, the charge pump clock, and buck enabling. 8.5 RF F RONT EGISTERS Register Name Register Description Address RF Power Configuration 0x40000050...
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ON Semiconductor Bit Field Field Name Description If set to 1 enables the differential coding/decoding MODE2_DIFF_CODING If set to 1, the PSK mode is selected, FSK otherwise. MODE2_PSK_NFSK 12:8 set the output testmode MODE2_TESTMODE In FSM mode, if set to 1 indicates to the FSM to go in suspend mode...
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RSL10 Hardware Reference Bit Field Field Name Description If set to 1 correct the AFC negatively CARRIER_RECOVERY_AFC_NEG If set to 1 enables the starter mode, i.e. a 32x faster carrier CARRIER_RECOVERY_STARTER_MODE recovery. if set to 1 enables the Automatic Frequency Control...
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ON Semiconductor Bit Field Field Name Description If set to 1, stops the Rx and flushes the FIFO in case of packet length FIFO_FIFO_FLUSH_ON_PL_ERR error If set to 1, stops the Rx and flushes the FIFO in case of CRC error...
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RSL10 Hardware Reference Bit Field Field Name Description If set to 1, flushes the Rx FIFO when the Rx is enabled, in order to receive a FIFO_2_RXFF_FLUSH_ON_START packet with an empty FIFO. If set to 1, flushes the Tx FIFO after the end of a packet transmission in order FIFO_2_TXFF_FLUSH_ON_STOP to have an empty FIFO.
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ON Semiconductor Bit Field Field Name Description Configuration of GPIO pad 5 PAD_CONF_3_PAD_5_CONF Configuration of GPIO pad 4 PAD_CONF_3_PAD_4_CONF Field Name Value Symbol Value Description Hex Value 0x0* MAC_CONF_MAC_TIMER_GR MAC_CONF_MAC_TIMER_GR_DEFAULT 0x0* MAC_CONF_RX_MAC_ACT MAC_CONF_RX_MAC_ACT_DEFAULT 0x0* MAC_CONF_RX_MAC_TX_NRX MAC_CONF_RX_MAC_TX_NRX_DEFAULT 0x0* MAC_CONF_RX_MAC_START_ MAC_CONF_RX_MAC_START_NSTOP_ NSTOP...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value 0x0* TX_MAC_TIMER_TX_MAC_TIMER TX_MAC_TIMER_TX_MAC_TIMER_ DEFAULT 0x0* RX_MAC_TIMER_RX_MAC_TIMER RX_MAC_TIMER_RX_MAC_TIMER_ DEFAULT 8.5.7 RF_CENTER_FREQ Bit Field Field Name Description If set to 1, automatically adapt frequency between Tx and Rx. CENTER_FREQ_ADAPT_CFREQ If set to 1, the ratio of the pll reference between Tx and Rx is 5 instead of 6.
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* MOD_INFO_RX_SYMBOL_2BIT_RX MOD_INFO_RX_SYMBOL_2BIT_RX_ DEFAULT 0x0* MOD_INFO_RX_DR_M_RX MOD_INFO_RX_DR_M_RX_DEFAULT 0x0* MOD_INFO_TX_EN_DIV_2_N3_TX MOD_INFO_TX_EN_DIV_2_N3_TX_ DEFAULT 0x0* MOD_INFO_TX_SYMBOL_2BIT_TX MOD_INFO_TX_SYMBOL_2BIT_TX_ DEFAULT 0x0* MOD_INFO_TX_DR_M_TX MOD_INFO_TX_DR_M_TX_DEFAULT 8.5.9 RF_REG08 Bit Field Field Name Description 31:24 The packet length in the fixed packet length mode. In the variable packet PACKET_LENGTH_PACKET_LEN length mode, it specifies the maximal packet length defined by the standard.
ON Semiconductor Bit Field Field Name Description If set to 1, the packet length is fixed and specified in the PACKET_LEN PACKET_LENGTH_OPTS_EN_PACKET register _LEN_FIX Signed value that specifies the correction to apply to the specified packet PACKET_LENGTH_OPTS_PACKET_ length (due to differences between standards). The packet length here is...
RSL10 Hardware Reference 8.5.12 RF_SYNC_PATTERN Bit Field Field Name Description 31:0 Pattern (sync word) to be inserted or recognized. PATTERN Field Name Value Symbol Value Description Hex Value 0x0* PATTERN PATTERN_DEFAULT 8.5.13 RF_REG0C Bit Field Field Name Description 30:26 polynom of the third convolutional code...
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* PACKET_EXTRA_EN_STOP_WORD PACKET_EXTRA_EN_STOP_WORD_ DEFAULT 0x0* PACKET_EXTRA_PKT_INFO_PRE_ PACKET_EXTRA_PKT_INFO_PRE_ NPOST NPOST_DEFAULT 0x0* PACKET_EXTRA_PATTERN_MAX_ PACKET_EXTRA_PATTERN_MAX_ ERR_DEFAULT 0x0* PACKET_EXTRA_PATTERN_WORD_ PACKET_EXTRA_PATTERN_WORD_ LEN_DEFAULT 8.5.14 RF_CRC_POLYNOMIAL Bit Field Field Name Description 31:0 CRC polynomial. It is coded using the Koopman notation, i.e. the nth bit codes CRC_POLYNOMIAL_CRC_POLY the (n+1) coefficient.
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* FRONTEND_EN_RESAMPLE_RSSI FRONTEND_EN_RESAMPLE_RSSI_ DEFAULT 0x0* FRONTEND_EN_RESAMPLE_PHADC FRONTEND_EN_RESAMPLE_PHADC_ DEFAULT 0x0* FRONTEND_DIV_PHADC FRONTEND_DIV_PHADC_DEFAULT 0x0* TX_MULT_TX_MULT_EXP TX_MULT_TX_MULT_EXP_DEFAULT 0x0* TX_MULT_TX_MULT_MAN TX_MULT_TX_MULT_MAN_DEFAULT 0x0* TX_FRAC_CONF_TX_FRAC_DEN TX_FRAC_CONF_TX_FRAC_DEN_ DEFAULT 0x0* TX_FRAC_CONF_TX_FRAC_NUM TX_FRAC_CONF_TX_FRAC_NUM_ DEFAULT 8.5.18 RF_TX_PULSE0 Bit Field Field Name...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value 0x0* TX_PULSE_SHAPE_2_TX_COEF8 TX_PULSE_SHAPE_2_TX_COEF8_ DEFAULT 0x0* TX_PULSE_SHAPE_2_TX_COEF7 TX_PULSE_SHAPE_2_TX_COEF7_ DEFAULT 0x0* TX_PULSE_SHAPE_2_TX_COEF6 TX_PULSE_SHAPE_2_TX_COEF6_ DEFAULT 0x0* TX_PULSE_SHAPE_2_TX_COEF5 TX_PULSE_SHAPE_2_TX_COEF5_ DEFAULT 8.5.20 RF_TX_PULSE2 Bit Field Field Name Description 31:24 TX_PULSE_SHAPE_3_TX_COEF12 23:16 TX_PULSE_SHAPE_3_TX_COEF11 15:8 TX_PULSE_SHAPE_3_TX_COEF10...
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* TX_PULSE_SHAPE_4_TX_COEF14 TX_PULSE_SHAPE_4_TX_COEF14_ DEFAULT 0x0* TX_PULSE_SHAPE_4_TX_COEF13 TX_PULSE_SHAPE_4_TX_COEF13_ DEFAULT 8.5.22 RF_RX_PULSE Bit Field Field Name Description 31:28 RX_PULSE_SHAPE_RX_COEF8 27:24 RX_PULSE_SHAPE_RX_COEF7 23:20 RX_PULSE_SHAPE_RX_COEF6 19:16 RX_PULSE_SHAPE_RX_COEF5 15:12 RX_PULSE_SHAPE_RX_COEF4 11:8 RX_PULSE_SHAPE_RX_COEF3 RX_PULSE_SHAPE_RX_COEF2 These registers specify the Rx pulse shape. The pulse shape is formed by: RX_PULSE_SHAPE_RX_COEF1 coef1-coef8-coef8-coef1.
RSL10 Hardware Reference Bit Field Field Name Description Mantissa of the final stage gain of the matched filter FILTER_GAIN_FILTER_GAIN_M Exponent of the final stage gain of the matched filter FILTER_GAIN_FILTER_GAIN_E Field Name Value Symbol Value Description Hex Value 0x0* RX_IF_RESAMPLE_PH_IF...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value 0x0* RSSI_BANK_TAU_RSSI_FILTERING RSSI_BANK_TAU_RSSI_ FILTERING_DEFAULT 0x0* DECISION_USE_VIT_SOFT DECISION_USE_VIT_SOFT_ DEFAULT 0x0* DECISION_VITERBI_LEN DECISION_VITERBI_LEN_ DEFAULT 0x0* DECISION_VITERBI_POW_NLIN DECISION_VITERBI_POW_NLIN_ DEFAULT 0x0* DECISION_EN_VITERBI_GFSK DECISION_EN_VITERBI_GFSK_ DEFAULT 8.5.26 RF_REG19 Bit Field Field Name Description 29:28 Same as pll_filter_res_trim but for Tx case. Real value in Tx is pll_filter_res_trim PLL_BANK_PLL_FILTER_RES_ xor pll_filter_res_trim_tx.
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* CLK_CH_FILTER_DIV_RSSI CLK_CH_FILTER_DIV_RSSI_ DEFAULT 0x0* CLK_CH_FILTER_DIV_FILT CLK_CH_FILTER_DIV_FILT_ DEFAULT 8.5.27 RF_REG1A Bit Field Field Name Description 31:28 Maximum attenuation level in AGC algorithm ATT_CTRL_ATT_CTRL_MAX 27:24 Attuenuation level if the AGC is bypassed...
RSL10 Hardware Reference 8.5.28 RF_REG1B Bit Field Field Name Description If set to 1 enables the Tx data-whitening before the convolutional code IEEE802154_OPTS_EN_DW_TEST block 30:29 sets the clock output mode for BER mode or RW mode: 00 => data change IEEE802154_OPTS_BER_CLK_MODE on falling edge, 01 =>...
ON Semiconductor 8.5.29 RF_AGC_LUT1 Bit Field Field Name Description 31:22 Look up table with the AGC values: agc_level_0 is supposed the lowest AGC_LUT_1_AGC_LEVEL_2_LO attenuation, while agc_level_11 is the one with a maximum of attenuation. 21:11 Look up table with the AGC values: agc_level_0 is supposed the lowest AGC_LUT_1_AGC_LEVEL_1 attenuation, while agc_level_11 is the one with a maximum of attenuation.
RSL10 Hardware Reference Bit Field Field Name Description 12:2 Look up table with the AGC values: agc_level_0 is supposed the lowest AGC_LUT_3_AGC_LEVEL_6 attenuation, while agc_level_11 is the one with a maximum of attenuation. Look up table with the AGC values: agc_level_0 is supposed the lowest AGC_LUT_3_AGC_LEVEL_5_HI attenuation, while agc_level_11 is the one with a maximum of attenuation.
ON Semiconductor Bit Field Field Name Description 10:8 Fixes the granularity of the timer in Rx mode. The granularity is given by TIMINGS_1_T_GRANULARITY_RX (2^(t_granularity))x1us Look up table with the AGC values: agc_level_0 is supposed the lowest AGC_LUT_5_AGC_LEVEL_11_HI attenuation, while agc_level_11 is the one with a maximum of attenuation.
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value 0x3* AGC_ATT_1_AGC_ATT_34 AGC_ATT_1_AGC_ATT_34_DEFAULT 0x3* AGC_ATT_1_AGC_ATT_23 AGC_ATT_1_AGC_ATT_23_DEFAULT 0x3* AGC_ATT_1_AGC_ATT_12 AGC_ATT_1_AGC_ATT_12_DEFAULT 0x3* AGC_ATT_1_AGC_ATT_01 AGC_ATT_1_AGC_ATT_01_DEFAULT 8.5.35 RF_REG22 Bit Field Field Name Description If set to 1 enables filter Tx configuration for the fast Rx PLL...
ON Semiconductor Bit Field Field Name Description 23:20 PA backoff bias BIAS_0_IQ_RXTX_1 19:16 PA bias BIAS_0_IQ_RXTX_0 14:12 Select the number of wait states during the APB transaction INTERFACE_CONF_APB_WAIT_ STATE Select the spi mode: 00 legacy spi, 01 advanced spi, 10 BLIM4SME spi...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value 0x0* BIAS_4_IQ_PLL_1 BIAS_4_IQ_PLL_1_DEFAULT 0x0* BIAS_3_IQ_RXTX_8 BIAS_3_IQ_RXTX_8_DEFAULT 0x0* BIAS_3_IQ_RXTX_7 BIAS_3_IQ_RXTX_7_DEFAULT 0x0* BIAS_2_IQ_RXTX_6 BIAS_2_IQ_RXTX_6_DEFAULT 0x0* BIAS_2_IQ_RXTX_5 BIAS_2_IQ_RXTX_5_DEFAULT 8.5.38 RF_REG25 Bit Field Field Name Description 31:28 Peak detector threshold bias 0 BIAS_9_IQ_BB_6...
ON Semiconductor Bit Field Field Name Description Peak detector threshold bias 1 BIAS_10_IQ_BB_8 Peak detector threshold bias 2 BIAS_10_IQ_BB_7 Field Name Value Symbol Value Description Hex Value 0x0* SD_MASH_MASH_ENABLE SD_MASH_MASH_ENABLE_DEFAULT 0x0* SD_MASH_MASH_DITHER SD_MASH_MASH_DITHER_DEFAULT 0x0* SD_MASH_MASH_ORDER SD_MASH_MASH_ORDER_DEFAULT 0x0* SD_MASH_MASH_RSTB SD_MASH_MASH_RSTB_DEFAULT 0x0*...
RSL10 Hardware Reference 8.5.41 RF_REG28 Bit Field Field Name Description If set to 1 switch the low-pass filter in the Rx chain CTRL_RX_SWITCH_LP If set to 1, the peak detector is powered on during the Rx by the FSM CTRL_RX_USE_PEAK_DETECTOR...
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* CTRL_RX_CTRL_RX CTRL_RX_CTRL_RX_DEFAULT 0x0* SWCAP_FSM_SB_CAP_RX SWCAP_FSM_SB_CAP_RX_DEFAULT 0x0* SWCAP_FSM_SB_CAP_TX SWCAP_FSM_SB_CAP_TX_DEFAULT 0x0* DLL_CTRL_CK_LAST_SEL_DELAY DLL_CTRL_CK_LAST_SEL_DELAY_ DEFAULT 0x0* DLL_CTRL_CK_FIRST_SEL_DELAY DLL_CTRL_CK_FIRST_SEL_DELAY_ DEFAULT 0x0* DLL_CTRL_CK_EXT_SEL DLL_CTRL_CK_EXT_SEL_DEFAULT 0x0* DLL_CTRL_CK_DIG_EN DLL_CTRL_CK_DIG_EN_DEFAULT 0x0* DLL_CTRL_CK_TEST_EN DLL_CTRL_CK_TEST_EN_DEFAULT 0x0* DLL_CTRL_TOO_FAST_ENB DLL_CTRL_TOO_FAST_ENB_DEFAULT 0x0*...
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RSL10 Hardware Reference Bit Field Field Name Description Debug: charge-pump offset current values selection bits (see bit 6 to enable this PLL_CTRL_1_CHP_CURR_ mode): 00 => d_phi = 15, 01 => d_phi=22.5, 10 => d_phi = 30, 11 => d_phi = 60.
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* PLL_CTRL_1_FAST_CHP_EN PLL_CTRL_1_FAST_CHP_EN_DEFAULT 0x0* PLL_CTRL_1_CHP_MODE_TRIM PLL_CTRL_1_CHP_MODE_TRIM_ DEFAULT 0x0* PLL_CTRL_1_CHP_CMC_EN PLL_CTRL_1_CHP_CMC_EN_DEFAULT 0x0* PLL_CTRL_1_CHP_CURR_OFFSET_EN PLL_CTRL_1_CHP_CURR_OFFSET_EN_ DEFAULT 8.5.43 RF_REG2A Bit Field Field Name Description If set to 1, the en PPA cascode bit is independent from the en PA...
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RSL10 Hardware Reference Bit Field Field Name Description Xtal oscillator enable (active low) XTAL_CTRL_XO_EN_B_REG 15:14 Xtal trimming speed: 00 => 43us, 01 => 85us, 10 => 171us, 11 => 341us XTAL_CTRL_XTAL_CKDIV When high, disable the output clock to go to main IP (clk_out output stay XTAL_CTRL_CLK_OUT_EN_B low).
RSL10 Hardware Reference Bit Field Field Name Description If set to 1 enables the early fine recovery after the packet detection or DEMOD_CTRL_EARLY_FINE_RECOV pre-sync Number of samples to estimate the carrier offset: 0 -> 32, 1 -> 64, 2 -> 128, RSSI_DETECT_RSSI_DET_CR_LEN 3->256...
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ON Semiconductor Bit Field Field Name Description If set to 1 enables the pull-up of the GPIO pads PADS_PE_DS_GPIO_PE If set to 1 enables the pull-up of the nreset pad PADS_PE_DS_NRESET_PE If set to 1 enables the pull-up of the MISO SPI pad...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value 0x0* SYNC_WORD_CORR_EN_SYNC_WORD_CORR SYNC_WORD_CORR_EN_SYNC_WORD_ CORR_DEFAULT 0x0* SYNC_WORD_CORR_SYNC_WORD_BIAS SYNC_WORD_CORR_SYNC_WORD_BIAS_ DEFAULT 8.5.49 RF_REG30 Bit Field Field Name Description 31:25 Start the bist test on the Rx FIFO (code 0x5d) RXFIFO_STATUS_BIST 31:30 Indicate the BIST error: 00 => no error, 01 => error in checkboard test, 10 RXFIFO_STATUS_BIST_ERRORS =>...
ON Semiconductor 8.5.50 RF_REG31 Bit Field Field Name Description 31:24 Maximum RSSI value over a filtering period RSSI_MAX_RSSI_MAX 23:16 Minimum RSSI value over a filtering period RSSI_MIN_RSSI_MIN 15:8 Number of bytes in the Rx FIFO RXFIFO_COUNT_RX_COUNT Number of bytes in the Tx FIFO TXFIFO_COUNT_TX_COUNT 8.5.51 RF_REG32...
RSL10 Hardware Reference 8.5.55 RF_IRQ_STATUS Bit Field Field Name Description Is set to 1 when the IRQ RXFIFO is active IRQ_STATUS_FLAG_RXFIFO Is set to 1 when the IRQ TXFIFO is active IRQ_STATUS_FLAG_TXFIFO Is set to 1 when the IRQ SYNC is active...
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* ANALOG_INFO_CLK_DIG_READY ANALOG_INFO_CLK_DIG_NOT_READY ANALOG_INFO_CLK_DIG_READY 8.5.59 RF_REVISION Bit Field Field Name Description 29:24 Version of the chip: 0x00: v1, 0x10: v2A, 0x11: v2B, 0x12: v2C, 0x13: v2D, 0x14: CHIP_ID v2E, 0x20: v3...
Figure 18. This supplements the physical layers implemented by the RF front-end (refer to Chapter 8, “RF Front-End” on page 133) and the L2CAP and host layers that are supported by the Bluetooth stack firmware (refer to the “Bluetooth Stack and Profiles” chapter from the RSL10 Firmware Reference). www.onsemi.com...
• The hardware aspects of the security manager as accessible through the GAP layer See the RSL10 Firmware Reference for more information about host and profile layer support. 9.1.1 Bluetooth Baseband Error Handling This interrupt indicates that a hardware error has been detected. The error type can be recovered by reading the...
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Indicates whether two consecutive and concurrent CONCEVTIRQ_ERROR have been generated, and not acknowledged in 1: Error occurred ble_event_irq time by the RSL10 software. 0: No error Indicates whether Rx data buffer pointer value programmed is null: RXDATA_PTR_ERROR this is a major programming failure.
RSL10 Hardware Reference Table 17. ERRORTYPESTAT Description (Continued) Command Value Description 0: No error Indicates Anticipated Pre-Fetch Mechanism error: happens when 2 EVT_CNTL_APFM_ERROR consecutive events are programmed, and the first event is not 1: Error occurred completely finished while second pre-fetch instant is reached.
ON Semiconductor The abstraction layer contains a few primitives, allowing atomic read/writes and copies of data from system RAM to exchange memory. 9.2.1 Baseband Abstraction Layer Primitives The following functions and macros are used by the link layer software to access the baseband registers, exchange...
Area Figure 20. Control Structure Allocation IMPORTANT: The exchange memory provided by the RSL10 SoC supports a maximum of 31 links; however, the default Bluetooth stack firmware may be built to support fewer links, for power and memory efficiency. If your user application requires more links than the Bluetooth library builds described in the RSL10 Firmware Reference can support, contact your ON Semiconductor Customer Service Representative for assistance.
ON Semiconductor BBCLK ------------------------------------------------------------------------- - 1MHz BBCLK_DIV BBIF_CTRL_CLK_SEL The reset and the low power timing generator clock (32 kHz), or a divided clock for lower power consumption, are divided from the standby clock (Section 6.3.2, “Standby Clock (STANDBYCLK)” on page 80) with the baseband timer...
RSL10 Hardware Reference 9.3.3 Timing and Event-Related Interrupts The real time scheduling and the system wakeup are synchronized over several interrupts. These interrupts are generated by the hardware (BaseBand / Core). Refer to Figure 22 on page 210. Rx ISR...
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ON Semiconductor SW programs ET entry HW fetches entry 2 slots in advance some time before slot Figure 23. Programming Process Overview Start Start Start Prog Latency Prog Latency Prog Latency Master Interval Slave Prog Latency Prog Latency Prog Latency...
RSL10 Hardware Reference 9.3.3.2 End of Event Interrupt The end of event interrupt allows the firmware to check what has been received and sent. This interrupt happens at the end of the event, even if nothing has been received. See Figure 24 on page 211.
ON Semiconductor Prog Latency Channel = 38 Scanner Advertiser Prog Latency Start Figure 26. Rx interrupts, Advertising Packet Received 9.3.3.4 Wakeup Interrupt The wakeup interrupt allows the firmware to turn on the system and start a Bluetooth low energy technology activity.
RSL10 Hardware Reference The event arbiter checks whether the event should be programmed, or if it is in the past and should be pushed into the canceled queue. 9.3.3.5 Software Interrupt This interrupt indicates an event arbiter cancellation.The firmware increments the priority and the programming time before trying to reinsert the event in the event arbiter wait queue.
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ON Semiconductor Register Name Register Description Address Deep sleep wakeup register 0x40001534 BB_DEEPSLWKUP Deep sleep status register 0x40001538 BB_DEEPSLSTAT Stabilization times 0x4000153C BB_ENBPRESET Fine timer correction register 0x40001540 BB_FINECNTCORR Base timer correction register 0x40001544 BB_BASETIMECNTCORR Diagnostic ports control register 0x40001550...
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Register controlling the decision instant for priority scheduling 0x400016B0 BB_BBPRIOSCHARB arbitration In typical use cases, the Bluetooth device address should be set to the value stored to the Device Configuration Record (NVR3) at the location. For more information see the RSL10 Firmware Reference. DEVICE_INFO_BLUETOOTH_ADDR www.onsemi.com...
ON Semiconductor 9.4.1 BBIF_CTRL Bit Field Field Name Description External wakeup request used to sort out sleep modes WAKEUP_REQ Configure the internal baseband controller clock divider in order to provide a CLK_SEL 1MHz reference clock Enable the baseband controller clocks generation...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Reset value 0x0* LINK_FORMAT LINK_FORMAT_RESET Master connect MASTER_CONNECT Slave connect SLAVE_CONNECT Low Duty Cycle Advertiser LOW_DUTY_ADVERTISER High Duty Cycle Advertiser HIGH_DUTY_ADVERTISER Passive Scanner PASSIVE_SCANNER Active Scanner ACTIVE_SCANNER Initiator INITIATOR...
ON Semiconductor 9.4.4 BBIF_COEX_STATUS Bit Field Field Name Description 15:12 Indicates the priority level of the current Bluetooth baseband core activity BLE_PTI Indicates if the Bluetooth baseband core has an event in process, active high. BLE_IN_PROCESS Indicates if the Bluetooth baseband core is busy and performs Tx activity, active BLE_TX high.
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Interrupt not triggered 0x0* BLE_TX_EVENT BLE_TX_EVENT_NONE Interrupt triggered on rising edge BLE_TX_EVENT_RISING_EDGE Interrupt triggered on falling edge BLE_TX_EVENT_FALLING_EDGE Interrupt triggered on any edge BLE_TX_EVENT_TRANSITION Interrupt not triggered 0x0* BLE_RX_EVENT...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value No audio link is currently processed by 0x0* RF_ACTIVE IDLE the RF front-end The audio link is currently processed ACTIVE by the RF front-end Use the Bluetooth low energy 0x0*...
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RSL10 Hardware Reference Bit Field Field Name Description Default Rx Window size in us (used when device is master connected or RXWINSZDEF performs its second receipt) Indicates the maximum number of errors allowed to recognize the SYNCERR synchronization word Field Name...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Bluetooth baseband core reports all 0x0* ADVERTFILT_EN ADVERTFILT_EN_0 errors to Bluetooth baseband software Bluetooth baseband core reports only ADVERTFILT_EN_1 correctly received packet, without error to Bluetooth baseband software Disable Bluetooth baseband core...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Bluetooth baseband core is used as a 0x0* DMMODE DMMODE_0 standalone BLE device Bluetooth baseband core is used in a DMMODE_1 dual mode device No ISO/Audio Channel available ISOPORTNB...
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ON Semiconductor Bit Field Field Name Description SW triggered interrupt mask SWINTMSK End of event / anticipated pre-fetch abort interrupt mask EVENTAPFAINTMSK Fine target timer mask FINETGTIMINTMSK Gross target timer mask GROSSTGTIMINTMSK Error interrupt mask ERRORINTMSK Encryption engine interrupt mask...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Interrupt not generated RXINTMSK RXINTMSK_0 Interrupt generated 0x1* RXINTMSK_1 Interrupt not generated CSCNTINTMSK CSCNTINTMSK_0 Interrupt generated 0x1* CSCNTINTMSK_1 9.4.12 BB_INTSTAT Bit Field Field Name Description Audio channel 2 interrupt status...
ON Semiconductor Field Name Value Symbol Value Description Hex Value No error interrupt 0x0* ERRORINTSTAT ERRORINTSTAT_0 An error interrupt is pending ERRORINTSTAT_1 No encryption / decryption interrupt 0x0* CRYPTINTSTAT CRYPTINTSTAT_0 An encryption / decryption interrupt is CRYPTINTSTAT_1 pending No end of advertising / scanning /...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value No Audio interrupt 0x0* AUDIOINT0RAWSTAT AUDIOINT0RAWSTAT_0 An Audio interrupt is pending. AUDIOINT0RAWSTAT_1 No SW triggered interrupt 0x0* SWINTRAWSTAT SWINTRAWSTAT_0 A SW triggered interrupt is pending SWINTRAWSTAT_1 No end of event interrupt...
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ON Semiconductor Bit Field Field Name Description End of deep sleep interrupt acknowledgment bit SLPINTACK Packet reception interrupt acknowledgment bit RXINTACK 625us base time reference interrupt acknowledgment bit CSCNTINTACK Field Name Value Symbol Value Description Hex Value 0x0* AUDIOINT2ACK AUDIOINT2ACK_0...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value 0x0* EVENTINTACK EVENTINTACK_0 Acknowledges the end of advertising / EVENTINTACK_1 scanning / connection interrupt. This bit resets SLPINTSTAT and SLPINTRAWSTAT flags 0x0* SLPINTACK SLPINTACK_0 Acknowledges the end of Sleep Mode SLPINTACK_1 interrupt.
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* BDADDRL BDADDRL_0 9.4.18 BB_BDADDRU Bit Field Field Name Description Bluetooth low energy device address privacy indicator PRIV_NPUB 15:0 Bluetooth low energy device address (MSB part) BDADDRU Field Name Value Symbol...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Bluetooth baseband core can be 0x0* EXTWKUPDSB EXTWKUPDSB_0 woken by external wakeup Bluetooth baseband core cannot be EXTWKUPDSB_1 woken up by external wakeup Bluetooth baseband core is not yet in...
ON Semiconductor 9.4.23 BB_ENBPRESET Bit Field Field Name Description 20:10 Time in low power oscillator cycles allowed for stabilization of the high frequency TWOSC oscillator when the deep-Sleep Mode has been left due to sleep-timer expiry (DEEPSLWKUP-DEEPSLTIME]) Field Name Value Symbol...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Disable diagnostic port 3 output. All 0x0* DIAG3_EN DIAG3_EN_0 outputs are set to 0x0. Enable diagnostic port 3 output DIAG3_EN_1 Selection of the outputs that must be 0x0* DIAG3...
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* REG_ADDMAX REG_ADDMAX_0 0x0* EM_ADDMAX EM_ADDMAX_0 9.4.29 BB_DEBUGADDMIN Bit Field Field Name Description 31:16 Lower limit for the register zone indicated by the reg_inzone flag REG_ADDMIN 15:0 Lower limit for the exchange memory zone indicated by the em_inzone flag...
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RSL10 Hardware Reference Bit Field Field Name Description Indicates anticipated pre-fetch mechanism error: happens when 2 consecutive EVT_SCHDL_APFM_ERROR events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached Indicates event scheduler faced invalid timing programing on two consecutive EVT_SCHDL_ENTRY_ERROR ET entries (e.g first one with 624us offset and second one with no offset)
ON Semiconductor Field Name Value Symbol Value Description Hex Value No error 0x0* WHITELIST_ERROR WHITELIST_ERROR_0 Error occurred WHITELIST_ERROR_1 No error 0x0* EVT_CNTL_APFM_ERROR EVT_CNTL_APFM_ERROR_0 Error occurred EVT_CNTL_APFM_ERROR_1 No error 0x0* EVT_SCHDL_APFM_ERROR EVT_SCHDL_APFM_ERROR_0 Error occurred EVT_SCHDL_APFM_ERROR_1 No error 0x0* EVT_SCHDL_ENTRY_ERROR EVT_SCHDL_ENTRY_ERROR_0 Error occurred...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value SPI pointer 0x0* SPIPTR SPIPTR_0 SPI clock is master1_gclk / 3 0x0* SPIFREQ SPIFREQ_0 SPIFREQ_1 SPIFREQ_2 SPIFREQ_3 Indicates SPI transfer in progress SPICOMP SPICOMP_0 Indicates SPI transfer is completed.
ON Semiconductor Field Name Value Symbol Value Description Hex Value No radio selected 0x0* XRFSEL XRFSEL_0 Integrated radio (Bluetooth low energy XRFSEL_3 technology) SUBVERSION Current RFFE revision SUBVERSION_3 9.4.34 BB_RADIOCNTL2 Bit Field Field Name Description 15:0 Frequency table pointer FREQTABLE_PTR...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value 0x0* RXPWRUP1 RXPWRUP1_0 0x0* TXPWRDN1 TXPWRDN1_0 0x0* TXPWRUP1 TXPWRUP1_0 9.4.37 BB_RADIOTXRXTIM0 Bit Field Field Name Description 31:24 TXPATHDLY0 20:16 RXPATHDLY0 14:8 RFRXTMDA0 SYNC_POSITION0 Field Name Value Symbol Value Description...
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* TXOFFPTR TXOFFPTR_0 0x0* TXONPTR TXONPTR_0 9.4.40 BB_SPIPTRCNTL1 Bit Field Field Name Description 31:16 Pointer to the RxOFF sequence address section RXOFFPTR 15:0 Pointer to the RxON sequence address section...
RSL10 Hardware Reference 9.4.44 BB_ACTSCANSTAT Bit Field Field Name Description 24:16 Active scan mode back-off counter initialization value BACKOFF Active scan mode upper limit counter value UPPERLIMIT Field Name Value Symbol Value Description Hex Value 0x1* BACKOFF BACKOFF_1 0x1* UPPERLIMIT UPPERLIMIT_1 9.4.45 BB_WLPUBADDPTR...
ON Semiconductor 9.4.48 BB_AESCNTL Bit Field Field Name Description Cipher mode control AES_MODE Starts AES-128 ciphering/deciphering process AES_START Field Name Value Symbol Value Description Hex Value Cipher mode 0x0* AES_MODE AES_MODE_0 Decipher mode AES_MODE_1 0x0* AES_START AES_START_0 Starts AES-128 ciphering/deciphering...
RSL10 Hardware Reference 9.4.52 BB_AESKEY127_96 Bit Field Field Name Description 31:0 AES encryption 128-bit key (bits 127 down to 96) AESKEY127_96 Field Name Value Symbol Value Description Hex Value 0x0* AESKEY127_96 AESKEY127_96_0 9.4.53 BB_AESPTR Bit Field Field Name Description 15:0...
ON Semiconductor Bit Field Field Name Description Applicable only in Tx/Rx RF Test Mode TXLENGTHSRC Applicable only in Tx/Rx RF Test Mode PRBSTYPE Applicable only in Tx/Rx RF Test Mode TXPLDSRC Applicable in RF Test Mode only TXPKTCNTEN Tx packet length in number of bytes...
RSL10 Hardware Reference 9.4.58 BB_RFTESTRXSTAT Bit Field Field Name Description 31:0 Reports number of correctly received packets during test modes RXPKTCNT Field Name Value Symbol Value Description Hex Value 0x0* RXPKTCNT RXPKTCNTX_0 9.4.59 BB_TIMGENCNTL Bit Field Field Name Description Controls the anticipated pre-fetch abort mechanism...
ON Semiconductor 9.4.62 BB_COEXIFCNTL0 Bit Field Field Name Description 25:24 Determines how mws_scan_frequency impacts Bluetooth low energy MWSSCANFREQMSK technology Tx and Rx 21:20 Defines Bluetooth low energy technology packet ble_rx mode behavior WLCRXPRIOMODE 17:16 Defines Bluetooth low energy technology packet ble_tx mode behavior...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Tx indication excluding Tx power up 0x0* WLCTXPRIOMODE WLCTXPRIOMODE_0 delay Tx indication including Tx power up WLCTXPRIOMODE_1 delay Tx High priority indicator WLCTXPRIOMODE_2 WLCTXPRIOMODE_3 mws Tx Frequency has no impact...
ON Semiconductor Field Name Value Symbol Value Description Hex Value tx has no impact 0x0* TXMSK TXMSK_0 tx can stop Bluetooth low energy TXMSK_1 technology Tx, no impact on Bluetooth low energy technology Rx tx can stop Bluetooth low energy...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value If ble_pti[3:0] output value is greater 0x0* WLCPRXTHR WLCPRXTHR_0 than WLCPRXTHR, then Rx Bluetooth low energy technology priority is considered as high, and must be provided to the RF coexistence...
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x3* BLEM7 BLEM7_3 0x4* BLEM6 BLEM6_4 0x8* BLEM5 BLEM5_8 0x9* BLEM4 BLEM4_9 0xA* BLEM3 BLEM3_10 0xD* BLEM2 BLEM2_13 0xE* BLEM1 BLEM1_14 0xF* BLEM0 BLEM0_15 9.4.66 BB_BBMPRIO1 Bit Field Field Name...
RSL10 Hardware Reference 9.4.69 BB_RAL_LOCAL_RND Bit Field Field Name Description Writing a 1 initializes of local RPA random number generation LFSR LRND_INIT 21:0 Initialization value for local RPA random generation when LRDN_INIT is set to 1, LRND_VAL else reports the current Local RPA random number LFSR value...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Audio Mode 0 0x0* ISOTYPE0 ISOTYPE0_0 Reserved ISOTYPE0_1 Reserved ISOTYPE0_2 Reserved ISOTYPE0_3 9.4.72 BB_ISOMUTECNTL0 Bit Field Field Name Description Indicates which buffer is in use (direct copy of ET-ISOBUFSEL) TOGO0...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Tx ISO Buffer pointer 0 of ISO Channel 0x0* ISO0TXPTR0 ISO0TXPTR0_0 Tx ISO Buffer pointer 1 of ISO Channel 0x0* ISO0TXPTR1 ISO0TXPTR1_0 9.4.74 BB_ISOCURRENTRXPTR0 Bit Field Field Name Description...
ON Semiconductor Field Name Value Symbol Value Description Hex Value 0x0* EVT_CNT_OFFSETU0 EVT_CNT_OFFSETU0_0 9.4.78 BB_ISOCHANCNTL1 Bit Field Field Name Description Generate Tx ACK RETXACKEN1 Enable audio syn_p generation SYNCGEN1 Enable ISO channel ISOCHANEN1 ISO Channel Type ISOTYPE1 Field Name Value Symbol...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Do not mute on bad reception of an 0x0* MUTE_SINK1 MUTE_SINK1_0 ISO packet Mute after data or bad reception, with MUTE_SINK1_1 the pattern stored in MUTE_PATTERN0 Provides Source buffer to the Packet...
ON Semiconductor 9.4.82 BB_ISOTRCNL1 Bit Field Field Name Description 23:16 Negotiated, maximum expected number of bytes for ISO Channel 0 Rx payloads ISO1RXLEN Negotiated, number of bytes for ISO Channel 0 Tx payloads ISO1TXLEN Field Name Value Symbol Value Description...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Disable ISO Channel (LLID=0 invalid) 0x0* ISOCHANEN2 ISOCHANEN2_0 Enable ISO Channel (LLID=0 valid) ISOCHANEN2_1 Audio Mode 0 0x0* ISOTYPE2 ISOTYPE2_0 Reserved ISOTYPE2_1 Reserved ISOTYPE2_2 Reserved ISOTYPE2_3 9.4.86 BB_ISOMUTECNTL2 Bit Field...
ON Semiconductor 9.4.87 BB_ISOCURRENTTXPTR2 Bit Field Field Name Description 31:16 Tx ISO Buffer pointer 0 of ISO Channel 2 ISO2TXPTR0 15:0 Tx ISO Buffer pointer 1 of ISO Channel 2 ISO2TXPTR1 Field Name Value Symbol Value Description Hex Value Tx ISO Buffer pointer 0 of ISO Channel...
RSL10 Hardware Reference 9.4.91 BB_ISOEVTCNTLOFFSETU2 Bit Field Field Name Description MSB part of EVT_CNT_OFFSET2[39:0] field EVT_CNT_OFFSETU2 Field Name Value Symbol Value Description Hex Value 0x0* EVT_CNT_OFFSETU2 EVT_CNT_OFFSETU2_0 9.4.92 BB_BBPRIOSCHARB Bit Field Field Name Description Determine Bluetooth low energy technology priority scheduling arbitration mode...
CHAPTER 10 Digital Input/Output 10.1 O VERVIEW The RSL10 system contains 16 digital input/output (DIO) pads that can be configured: • To support the external interfaces, output clocks, and other I/Os • As general-purpose I/Os controllable from the core DIOs support all digital inputs and output functions that are not supported directly by a dedicated I/O. For more information about the functional configuration of DIO pads, see Section 10.2, “Functional Configuration”...
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RSL10 Hardware Reference In addition to standard digital functional configuration, certain DIOs can be configured for special modes. These special modes are described in Section 10.2.1, “Special Functional Configurations” on page 264. CAUTION: While a DIO can be configured to be both an output and an input, it is the user application's responsibility to ensure that the DIO is not driving an output to a pad that is also being driven externally.
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ON Semiconductor Table 18. DIO Multiplexed Functionality (Continued) Mode Setting Description 0x1F Baseband SPI chip select output DIO_MODE_BB_SPI_CSN 0x20 Baseband SPI clock output DIO_MODE_BB_SPI_CLK 0x21 Baseband SPI serial output signal (MOSI) DIO_MODE_BB_SPI_MOSI 0x22 Baseband debug signal 0 DIO_MODE_BB_DBG0_0 0x23 Baseband debug signal 1...
LPDSP32 JTAG Test Mode select input selection LPDSP32_JTAG_TMS LPDSP32 JTAG test clock selection LPDSP32_JTAG_TCK 10.2.1 Special Functional Configurations RSL10 contains two special functional configurations that affect a subset of the DIOs. These special functional configurations are described in Table 20. www.onsemi.com...
DIO_JTAG_SW_PAD_CFG 10.3 P HYSICAL ONFIGURATION The RSL10 system includes physical configuration parameters for each DIO. These parameters are set using configuration bits from the appropriate register. DIO_CFG_* If the DIO is configured as an input pad, it has the following configuration options: •...
RSL10 Hardware Reference • bit allows you to select the drive strength for the DIO output. DIO_CFG_DRIVE NOTE: The bit-field from the register can be used to increase the DIO_PAD_CFG_DRIVE DIO_PAD_CFG drive strength of all outputs by 50% or more if needed for a user application.
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ON Semiconductor Field Name Value Symbol Value Description Hex Value 2x drive strength DRIVE DIO_2X_DRIVE 3x drive strength DIO_3X_DRIVE 5x drive strength DIO_5X_DRIVE 6x drive strength 0x3* DIO_6X_DRIVE Disable low pass filter 0x0* DIO_LPF_DISABLE Enable low pass filter DIO_LPF_ENABLE No pull selected...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Output STANDBYCLK signal 0x1B (continued) IO_MODE DIO_MODE_STANDBYCLK Output baseband controller Tx data 0x1C DIO_MODE_BB_TX_DATA signal Output baseband controller Tx data 0x1D DIO_MODE_BB_TX_DATA_VALID valid signal Output baseband controller 0x1E DIO_MODE_BB_SYNC_P...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Output RF front-end GPIO8 output 0x33 (continued) IO_MODE DIO_MODE_RF_GPIO8 signal Output RF front-end GPIO9 output 0x34 DIO_MODE_RF_GPIO9 signal Output the DMIC clock signal 0x35 DIO_MODE_DMIC_CLK Output audio synchronization pulse 0x36...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value DIO pad is low 0x0* DIO0_LOW DIO pad is low 0x0* DIO1_LOW DIO pad is low 0x0* DIO2_LOW DIO pad is low 0x0* DIO3_LOW DIO pad is low 0x0*...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Set the DIO pad to low if IO_MODE is (continued) GPIO GPIO4_LOW 0b0000XX Set the DIO pad to low if IO_MODE is GPIO5_LOW 0b0000XX Set the DIO pad to low if IO_MODE is...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Set the DIO pad to high if IO_MODE is 0x1000 (continued) GPIO GPIO12_HIGH 0b0000XX Set the DIO pad to high if IO_MODE is 0x2000 GPIO13_HIGH 0b0000XX Set the DIO pad to high if IO_MODE is...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value DIO is an input 0x0* DIO0_INPUT DIO is an input 0x0* DIO1_INPUT DIO is an input 0x0* DIO2_INPUT DIO is an input 0x0* DIO3_INPUT DIO is an input 0x0* DIO4_INPUT...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Set DIO to input if IO_MODE is (continued) GPIO GPIO4_INPUT 0b0000XX Set DIO to input if IO_MODE is GPIO5_INPUT 0b0000XX Set DIO to input if IO_MODE is GPIO6_INPUT 0b0000XX...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Set DIO to output if IO_MODE is 0x1000 (continued) GPIO GPIO12_OUTPUT 0b0000XX Set DIO to output if IO_MODE is 0x2000 GPIO13_OUTPUT 0b0000XX Set DIO to output if IO_MODE is 0x4000...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value This DIO is not configured as a ARM 0x0* (continued) GPIO DIO15_IS_NOT_GPIO Cortex-M3 core controlled GPIO This DIO is configured as a ARM DIO0_IS_GPIO Cortex-M3 core controlled GPIO This DIO is configured as a ARM...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Interrupt not triggered 0x0* EVENT DIO_EVENT_NONE Interrupt triggered on high state DIO_EVENT_HIGH_LEVEL Interrupt triggered on low state DIO_EVENT_LOW_LEVEL Interrupt triggered on rising edge DIO_EVENT_RISING_EDGE Interrupt triggered on falling edge DIO_EVENT_FALLING_EDGE...
RSL10 Hardware Reference 10.4.7 DIO_PCM_SRC Bit Field Field Name Description 20:16 PCM_SERI input selection SERI 12:8 PCM_FRAME input selection FRAME PCM_CLK input selection Field Name Value Symbol Value Description Hex Value Select DIO[0] as source SERI PCM_SERI_SRC_DIO_0 Select DIO[1] as source...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source FRAME PCM_FRAME_SRC_DIO_0 Select DIO[1] as source PCM_FRAME_SRC_DIO_1 Select DIO[2] as source PCM_FRAME_SRC_DIO_2 Select DIO[3] as source PCM_FRAME_SRC_DIO_3 Select DIO[4] as source PCM_FRAME_SRC_DIO_4 Select DIO[5] as source...
RSL10 Hardware Reference 10.4.8 DIO_SPI_SRC Bit Field Field Name Description 20:16 SPI_SERI input selection SERI 12:8 SPI_CS input selection SPI_CLK input selection Field Name Value Symbol Value Description Hex Value Select DIO[0] as source SERI SPI_SERI_SRC_DIO_0 Select DIO[1] as source...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source SPI_CS_SRC_DIO_0 Select DIO[1] as source SPI_CS_SRC_DIO_1 Select DIO[2] as source SPI_CS_SRC_DIO_2 Select DIO[3] as source SPI_CS_SRC_DIO_3 Select DIO[4] as source SPI_CS_SRC_DIO_4 Select DIO[5] as source SPI_CS_SRC_DIO_5...
RSL10 Hardware Reference 10.4.9 DIO_UART_SRC Bit Field Field Name Description UART_RX input selection Field Name Value Symbol Value Description Hex Value Select DIO[0] as source UART_RX_SRC_DIO_0 Select DIO[1] as source UART_RX_SRC_DIO_1 Select DIO[2] as source UART_RX_SRC_DIO_2 Select DIO[3] as source...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source SDA_SRC_DIO_0 Select DIO[1] as source SDA_SRC_DIO_1 Select DIO[2] as source SDA_SRC_DIO_2 Select DIO[3] as source SDA_SRC_DIO_3 Select DIO[4] as source SDA_SRC_DIO_4 Select DIO[5] as source SDA_SRC_DIO_5...
RSL10 Hardware Reference 10.4.11 DIO_AUDIOSINK_SRC Bit Field Field Name Description Audio sink clock input selection Field Name Value Symbol Value Description Hex Value Select DIO[0] as source AUDIOSINK_CLK_SRC_DIO_0 Select DIO[1] as source AUDIOSINK_CLK_SRC_DIO_1 Select DIO[2] as source AUDIOSINK_CLK_SRC_DIO_2 Select DIO[3] as source...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source NMI_SRC_DIO_0 Select DIO[1] as source NMI_SRC_DIO_1 Select DIO[2] as source NMI_SRC_DIO_2 Select DIO[3] as source NMI_SRC_DIO_3 Select DIO[4] as source NMI_SRC_DIO_4 Select DIO[5] as source NMI_SRC_DIO_5...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Select DIO[0] as source RF_SYNC_P BB_RF_SYNC_P_SRC_DIO_0 Select DIO[1] as source BB_RF_SYNC_P_SRC_DIO_1 Select DIO[5] as source BB_RF_SYNC_P_SRC_DIO_2 Select DIO[3] as source BB_RF_SYNC_P_SRC_DIO_3 Select DIO[4] as source BB_RF_SYNC_P_SRC_DIO_4 Select DIO[5] as source...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source BB_RX_CLK_SRC_DIO_0 Select DIO[1] as source BB_RX_CLK_SRC_DIO_1 Select DIO[2] as source BB_RX_CLK_SRC_DIO_2 Select DIO[3] as source BB_RX_CLK_SRC_DIO_3 Select DIO[4] as source BB_RX_CLK_SRC_DIO_4 Select DIO[5] as source BB_RX_CLK_SRC_DIO_5...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Select DIO[0] as source DATA BB_RX_DATA_SRC_DIO_0 Select DIO[1] as source BB_RX_DATA_SRC_DIO_1 Select DIO[2] as source BB_RX_DATA_SRC_DIO_2 Select DIO[3] as source BB_RX_DATA_SRC_DIO_3 Select DIO[4] as source BB_RX_DATA_SRC_DIO_4 Select DIO[5] as source...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source MISO BB_SPI_MISO_SRC_DIO_0 Select DIO[1] as source BB_SPI_MISO_SRC_DIO_1 Select DIO[2] as source BB_SPI_MISO_SRC_DIO_2 Select DIO[3] as source BB_SPI_MISO_SRC_DIO_3 Select DIO[4] as source BB_SPI_MISO_SRC_DIO_4 Select DIO[5] as source...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Select DIO[0] as source MOSI RF_SPI_MOSI_SRC_DIO_0 Select DIO[1] as source RF_SPI_MOSI_SRC_DIO_1 Select DIO[2] as source RF_SPI_MOSI_SRC_DIO_2 Select DIO[3] as source RF_SPI_MOSI_SRC_DIO_3 Select DIO[4] as source RF_SPI_MOSI_SRC_DIO_4 Select DIO[5] as source...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source RF_SPI_CSN_SRC_DIO_0 Select DIO[1] as source RF_SPI_CSN_SRC_DIO_1 Select DIO[2] as source RF_SPI_CSN_SRC_DIO_2 Select DIO[3] as source RF_SPI_CSN_SRC_DIO_3 Select DIO[4] as source RF_SPI_CSN_SRC_DIO_4 Select DIO[5] as source RF_SPI_CSN_SRC_DIO_5...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Select DIO[0] as source RF_SPI_CLK_SRC_DIO_0 Select DIO[1] as source RF_SPI_CLK_SRC_DIO_1 Select DIO[2] as source RF_SPI_CLK_SRC_DIO_2 Select DIO[3] as source RF_SPI_CLK_SRC_DIO_3 Select DIO[4] as source RF_SPI_CLK_SRC_DIO_4 Select DIO[5] as source...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source GPIO3 RF_GPIO3_SRC_DIO_0 Select DIO[1] as source RF_GPIO3_SRC_DIO_1 Select DIO[3] as source RF_GPIO3_SRC_DIO_2 Select DIO[3] as source RF_GPIO3_SRC_DIO_3 Select DIO[4] as source RF_GPIO3_SRC_DIO_4 Select DIO[5] as source...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Select DIO[0] as source GPIO2 RF_GPIO2_SRC_DIO_0 Select DIO[1] as source RF_GPIO2_SRC_DIO_1 Select DIO[2] as source RF_GPIO2_SRC_DIO_2 Select DIO[3] as source RF_GPIO2_SRC_DIO_3 Select DIO[4] as source RF_GPIO2_SRC_DIO_4 Select DIO[5] as source...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source GPIO0 RF_GPIO0_SRC_DIO_0 Select DIO[1] as source RF_GPIO0_SRC_DIO_1 Select DIO[0] as source RF_GPIO0_SRC_DIO_2 Select DIO[3] as source RF_GPIO0_SRC_DIO_3 Select DIO[4] as source RF_GPIO0_SRC_DIO_4 Select DIO[5] as source...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Select DIO[0] as source GPIO7 RF_GPIO7_SRC_DIO_0 Select DIO[1] as source RF_GPIO7_SRC_DIO_1 Select DIO[5] as source RF_GPIO7_SRC_DIO_2 Select DIO[3] as source RF_GPIO7_SRC_DIO_3 Select DIO[4] as source RF_GPIO7_SRC_DIO_4 Select DIO[5] as source...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source GPIO5 RF_GPIO5_SRC_DIO_0 Select DIO[1] as source RF_GPIO5_SRC_DIO_1 Select DIO[5] as source RF_GPIO5_SRC_DIO_2 Select DIO[3] as source RF_GPIO5_SRC_DIO_3 Select DIO[4] as source RF_GPIO5_SRC_DIO_4 Select DIO[5] as source...
RSL10 Hardware Reference 10.4.18 DIO_RF_GPIO89_SRC Bit Field Field Name Description 12:8 RF front-end GPIO9 input selection GPIO9 RF front-end GPIO8 input selection GPIO8 Field Name Value Symbol Value Description Hex Value Select DIO[0] as source GPIO9 RF_GPIO9_SRC_DIO_0 Select DIO[1] as source...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Select DIO[0] as source GPIO8 RF_GPIO8_SRC_DIO_0 Select DIO[1] as source RF_GPIO8_SRC_DIO_1 Select DIO[5] as source RF_GPIO8_SRC_DIO_2 Select DIO[3] as source RF_GPIO8_SRC_DIO_3 Select DIO[4] as source RF_GPIO8_SRC_DIO_4 Select DIO[5] as source...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Select DIO[0] as source DMIC_CLK_SRC_DIO_0 Select DIO[1] as source DMIC_CLK_SRC_DIO_1 Select DIO[2] as source DMIC_CLK_SRC_DIO_2 Select DIO[3] as source DMIC_CLK_SRC_DIO_3 Select DIO[4] as source DMIC_CLK_SRC_DIO_4 Select DIO[5] as source...
ON Semiconductor 10.4.20 DIO_LPDSP32_JTAG_SRC Bit Field Field Name Description 20:16 LPDSP32_TDI input selection 12:8 LPDSP32_TMS input selection LPDSP32_TCK input selection Field Name Value Symbol Value Description Hex Value Select DIO[0] as source LPDSP32_TDI_SRC_DIO_0 Select DIO[1] as source LPDSP32_TDI_SRC_DIO_1 Select DIO[2] as source...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Select DIO[0] as source LPDSP32_TMS_SRC_DIO_0 Select DIO[1] as source LPDSP32_TMS_SRC_DIO_1 Select DIO[2] as source LPDSP32_TMS_SRC_DIO_2 Select DIO[3] as source LPDSP32_TMS_SRC_DIO_3 Select DIO[4] as source LPDSP32_TMS_SRC_DIO_4 Select DIO[5] as source...
IMPORTANT: For accurate ADC measurements across operating conditions, the VDDC supply voltage level must be a minimum of 1.00 V. For more information about VDDC configuration, see Section 5.3.4, “Digital Supply Voltages” on page 46, and the “Manufacturing Calibrated Settings” from the RSL10 Firmware Reference. 11.1.1 ADC Input Configuration The purpose of the ADCs is to sample analog signals that are relevant to the user’s application use cases—for...
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RSL10 Hardware Reference Low-Frequency Mode SLOWCLK is first prescaled by a fixed factor of 10, with a maximum sampling rate of 5 kHz. ADC measurement results have a resolution of 14 bits. High-Frequency Mode SLOWCLK is prescaled by a factor of 2, with sampling rates of up to 25 kHz where ADC measurement results have a resolution of 14 bits, or up to 50 kHz where ADC measurement results have a resolution of 8 bits.
2.0 V. Measurements outside of the range from 0 to 2.0 V can extend this range if the ADC sampling configuration extends the range of measured values. For improved accuracy in the ADC data, the RSL10 SoC provides an offset correction factor in the ADC_OFFSET register that automatically applies a compensation value to the measured ADC data.
RSL10 Hardware Reference 11.1.5 ADC and Power Supply Monitoring Interrupt A single interrupt line is shared between the ADC and the power supply monitoring circuitry. This interrupt can be independently configured to trigger when one or both of the following conditions are met: •...
ON Semiconductor 11.1.6.3 ADC_INPUT_SEL Bit Field Field Name Description Positive input selection POS_INPUT_SEL Negative input selection NEG_INPUT_SEL Field Name Value Symbol Value Description Hex Value Select DIO0 as positive input POS_INPUT_SEL ADC_POS_INPUT_DIO0 Select DIO1 as positive input ADC_POS_INPUT_DIO1 Select DIO2 as positive input...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value ADC disabled 0x0* FREQ ADC_DISABLE Sample rate is SLOWCLK/200 (low ADC_PRESCALE_200 frequency mode) Sample rate is SLOWCLK/400 (low ADC_PRESCALE_400 frequency mode) Sample rate is SLOWCLK/640 (low ADC_PRESCALE_640 frequency mode)
ON Semiconductor Field Name Value Symbol Value Description Hex Value No Alarm is triggered 0x0* ALARM_COUNT_VALUE BATMON_ALARM_NONE Alarm count value is 1 BATMON_ALARM_COUNT1 Alarm count value is 255 0xFF BATMON_ALARM_COUNT255 Lowest voltage threshold: 7.8 mV SUPPLY_THRESHOLD SUPPLY_THRESHOLD_LOW Mid voltage threshold: 1 V...
URPOSE NTERFACE RSL10 can configure any of the DIO pads as software-controlled general-purpose DIO (GPIO) pads. The function of these GPIO pads is defined by a user application, which can use them for any general-purpose input or output. register indicates which DIO pads have been configured for GPIO functionality; bits in this register...
ON Semiconductor The value observed at the digital input pads can be read from the register. This value is read as 0 for all DIO_DATA pads configured as ADC inputs (see Section 11.1, “Analog-to-Digital Converters (ADCs)”), because the digital input is not enabled in this mode.
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RSL10 Hardware Reference The example timing diagram shown in Figure 28 provides some information about the important elements in an I transaction, which are described in further detail in the previously mentioned bus specification. These elements are: Start Condition The SDA transitions from the idle high state to the low state while the SCL remains high. This can also happen during a transmission as a repeated start condition, which indicates that the transaction is starting again without an intermediate stop condition.
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ON Semiconductor Start Address Read/Write Acknowledge Data Acknowledge Data Not Acknowledge Stop Condition (Bits 0-6) (Bit 7) by Slave (Bits 0-7) by Master or (Bits 0-7) by Master Receiver; Condition Slave Acknowledge or Not Acknowledge by Slave Receiver Figure 28. I...
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RSL10 Hardware Reference Table 24. I C Event and State Status Bits Bit Field Field Name Bit Type Field Description Event Indicate if an error (I C bus or I C watchdog) has occurred. I2C_STATUS_ERROR_S is 0 when I2C_STATUS_ERROR_S I2C_ERROR_CNT contains 0 and is not 1.
ON Semiconductor Table 24. I C Event and State Status Bits (Continued) Bit Field Field Name Bit Type Field Description State Indicate the state of the Read/Write direction bit last sent or I2C_STATUS_READ_WRITE received. Transition out of this state occurs after a new Read/ Write direction bit is sent or received.
RSL10 Hardware Reference transaction, the bit in the register can be queried to identify the addresses that I2C_STATUS_GEN_CALL I2C_STATUS were used to address the device. A device receiving data in a slave mode configuration can use the bit from the...
ON Semiconductor 11.3.3 I C Interrupts The I C interface uses an associated interrupt which, when enabled, signals the receipt of a correct address byte and the completion of each data byte in the transaction. When enabled, the I C interrupt signals the stop condition following a transaction for a master transfer. The system...
RSL10 Hardware Reference NOTE: Use of the bits from the I2C_CTRL1_NACK I2C_CTRL1_ACK I2C_CTRL1_STOP_CMD register is only defined when an acknowledgement is needed during a data transfer. I2C_CTRL1 Interface behavior in response to these control bits being set at other times is undefined.
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ON Semiconductor Bit Field Field Name Description Select whether data transfer will be controlled by the ARM Cortex-M3 core or CONTROLLER the DMA for I2C Configure whether stop interrupts will be generated by the I2C interface STOP_INT_ENABLE Select whether acknowledgement is automatically generated or not...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Require manual acknowledgement of 0x0* AUTO_ACK_ENABLE I2C_AUTO_ACK_DISABLE all I2C interface transfers Use automatic acknowledgement for I2C_AUTO_ACK_ENABLE I2C interface transfers Disable the I2C sample clock (I2C is 0x0* I2C_SAMPLE_CLK_ENABLE I2C_SAMPLE_CLK_DISABLE...
ON Semiconductor 11.3.4.5 I2C_ADDR_START Bit Field Field Name Description I2C address to use for the transaction ADDRESS Select whether a read or a write transaction is started READ_WRITE Field Name Value Symbol Value Description Hex Value Start an I2C write transaction...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value No pending master start frame 0x0* START_PENDING I2C_START_NOT_PENDING A master frame is pending to start (bit I2C_START_PENDING is set when I2C_ADDR_START is written) I2C interface is not operating in master...
ODULATION NTERFACE RSL10 has access to a highly configurable pulse code modulation (PCM) interface that can be used to stream control, configuration or signal data into and out of the microcontroller. The PCM interface is multiplexed onto the DIO pads, which can be configured as the input and output signals that form the PCM interface with the necessary physical pad configuration.
RSL10 Hardware Reference Either the ARM Cortex-M3 processor or the DMA can control the data transferred by the PCM interface. Select the controller by configuring the bit in the register. PCM_CTRL_CONTROLLER PCM_CTRL IMPORTANT: The PCM interface configuration and internal status registers are tightly synchronized to the input PCM clock.
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ON Semiconductor be left in the default configuration (configured for two words per frame), regardless of the actual frame length used, to get the expected behavior. Alternately, if the bit is FRAME_SUBFRAMES configured to enable subframes, a frame signal is generated with every word of each data frame.
ON Semiconductor 11.4.1.2 Data Serial Input and Output Configuration The PCM interface allows data bits to be configured for transmission and reception in either an MSB to LSB ordering, or an LSB to MSB ordering. To select between these two configurations, set the...
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RSL10 Hardware Reference Table 25. Required Configuration Settings for I S Configuration Configuration Bit or Bit Field Setting PCM_CTRL_WORD_SIZE PCM_WORD_SIZE_16 PCM_CTRL_FRAME_LENGTH PCM_MULTIWORD_2 PCM_CTRL_FRAME_WIDTH PCM_FRAME_WIDTH_LONG PCM_CTRL_FRAME_ALIGN PCM_FRAME_ALIGN_LAST PCM_CTRL_BIT_ORDER PCM_BIT_ORDER_MSB_FIRST PCM_CTRL_FRAME_SUBFRAMES PCM_SUBFRAME_DISABLE PCM_CTRL_SLAVE PCM_SLAVE PCM_CTRL_PCM_CLK_POL PCM_SAMPLE_RISING_EDGE The PCM interface produces a data stream that complies with the I S standard with either sampling edge.
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ON Semiconductor Figure 31. Signal Timing Diagram: I S Configuration www.onsemi.com...
RSL10 Hardware Reference 11.4.4 PCM Registers Register Name Register Description Address PCM Control 0x40000A00 PCM_CTRL PCM Transmit Data 0x40000A04 PCM_TX_DATA PCM Receive Data 0x40000A08 PCM_RX_DATA PCM Status 0x40000A0C PCM_STATUS 11.4.4.1 PCM_CTRL Bit Field Field Name Description PCM clock polarity PCM_CLK_POL...
ON Semiconductor Field Name Value Symbol Value Description Hex Value The PCM frame is high for one PCM 0x0* FRAME_WIDTH PCM_FRAME_WIDTH_SHORT clock period The PCM frame is high for half of the PCM_FRAME_WIDTH_LONG frame length PCM frames contain 2 words...
IDTH ODULATION The RSL10 system contains two pulse-width modulator (PWM) drivers that can be configured to generate a single output signal with a specified period and duty cycle. Each PWM driver can be used as independently as a simple D/A converter, or as a driver for an external audio sink.
ON Semiconductor PWM*CLK cycles of each period, to a maximum equal to the period of that PWM signal. After (PWM_CFG_PWM_HIGH + 1) PWM*CLK cycles, the PWM signal is low for the remainder of the period. NOTE: If the specified high time is greater than or equal to the specified period for a PWM, the PWM signal does not go low.
ERIPHERAL NTERFACES The RSL10 system includes two Serial Peripheral Interfaces (SPI) that allow the system to communicate with external components including external analog front ends, external controllers, and non-volatile memories (NVM). The SPI interfaces are multiplexed onto the DIO pads, which can be configured as the input and output signals that form each SPI interface with the necessary physical pad configuration.
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ON Semiconductor SYSCLK SPI*_CLK NOTE: If , the output on the SPI*_SERO pad might be SYSCLK SPI*_CLK delayed by up to one SYSCLK period. For both master and slave mode, the bit in the SPI*_CTRL0_CLK_POLARITY SPI*_CTRL0 register is used to control both when data changes and when data is sampled.
RSL10 Hardware Reference If the bit in the register is set, the SPI interface operates in auto mode SPI*_CTRL0_MODE_SELECT SPI*_CTRL0 to limit the overhead between SPI transfers. This mode works in conjunction with the SPI interface data registers. These registers are: Shift register containing the data to transmit using the SPI interface.
ON Semiconductor 11.6.3 SPI DMA Control If using the DMA to control data transfers over an SPI interface, transmit events are triggered on the completion of a data transmission and receive events are triggered on the completion of a received data word. There are two methods to ensure that the first DMA word is transferred: •...
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RSL10 Hardware Reference Bit Field Field Name Description Select the polarity of the SPI clock SPI0_CLK_POLARITY Select between manual and auto transaction handling modes for SPI master SPI0_MODE_SELECT transactions Enable/disable the SPI interface SPI0_ENABLE Prescale the SPI interface clock for master transfers...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Prescale the SPI interface clock by 2 0x0* SPI0_PRESCALE SPI0_PRESCALE_2 Prescale the SPI interface clock by 4 SPI0_PRESCALE_4 Prescale the SPI interface clock by 8 SPI0_PRESCALE_8 Prescale the SPI interface clock by 16...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value SPI transfers use 1-bit words 0x0* SPI0_WORD_SIZE SPI0_WORD_SIZE_1 SPI transfers use 8-bit words SPI0_WORD_SIZE_8 SPI transfers use 16-bit words SPI0_WORD_SIZE_16 SPI transfers use 24-bit words 0x17 SPI0_WORD_SIZE_24 SPI transfers use 32-bit words...
ON Semiconductor 11.6.4.6 SPI1_CTRL0 Bit Field Field Name Description Enable/disable SPI overrun interrupts SPI1_OVERRUN_INT_ENABLE Enable/disable SPI underrun interrupts SPI1_UNDERRUN_INT_ENABLE Select whether data transfer will be controlled by the ARM Cortex-M3 core or SPI1_CONTROLLER the DMA for SPI Use the SPI interface as master or slave...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Prescale the SPI interface clock by 2 0x0* SPI1_PRESCALE SPI1_PRESCALE_2 Prescale the SPI interface clock by 4 SPI1_PRESCALE_4 Prescale the SPI interface clock by 8 SPI1_PRESCALE_8 Prescale the SPI interface clock by 16...
ON Semiconductor 11.6.4.8 SPI1_TX_DATA Bit Field Field Name Description 31:0 Single word buffer for data to be transmitted over the SPI interface SPI1_TX_DATA 11.6.4.9 SPI1_RX_DATA Bit Field Field Name Description 31:0 Single word buffer for data that has been received over the SPI interface SPI1_RX_DATA 11.6.4.10 SPI1_STATUS...
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RSL10 Hardware Reference The UART interface can be enabled or disabled using the bit in the appropriate UART_CFG_ENABLE UART_CTRL register. When disabled the UART interface will immediately terminate any ongoing transfer, and setting the UART transmit line high and ignoring any partially received receive data.
ON Semiconductor 11.7.1 UART Interrupts The UART interface uses three associated interrupts that separately control transmission and reception of UART data and handling of UART transmission errors. Section 14.1, “Nested Vectored Interrupt Controller (NVIC)” on page 401 for information regarding interrupt configuration and handling.
For more information on DIO configuration, see Chapter 10, “Digital Input/Output” on page 261. Figure 34 on page 349 shows how these interfaces (and their DIO connections) are connected internally on the RSL10 SoC, and Table 26 provides a description of these connections.
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ON Semiconductor Figure 34. Interface between the Baseband Controller and the RF Front-End www.onsemi.com...
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RSL10 Hardware Reference Table 26. Interface signals between the baseband controller and the RF front-end Baseband Signal RF Front-end Signal Source Description BB_SPI_MISO RF_SPI_MISO RF Front-end SPI data slave to master BB_SPI_MOSI RF_SPI_MOSI Baseband SPI data master to slave BB_SPI_CLK...
CHAPTER 12 Peripherals 12.1 C (CRC) G YCLIC EDUNDANCY HECK ENERATOR The peripherals to the ARM Cortex-M3 processor include a CRC generator that provides support for two standard cyclic redundancy check (CRC) algorithms (CRC-CCITT and CRC-32, defined by the IEEE 802.3 Ethernet standard).
RSL10 Hardware Reference The ARM Cortex-M3 processor’s CRC generator supports non-standard variants of the CRC-CCITT and CRC-32 standard implementation. • To use non-standard CRC ordering of data within each data byte, set the bit from the CRC_CTRL_BIT_ORDER register. CRC_CTRL •...
ON Semiconductor Field Name Value Symbol Value Description Hex Value Final CRC XOR is done according to 0x0* FINAL_CRC_XOR CRC_FINAL_XOR_STANDARD the standard (CRC-CCITT: no XOR; CRC-32: XOR with 0xFFFFFFFF) Final CRC XOR is done in opposite of CRC_FINAL_XOR_NON_STANDARD the standard...
RSL10 Hardware Reference 12.1.1.5 CRC_ADD_16 Bit Field Field Name Description 15:0 Add 1 half-word (16 bits) to the CRC calculation CRC_ADD_16 12.1.1.6 CRC_ADD_24 Bit Field Field Name Description 23:0 Add 3 bytes (24 bits) to the CRC calculation CRC_ADD_24_BITS 12.1.1.7 CRC_ADD_32...
ON Semiconductor 12.2.2 DMA Channel Configuration The DMA has eight independently configurable channels. To enable or disable a DMA channel, configure the bit from the appropriate register. If the DMA channel is in the midst of an operation DMA_CTRL0_ENABLE DMA_CTRL0 when it is disabled, the operation is aborted.
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RSL10 Hardware Reference a peripheral as the destination typically have destination incrementing disabled. Conversely, transfers that use memory as the destination typically have destination incrementing enabled. If the address is incremented, the increment can be configured to be positive or negative, and to...
ON Semiconductor Interrupt Configuration The interrupts used to coordinate with, and control, a DMA transfer can be defined using the bits from the DMA channel’s register. For more DMA_CTRL0_*_INT_ENABLE DMA_CTRL0 information, see Section 12.2.5, “DMA Interrupt Configuration” on page 364.
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RSL10 Hardware Reference For example, when reading 8-bit bytes from the I C interface and storing them to data memory, four 8-bit data words from the I C interface are packed before they are written to memory. In this example, it is most efficient to make the destination word size 32 bits to minimize bus utilization and maximize memory use efficiency.
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ON Semiconductor Word size Source Data Destination Data SRC DEST Big Endian Little Endian H G F E D C B A s H G F E D C B A d H G F E D C B A d...
RSL10 Hardware Reference For memory-to-peripheral transfers, the counter in the DMA channel always operates on the peripheral’s word size. For peripheral-to-memory, peripheral-to-peripheral and memory-to-memory transfers, the counter in the DMA channel always operates on the source’s word size. The next address for reading or writing can be determined from: •...
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ON Semiconductor Table 30. Valid Sources of DMA Data Source Encoded Bits SPI 0 SPI 1 UART ASRC PBUS DMIC Each source interface or peripheral, when configured for DMA operation, asserts its DMA request signal when data can be read from the interface. This signal is cleared automatically when a data value is read from the interface using the peripheral bus.
RSL10 Hardware Reference IMPORTANT: Due to the structure of the SPI interfaces, when a user application initializes a transmit transfer using an SPI interface controlled by a DMA channel, the user application must preload the SPI interface’s transmit data register ( ) with the first data word of the transfer.
ON Semiconductor 10. The DMA releases the peripheral bus. 11. The DMA channel’s counter is incremented. 12. If the transfer length is not reached, the DMA channel waits for the next peripheral DMA request. If the transfer length is reached and the DMA is in linear mode, the DMA channel switches to the complete state. If the DMA is in circular mode, the DMA resets the counter to 0 and remains enabled.
RSL10 Hardware Reference The DMA writes the word at the next destination address. 10. The DMA channel acknowledges the destination peripheral DMA request (implied by the previous write operation). 11. The DMA releases the peripheral bus. 12. The DMA channel’s counter is incremented.
ON Semiconductor When using a circular DMA transfer, the counter interrupt and complete interrupt can be used in tandem to create a two-page buffer for continuous data transfers. When the first page has transferred, the counter interrupt triggers. When the second page has transferred, the complete interrupt triggers. In this configuration:...
RSL10 Hardware Reference When the DMA is granted access to memory, it performs a single operation (read or write) and releases the processor data memory. This ensures that the DMA never blocks access to data memory from the processor for more than a single memory operation.
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ON Semiconductor Register Name Register Description Address DMA Channel Source Base Address 4 0x40000630 DMA_SRC_BASE_ADDR[4] DMA Channel Source Base Address 5 0x40000634 DMA_SRC_BASE_ADDR[5] DMA Channel Source Base Address 6 0x40000638 DMA_SRC_BASE_ADDR[6] DMA Channel Source Base Address 7 0x4000063C DMA_SRC_BASE_ADDR[7] DMA Channel Destination Base Address 0...
RSL10 Hardware Reference Register Name Register Description Address DMA Channel Word Count 3 0x400006CC DMA_WORD_CNT[3] DMA Channel Word Count 4 0x400006D0 DMA_WORD_CNT[4] DMA Channel Word Count 5 0x400006D4 DMA_WORD_CNT[5] DMA Channel Word Count 6 0x400006D8 DMA_WORD_CNT[6] DMA Channel Word Count 7...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Set the step size of DMA channel to 1 0x0* DEST_ADDR_STEP_SIZE DMA_DEST_ADDR_STEP_SIZE_1 Set the step size of DMA channel to 2 DMA_DEST_ADDR_STEP_SIZE_2 Set the step size of DMA channel to 3...
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RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Source data uses 8-bit words 0x0* SRC_WORD_SIZE DMA_SRC_WORD_SIZE_8 Source data uses 16-bit words DMA_SRC_WORD_SIZE_16 Source data uses 32-bit words DMA_SRC_WORD_SIZE_32 Source data uses 4-bit words DMA_SRC_WORD_SIZE_4 Data writes are triggered by the I2C...
ON Semiconductor Field Name Value Symbol Value Description Hex Value DMA channel will provide a 0x0* TRANSFER_TYPE DMA_TRANSFER_M_TO_M memory-to-memory data transfer DMA channel will provide a DMA_TRANSFER_M_TO_P memory-to-peripheral data transfer DMA channel will provide a DMA_TRANSFER_P_TO_M peripheral-to-memory data transfer DMA channel will provide a...
RSL10 Hardware Reference 12.2.8.5 DMA_NEXT_SRC_ADDR The following bit fields and field names apply equally to all registers. DMA_NEXT_SRC_ADDR[*] Bit Field Field Name Description 31:0 Address of the next data to be transferred using DMA channel DMA_NEXT_SRC_ADDR 12.2.8.6 DMA_NEXT_DEST_ADDR The following bit fields and field names apply equally to all registers.
Indicate that a channel disable DISABLE_INT_STATUS DMA_DISABLE_INT_STATUS interrupt has occurred 12.3 T IMERS The RSL10 system provides five timers including: • The SysTick timer from the ARM Cortex-M3 processor, which is described in Section 14.2, “SysTick” on page 409 • Four general-purpose timers Each general-purpose timer provides: •...
RSL10 Hardware Reference • bit is used to select between fixed initial division of slow clock by 2 or by 32 TIMER_CFG_CLK_SRC • bit field is used to increase the scaling factor by a power of two, allowing the TIMER_CFG_PRESCALE selection of a clock that is additionally divided by as much as 128 for each timer.
ON Semiconductor Register Name Register Description Address Timer current value register 1 0x40000424 TIMER_VAL[1] Timer current value register 2 0x40000428 TIMER_VAL[2] Timer current value register 3 0x4000042C TIMER_VAL[3] 12.3.3.1 TIMER_CFG The following bit fields and field names apply equally to all ] registers.
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Divide the input clock frequency by 1 0x0* PRESCALE TIMER_PRESCALE_1 Divide the input clock frequency by 2 TIMER_PRESCALE_2 Divide the input clock frequency by 4 TIMER_PRESCALE_4 Divide the input clock frequency by 8...
ON Semiconductor The watchdog timer runs on a prescaled clock that has been derived from the slow clock using a fixed division of 1024. This clock is used to decrement the value in the watchdog’s 13-bit counter. When the watchdog timer is refreshed, a configurable number of bits in the 13-bit counter are set and the prescaling counter is reset.
RSL10 Hardware Reference 12.4.1.2 WATCHDOG_CTRL Bit Field Field Name Description 31:0 Write a key to reset the watchdog WATCHDOG_REFRESH Field Name Value Symbol Value Description Hex Value Write 32-bit key to reset the watchdog 0x2B1E211 WATCHDOG_REFRESH WATCHDOG_REFRESH (other values have no effect)
CHAPTER 13 Audio 13.1 D (DMIC) I IGITAL ICROPHONE NPUTS The DMIC block provides a serial audio interface for up to two channels, using a pulse density modulated (PDM) digital output stream. The DMIC input data is decimated in a two-step process: A filter supporting a decimation range between 8 and 36 is used.
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RSL10 Hardware Reference • bit-field defines the decimation rate applied to data input from the DMIC. The AUDIO_CFG_DEC_RATE decimation factor as a function of the register is as follows: AUDIO_CFG_DEC_RATE Decimation Factor AUDIO_CFG_DEC_RATE + 8 • bit is used to select either clocking the DMIC input signal with the audio...
ON Semiconductor before it is overwritten with a subsequent sample. If an overrun has occurred, this flag remains set until the corresponding bit is used to clear it. AUDIO_STATUS_DMIC*_OVERRUN_FLAG_CLEAR Data received from the DMIC input samples is decimated into 18-bit samples, using a two-phase decimation filter.
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RSL10 Hardware Reference Bit Field Field Name Description Data alignment in AUDIO_OD_DATA OD_DATA_ALIGN Enable output driver output OD_ENABLE Enable the DMA request when a new DMIC1 sample is ready DMIC1_DMA_REQ_EN Enable the interrupt generation when a new DMIC1 sample is ready...
ON Semiconductor Field Name Value Symbol Value Description Hex Value OD_DATA is 16-bit LSB aligned 0x0* OD_DATA_ALIGN OD_DATA_LSB_ALIGNED OD_DATA is 18-bit MSB aligned OD_DATA_MSB_ALIGNED Disable the OD output 0x0* OD_ENABLE OD_DISABLE Enable the OD output OD_ENABLE Disable the DMA request when a...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Reset the OD underrun detection OD_UNDERRUN_FLAG_CLEAR OD_UNDERRUN_FLAG_CLEAR sticky bit Indicates that no OD underrun has 0x0* OD_UNDERRUN_FLAG OD_UNDERRUN_NOT_DETECTED been detected Indicates that an OD underrun has OD_UNDERRUN_DETECTED been detected...
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ON Semiconductor Field Name Value Symbol Value Description Hex Value Delay disabled 0x0* DMIC1_DELAY DMIC1_DELAY_DISABLE Delay of 0.125 samples DMIC1_DELAY_0P125 Delay of 0.25 samples DMIC1_DELAY_0P25 Delay of 0.375 samples DMIC1_DELAY_0P375 Delay of 0.5 samples DMIC1_DELAY_0P5 Delay of 0.625 samples DMIC1_DELAY_0P625 Delay of 0.75 samples...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value Cut-off frequency is Fs/3200 (5 Hz at 0x0* DMIC0_DCRM DMIC0_DCRM_CUTOFF_5HZ Fs=16 kHz) Cut-off frequency is Fs/1600 (10 Hz at DMIC0_DCRM_CUTOFF_10HZ Fs=16 kHz) Cut-off frequency is Fs/800 (20 Hz at...
UTPUT RIVER The output driver provides a mono digital audio output from the RSL10 system. This output driver can be connected to drive one or more DIO pairs, which are used as the driver for a speaker or receiver. The output driver consists of four stages:...
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This includes: AUDIO_STATUS • bit, which indicates if the output driver is included in this version of RSL10 AUDIO_STATUS_OD_STATUS • bit, which indicates when a new audio sample is required for the AUDIO_STATUS_OD_DATA_REQ_FLAG output driver.
ON Semiconductor Table 32. Recommended Output Driver Configuration Register Bit Field Setting Notes Set supplied clock frequency to between 1 and 2 MHz (1 MHz for lowest power CLK_DIV1 AUDIOCLK_PRESCALE consumption, 2 MHz for lowest high frequency noise). AUDIOSLOWCLK_PRESCALE Prevent the output driver from driving...
RSL10 Hardware Reference Field Name Value Symbol Value Description Hex Value DC removal filter disabled 0x0* DCRM DCRM_DISABLE Cut-off frequency is OD_CLK/800000 DCRM_CUTOFF_1P25HZ (1.25 Hz at OD_CLK=1 MHz) Cut-off frequency is OD_CLK/400000 DCRM_CUTOFF_2P5HZ (2.5 Hz at OD_CLK=1 MHz) Cut-off frequency is OD_CLK/266667 DCRM_CUTOFF_3P75HZ (3.75 Hz at OD_CLK=1 MHz)
+/-22 ppm can be achieved. An example employing the audio sink block for this use case can be seen in the calibration library, as described in the RSL10 Firmware Reference. The audio sink clock being measured is sourced from a DIO or from STANDBYCLK, as specified by the DIO configuration.
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RSL10 Hardware Reference AUDIOSINK_CNT[i-1] Audio si nk clock AUDIOSINK_PERIOD_CNT[i-1] BLE/RF frame pulse AUDIOSINK_PHASE_CNT[i-1] AUDIOSINK_PHASE_CNT[i] SY SCLK Figure 38. Audio Sink Timing The measurement registers are defined as follows: • register holds the integer number of cycles of the audio sink clock being measured AUDIOSINK_CNT between consecutive BLE/RF frame pulses.
ON Semiconductor • bit, which clears and starts the phase counter AUDIOSINK_CTRL_PHASE_CNT_START_NO_WAIT immediately. • bit, which stops the phase counter mechanism manually. AUDIOSINK_CTRL_PHASE_CNT_STOP • bit, which indicates whether the phase counter mechanism is AUDIOSINK_CTRL_PHASE_STATUS currently active or idle. • register, which contains the number of SYSCLK cycles between when the...
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RSL10 Hardware Reference Bit Field Field Name Description Stop the audio sink clock period counter mechanism PERIOD_CNT_STOP Start the audio sink clock period counter mechanism PERIOD_CNT_START Audio sink clock phase counter missed status PHASE_CNT_MISSED_STATUS Audio sink clock phase counter status...
ON Semiconductor 13.3.1.2 AUDIOSINK_CFG Bit Field Field Name Description Defines over how many audio sink clock periods the period counter measures PERIODS_CFG Field Name Value Symbol Value Description Hex Value Measure 1 audio sink clock period 0x0* PERIODS_CFG AUDIO_SINK_PERIODS_1 Measure 2 audio sink clock periods...
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RSL10 Hardware Reference The ASRC is configured with the register. This register configures: ASRC_CFG • The ASRC operates in one of four modes, controlled by the setting. Use of these ASRC_CFG_ASRC_MODE modes is dependent on the relationship between the source (F...
ON Semiconductor • This 30-value register array holds the internal filter states of the polyphase filter. The ASRC_STATE_MEM: number of states that need to be stored depends on the setting, as outlined in Table 33 ASRC_CFG_ASRC_MODE on page 396. Data is provided to the ASRC through the register.
RSL10 Hardware Reference Bit Field Field Name Description Write a 1 to reset ASRC ASRC_RESET Enable status of the re-sampler block ASRC_EN_STATUS Disable the re-sampler block ASRC_DISABLE Enable the re-sampler block ASRC_ENABLE Field Name Value Symbol Value Description Hex Value...
ON Semiconductor Field Name Value Symbol Value Description Hex Value This source can not set an interrupt ASRC_UPDATE_ERR INT_DIS_ASRC_UPDATE_ERR This source can set the interrupt line 0x1* INT_EBL_ASRC_UPDATE_ERR This source can not set an interrupt 0x0* ASRC_IN_ERR INT_DIS_ASRC_IN_ERR This source can set the interrupt line...
RSL10 Hardware Reference 13.4.1.7 ASRC_PHASE_INC Bit Field Field Name Description 31:0 ASRC phase counter increment step size ASRC_STEP 13.4.1.8 ASRC_PHASE_CNT Bit Field Field Name Description 31:0 ASRC phase counter ASRC_PHASE_CNT 13.4.1.9 ASRC_STATE_MEM Bit Field Field Name Description 31:0 ASRC State Memory 0 to 29 ASRC_STATE_MEM www.onsemi.com...
ARM Cortex-M3 processor and is described in the ARM Cortex-M3 Technical Reference Manual. The ARM Cortex-M3 processor as implemented for RSL10 uses pulse interrupts. These interrupts are sampled on the rising edge of SYSCLK. A pulse interrupt can be reasserted during the ISR so that the interrupt can be in the pending state and active at the same time.
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RSL10 Hardware Reference Table 34. Interrupts in the ARM Cortex-M3 Processor (Continued) Interrupt Enumeration Define Enumeration Value Vector Number Description DIO0_IRQn DIO0 interrupt DIO1_IRQn DIO1 interrupt DIO2_IRQn DIO2 interrupt DIO3_IRQn DIO3 interrupt WATCHDOG_IRQn Watchdog interrupt SPI0_RX_IRQn SPI0 receive interrupt SPI0_TX_IRQn...
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1 interrupt BLE_AUDIO2 Audio over Bluetooth low energy technology channel 2 interrupt Table 35 lists the NVIC registers. The following subsections describe their bit fields and use by the RSL10 microcontroller. Table 35. NVIC Control Registers Register Name Register Description...
Table 36. Interrupt Controller Type Register Bit Assignments Bit Field Field Name Description INTLINESNUM Total number of interrupt line groups: RSL10 uses 69 external interrupts (NVIC_INTLINESNUM_65_96, hex value 0x2) 14.1.2 Interrupt Set Enable and Clear Enable Registers Use the Interrupt Set Enable registers ( ) to:...
RSL10 Hardware Reference These registers are part of the ARM Cortex-M3 processor’s register block. Table 37 describes the field of the NVIC Interrupt Set-Enable registers. Table 38 describes the field of the Interrupt Clear-Enable registers. Table 37. Interrupt Set-Enable Register Bit Assignments...
ARMv7M Architecture Reference Manual. The NVIC for the ARM Cortex-M3 processor in the RSL10 system has been implemented with four interrupt priority bits per interrupt. These four priority bits are MSB aligned to an eight-bit priority bit field as required by ARM.
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RSL10 Hardware Reference bit field from the Application Interrupt and Reset Control register (see the ARMv7M SCB_AIRCR_PRIGROUP Architecture Reference Manual) is used to divide the interrupt priority settings into interrupt groups, and to prioritize interrupts within those groups. The possible configurations for the division of the priority bit field into pre-emption priority and subgroup priority is shown in Table 42.
ON Semiconductor 14.1.6 Registers Described by ARM Documentation The following registers are documented in the ARMv7M Architecture Reference Manual: • Interrupt Control State register • Vector Table Offset register • Application Interrupt and Reset Control register • System Control register •...
RSL10 Hardware Reference 14.2.1 SysTick Control and Configuration Registers Register Name Register Description Address SYSTICK Control and Status Register 0xE000E010 SysTick_CTRL SYSTICK Reload Value Register 0xE000E014 SysTick_LOAD SYSTICK Current Value Register 0xE000E018 SysTick_VAL SYSTICK Calibration Register 0xE000E01C SysTick_CALIB IMPORTANT: The SysTick timer is a standard component provided with the ARM Cortex-M3 processor. The registers for this peripheral are defined in core_cm3.h and augmented by defines for the bit fields, bit settings...
• To break a stalled memory access, where the memory access might be stalled due to a memory conflict with another component of the RSL10 system, set the bit. CoreDebug_DHCSR_C_SNAPALL The Debug Exception and Monitor Control Register (...
RSL10 Hardware Reference also provides a variety of debug related status information, including: DHCSR • If the core has been reset or is resetting ( ); this bit is cleared when read CoreDebug_DHCSR_S_RESET_ST • If an instruction has completed execution since this register has been last read; this bit is cleared when read •...
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ON Semiconductor 14.3.4 Debug Fault Status Register The Debug Fault Status register ( ) is used to monitor debug events including: DFSR • External debug requests • Vector catches • Data watchpoint matches • instruction execution BKPT • Halt requests Each flag in the Debug Fault Status register is set independently when its debug condition occurs.
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RSL10 Hardware Reference 14.3.5.1 SCB_DFSR Settings Bit Field Field Name Description EXTERNAL Indicate if an external debug request has been asserted. The processor stops on the next instruction boundary. VCATCH Indicate if a vector catch occurred. When the VCATCH flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault.
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ON Semiconductor 14.3.5.4 Debug Exception and Monitor Control Register Bit Field Field Name Description MON_REQ Indicate if a debug monitor exception has been triggered by a pending manual request or a hardware debug event MON_STEP Single-step the core; this bit can only be written if the debug monitor exception is...
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APPENDIX A Control and Configuration Registers This appendix lists all the registers that are available. Refer to the appropriate section for information about the control and configuration registers for a block. The sections are: • Section A.1, “Chip Identification” on page 417 •...
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APPENDIX B Glossary The following abbreviations and terms are used in this manual: analog control system analog-to-digital converter analog front-end cyclic redundancy check digital-to-analog converter digital input/output direct memory access error correcting code generic access profile general-purpose input/output GPIO high impedance inter-IC communication protocol inter-IC sound protocol integral non-linearity...
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RSL10 Hardware Reference phase-locked loop power management unit pulse width modulation power-on-reset random-access memory radio-frequency front-end RFFE read-only memory real-time clock serial clock (part of I C bus) serial data (part of I C bus) serial peripheral interface serial wire debug, two-wire interface used for communication with ARM cores...
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