High-Speed Memory; Introduction; Hsm Addressing - RCA Spectra 70 Training Manual

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HIGH-SPEED MEMORY
INTRODUCTION
The RCA 70/25 magnetic core High-Speed Memory
(HSM) may consist of one, two or four memory
planes. Each plane contains 16,384(10) byte locations
(4 x 64 x 64 bytes). The byte is the smallest addres-
sable unit in memory, and is made up of eight
information bits and a parity bit.
BYTE
Bit Identification
P
27
2 6
2 5
24
2 3
22
21
2 0
Bit (X
=
0 or 1)
X
X
X
X
X
X
X
X
X
Four bytes of HSM may be transferred to a memory
register and regenerated in memory within 1.5
microseconds. These four bytes are moved side by
side or in parallel.
MEMORY REGISTER
0
1
HSM
2
3
To save processing time, the memory access hard-
ware moves instructions and data in four byte units
whenever possible, returning to a byte after byte
or serial transfer when necessary to stay within
limits defined by a specific operation. These four
byte units are called words. The first four bytes
of memory, locations 0, 1, 2, and 3, constitute the
first word. The second begins with location 4, and
the third with 8, etc. Even Word boundary is the
term used to describe the initial byte of each word;
locations 0, 4, 8, etc. The addresses contained in
several 70/25 instructions must begin at even-word
boundaries (see page 41).
HSM ADDRESSING
The address of each byte location is expressed as
a binary number. Sixteen bits are required to ad-
dress the highest location of a four plane system
(65,536).
3
Examples:
BINARY ADDRESS
215 214 2 13 212 211 2 10 2 9 2 8 27
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
2 6 2 5 24 2 3
0
0
1
1
1
1
0
1
1
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
22 21 2 0
0
0
1
1
0
1
1
1
1
1
1 I 0
0
o
I
0
1
1
1
DECIMAL
EQUIVALENT
25
109
879
4.094
16.512
65,535
The first example shows the binary representation
of HSM location 25. The conversion to decimal re-
quires the adding of the 2 n value of all bits that are
one (1).
BINARY
DECIMAL EQUIVALENT
2 0
1
2 3
8
24
16
-
25
Within the 70/25 instruction format two bytes, 16
bits, are allocated for each memory address.
1 st ADDRESS
2nd ADDRESS
An address is divided into two parts: (1) a displace-
ment of 12 bits contained in the instruction, and (2)
a base address which is pre-stored in one of the
fifteen General Registers.
The most significant four bits of each address, the
Bl or B2 fields, designate the General Register
containing the associated base address.
B FIELD
0001 (2)
-
General Register 1
1000(2)
-
General Register 8
1111(2)
-
General- Register 15
0000(2)
-
No base address
Assume
that
General
Register
One
contains
40,000(10) .

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