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ELAPSED TIMER INTERRUPT
General Register Zero serves as an elapsed time
clock. Every 16-2/3 milliseconds (using 60 cycle
power) the power supply generates a (1) 2 bit that is
added to the contents of Register Zero. When the
register overflows, interrupt takes place. The time
intervals between interrupts is controlled by the
value pre-stored in the register (see page 13).
Before transfer to the P2 state, the current setting
of the Condition Code is stored in the 2 0 - 2 1 bits of
reserved location forty-three (2Bh6' and the code
reset to (11)2'
INHIBITING INTERRUPT
All interrupts except the Operation Code Trap may
be inhibited.
Reserved HSM location forty-nine
(31)16 allows the user to inhibit interrupt on all or
selected I/O channels. The user places a mask into
the eight rightmost bit positions of the reserved loca-
tion. The bit positions, (2 0 -2 7 ), correspond to the
eight I/O channels, 0-7. A (1)2 bit permits interrupt
and a (0)2 bit inhibits it.
LOCATION 49 (31)16
A mask of 10010110 allows channels one, two, four
and seven to interrupt, and inhibits interrupt from
channels zero, three, five, and six.
If an interrupt on an I/O channel is inhibited, the
channel remains busy until a Post Status instruction,
addressed to that channel, is executed (see page 53).
Three bit positions (22_2°) in reserved location
forty-eight (30) 16 allow the user to inhibit the Elapsed
Timer,
Arithmetic Overflow,
and MULTIPLEX
CHANNEL interrupts.
2 1 =Overflow
22=Timer
2 0co
Multiplex Channel
A mask of 101 in the 22_2 0 allows Timer and Multi-
plex interrupt, but inhibits interrupt caused by
arithmetic overflow or divide exception.
INTERRUPT PRIORITIES
Op Code Trap - immediate
I/O
1
Elapsed Timer
2
Overflow and
Divide Exception 3
11
Exercise:
T
F
1.
Only fifteen of the thirty-one 70/25 in-
structions
can be executed in the
Interrupt State.
T
F
2.
The main program is executed in the
Processing State.
T
F
3.
The
Processing State is not inter-
ruptible.
T
F
4.
The Interrupt State is not interruptable.
T
F
5.
The Condition Code is stored prior to
changing states.
T
F
6.
The Condition Code is always set to 00
prior to going into the P2 state.
T
F
7.
The two program counters are stored
in the reserved area of memory.
T
F
8.
The Processing State uses only one
counter to indicate the address of the
next instruction.
T
F
9.
The PI counter is destroyed by the
interrupt.
T
F 10.
The computer remains in the P2 state
until another interrupt occurs.
T
F 11.
The operation code is stored on an
Operation Code Trap.
T
F 12.
The Standard Device Byte is stored on
an Operation Code Trap.
T
F 13.
Interrupt from any
r/o
device is the
only interrupt that can be inhibited.
14.
Describe the use of HSM location 49.
15.
Describe two uses of the Operation Code
Trap.
16.
Write the masks necessary to inhibit all
possible interrupts. Where must they
be stored?
17.
Describe what is stored in reserved
memory when each of the four types of
interrupt takes place.
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