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Interrupt; Introduction; Programming States; Processing State - RCA Spectra 70 Training Manual

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INTERRUPT
INTRODUCTION
An interrupt facility provides an automatic means for
the detection of exceptional conditions, and a method
for an immediate program response. The function
of sensing for exceptional conditions and the auto-
matic transfer of control to software has been
mechanized in the RCA 70/25 hardware. Combining
software with the hardware interrupt makes it
unnecessary to halt the computer when an error
develops, and eliminate s program sensing of external
demands. This system allows the user to program a
response independently of his production processing.
PROGRAMMING STATES
All instructions are executed in one of two states:
(1) the Processing State (P1) , or (2) the Interrupt
State (P2). The Processing State is the normal mode
of operation.
An
interrupt causes the computer to
transfer from the Processing State to the Interrupt
State where it remains until instructed to return to
the original Processing State.
PROCESSING STATE
During the execution of instructions in the P1 state
the address of the next instruction to be executed is
stored in the P1 counter (reserved HSM forty (28)16
and forty-one (29)16'
BYTE
(40)10
BYTE
(41)10
121512141213121212111210129128127126125124123122121120
I
PI COUNTER
Each time an instruction is staticized in the P1 state
the contents of the P1 counter is updated to contain
the address of the next instruction. All thirty-one
instructions may be executed in the P1 state. The
computer remains in this state until an interrupt
occurs.
INTERRUPT STATE
When an exceptional condition is detected, and an
interrupt initiated, the hardware transfers control
to the instruction whose address is stored in the P2
counter (reserved HSM forty-four (2C)16 and forty-
five (2D)16)'
BYTE
(44)10
P2 COUNTER
9
The system is now in the Interrupt State. Each time
an instruction is staticized the contents of the P2
counter is updated to contain the address of the next
instruction to be executed. All thirty-one instruc-
tions may be executed in the P2 state, and the com-
puter remains in this state until a STPP2 instruction
(see page 39) is executed. The STPP2 instruction
resets the P2 counter to its original value, and
returns Control to Pl. The Interrupt State is not
interruptable.
Any interrupt attempted will be
"PENDING" until the computer returns to the Process
State.
Interrupt occurs only after the termination of an
instruction.
Therefore, when the system returns
to the Process after interrupt, the P1 counter holds
the address of the instruction that immediately fol-
lows the point where interrupt took place.
This
automatic linkage permits the user to disregard
interrupt considerations when programming his
process.
TYPES OF INTERRUPT
There are four conditions that can interrupt the
Processing State:
1.
I/O Device (Manual or Termination)
2.
Operation Code Trap
3.
Arithmetic Overflow or Divide Exception
4.
Elapsed Timer Overflow
1/0 INTERRUPT
An interrupt occurs after the termination of each
Input/Output Command. A termination interrupt
indicates one of two possible terminating conditions:
1.
The I/O instruction was not completed success-
fully (ERROR).
In this case, the Secondary
Indicator bit in the Standard Device Byte is (1) 2
(see page 53).
2.
The channel and device that executed the instruc-
tion is now free, and ready to receive the next
command (NORMAL TERMINATION).
In this
event, the 26 bit of the Standard Device Byte is
set to (1)2' (see page 53).
The purpose of normal termination interrupt is to
notify system software that an I/O channel is avail-
able. With this knowledge, the software can use

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