ELAPSED TIME CLOCK
The least significant 24 bits of Register Zero, the
first General Register, may serve as an elapsed time
clock. The 70/25 power supply generates a (1)2 bit
every 16-2/3 milliseconds (60 cycle power). This
bit is added to the contents of Register Zero. When
register overflow develops, an interrupt is initiated
(see page 11). The programmer may control the
time interval between these interrupts by the selec-
tion of the value stored in the register.
A (1) 2 is added to the low order bit of the register
50 CYCLE POWER
60 CYCLE POWER
1 ADD EVERY 20 MILLISECONDS
1 ADD EVERY 16-2/3 MILLISECONDS
50 ADDS EVERY SECOND
60 ADDS EVERY SECOND
3000 ADDS EVERY MINUTE
3600 ADDS EVERY MINUTE
180000 ADDS EVERY HOUR
216000 ADDS EVERY HOUR
If the Timer is set to a value of all one bits
(16,777,215>10' the first add causes overflow.
the Timer contains all zeros, overflow will take
place approximately 93 hours later, using 50 cycle
power, or 77 hours later using 60 cycle power.
The number of adds required to clock off more
meaningful time intervals are indicated below:
60 CYC LE POWER
bit Timer is
. Let us assume we wish to generate
an interrupt every minute. By subtracting 360010'
the number of adds executed in a minute, from the
overflow value, we can determine the amount to be
stored in the register.
It should be remembered that the timer contents is
reduced to zero at the point of overflow. As long as
the initial value is added to the register contents be-
fore the computer returns to the Processing State,
no time loss results.
Regi ster Zero may not be used for general storage
purposes. Even though interrupt has been inhibited
(the 22 bit of reserved HSM location 48 is (0)2), the
addition of (1) 2 bits to the register contents continues.
If we want interrupt after 5 minutes and 30 seconds,
what value should be stored in register zero?