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Model
DRC-93C
Section Iv
the ASCII letter Q followed by two
will
allow the setting of the
alphanumerics representing the most
Overload/Error Indicator and Sample
significant four bits and the least
Data Ready bits
in the Status
significant four bits, respectively.
Register, but will not send an
Note that the controller can be
Service Request if either condition
programmed for more than one set of
is met.
Q61 however will allow
conditions simultaneously. To enable
either of these bits to be set and
the Service Request, Bit
6
must be
when either is set, an Service
a
1 .
Request will be issued by the DRC-
93C over the IEEE-488 Bus.
This
4 . 1 1 . 3 . 1
Status
Register Mask Bits
Service Request will remain on the
0
and
1
-
Sample and Control Data
Bus until either a Serial poll is
Ready Enables.
If either Bit
0
or
initiated or the cause of the
Bit
1
of the Status Register Mask
setting of the SRQ is eliminated.
is set
(1)
,
then for that data, the
corresponding bit in the Status
The Status Register mask and control
Register is set when a valid data
channel limit is part of the power-
reading is available.
up save settings like the set point
and units.
It is updated on power-
4 . 1 1 . 3 . 2
Status
Register Mask Bit
2-
up to the last settings with internal
The Control
Channel
Limit Enable.
switch
2
set.
On power up the
If the control channel limit (Figure
Status Register mask is set to
00
4-2, Bit
2)
is selected, the limit
and the control channel limit to
must follow the Q comand and is in
0 0 0 . 0
if switch
2
is off.
a free field format.
Examples are
XXX.X,
.x,
x.x, xx.x, x.,
xx.,
etc.
4 . 1 1 . 3 . 5
Examples for setting Mask
If Bit
2
of the Mask is set
(1)
,
then when the control sensor reading
Example
#1
-
Q61
-
Sample Data
gets within the chosen limit from
Ready with the Service Request bit
the set point, the corresponding
(SRQ) on.
-
With the SRQ bit of the
bit i s set in the Status Register.
Status Register mask enabled, the
DRC-93C
SRQ
interrupt will
be
4 . 1 1 . 3 . 3
S t a t u s Register
Mask Bit
3-
generated.
The BUS CONTROLLER can
Sample Sensor Channel Change Enable
read the
Status Register to determine
If the Sensor Channel Change (Bit
appropriate instrument conditions.
3)
is selected, then bit
3
in the
In this case bits
1
is continuously
Status Register
is set when
a
updated to reflect current instrument
channel change occurs.
status of the Sample Data Ready. Q61
also results in a service request
4 . 1 1 . 3 . 4
Status
Register Mask Bit 5
if an \
is indicated.
-
Overload/Error Indicator Enable.
If
the
Overload/Error
Indicator
Example
#2
-
Q2F000.1
-
All Status
Enable Bit
(5)
is set, then if the
Reports with the SRQ bit off.
-
display has an overload condition
With the SRQ bit of the Status
on any channel or an error occurs,
Register mask
disabled, no SRQ
the corresponding bit on the Status
interrupt by the DRC-93C will be
Register
is set and a Service
generated, however, the BUS
CON-
Request is issued if the SRQ bit of
TROLLER can still read the Status
the mask is a
1 .
The user can
Register and this command will give
check which overload or error was
all five Status Reports.
detected by sending the Output Data
Statement W0 (See Section
4.14.2
Example
#3
-
Q06000.1
-
Enable the
and Table
4-15).
Control
Data Ready
and
Control
Channel Limit with
a
band of 0.1
For example, in Figure 4-2,
Q21
about the control point.
COPYRIGHT
3/88
LSCI
4-21
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