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Section IV
Model
DRC-93c
Status Register is set when a
Mask is provided to allow the user
channel change occurs for the
to select whether he wants a given
Display. If the Service Request is
Status Report or not.
The various
enabled this bit being set will
bits of the Status Register Mask
cause the DRC-93C to pull the SRQ
enable the various Status Reports.
management low to signal the
BUS
The bits in the Status Register
CONTROLLER.
Mask have the same bit position as
bit is reset to zero upon reading
the bits in the Status Register.
the Status Register.
Only those bits which are allowed
This function can be inhibited by
by the Status Register Mask Command
turning off the bit
3
in the Status
are potentially changeable in the
Register Mask.
Status Register.
Note that the
corresponding bit in the Status
4.11.2.4
Status Report
5
-
Overload
Register Mask determines whether
E r r o r
I n d i c a t o r .
If the display
its
counterpart
in
the Status
has an overload condition on any
Register can change.
selected channel or an error occurs,
then bit
5
of the Status Register
The Status Register Mask is shown
is set and a Service Request is
in Figure 4-2.
It consists of
8
issued if enabled.
This Status
bits, one bit (bit
6 )
which deter-
Register bit is reset to zero upon
mines whether the DRC-93C is to
reading the Status Register.
report via the SRQ line and five
bits to determine which Status
This function can
be
inhibited by
Reports to make.
Bit
6
is
the SRQ
turning bit
5
off in the Status
(Service Request) bit and if set
Register Mask.
allows the DRC-93C to send out a
Service Request on the SRQ IEEE-488
4.11.2.5
When operating without the
line.
If the SRQ bit is not set
Service Request
it is still possible
(off) then the DRC-93C is inhibited
for the BUS CONTROLLER to read the
from producing a Service Request.
Status Register.
The
Service
The Status Register can still be
Request is inhibited by turning off
read by
the BUS CONTROLLER to
the SRQ bit (bit
6 )
in the Status
examine the Status Reports, but the
Register Mask.
BUS
CONTROLLER will not be inter-
rupted by
the Service Request.
However, it must be understood that
Five of the other seven bits select
certain bits in the Status Register
which of the five Status Reports to
are continually changing.
The
make. If one of these five bits is
Status Reports for the Overload/Er-
set (on), the DRC-93C will update
ror, Display Data Ready, and Control
the corresponding Status Report bit
Data Ready are continuously updated
in the Status Register.
Then if
to
reflect current
instrument
the SRQ bit (bit
6 )
of the Status
status.
The Channel Change and
Register Mask is set, the DRC-93C
Control Channel Limit once encount-
will send out a Service Request on
ered are latched (set to
1 )
and
the SRQ IEEE-488 line.
By
means of
remain latched until the Status
a serial poll enable
(SPE),
the
B U S
Register is read.
CONTROLLER
determines that the DRC-
93C has sent out a service request
4.11.3
The Status Register M a s k
-
and then reads the Status Register.
Reading the Status Register resets
the Status Register to all zeros.
The Status Reports listed above may
Executing the Q command also resets
not be desired or perhaps only a few
the Status Register to all zeros.
are of interest. The Status Register
The Status Register Mask command is
4-20
COPYRIGHT
3/88
LSCI
This Status Register
The
Qc1c2
Command
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