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Ingenic JZ4780 Programming Manual

Mobile application processor
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JZ4780
Mobile Application Processor
Programming Manual
Release Date: Jan 6, 2013

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Summary of Contents for Ingenic JZ4780

  • Page 1 JZ4780 Mobile Application Processor Programming Manual Release Date: Jan 6, 2013...
  • Page 2 Ingenic Terms and Conditions of Sale. Ingenic products are not designed for and should not be used in any medical or life sustaining or supporting equipment. All information in this document should be treated as preliminary. Ingenic may make changes to this document without notice.

  • Page 3: Table Of Contents

    Config7 Register (CP0 Register 16, Select 7)............... 20 2.2.10 Mailbox0 (CP0 Register 20, Select 0) ................21 2.2.11 Mailbox1 (CP0 Register 20, Select 1) ................21 Application Notes ........................21 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 4 5.6.7 Background0 Color Register (LCDBGC0) ..............62 5.6.8 Background1 Color Register (LCDBGC1) ..............62 5.6.9 Foreground Color Key Register 0 (LCDKEY0) .............. 62 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 5 TFT and CCIR Pin Mapping ..................83 5.7.2 Data mapping to GPIO function..................85 Display Timing ........................86 5.8.1 General 16-bit and 18-bit TFT Timing ................86 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 6 Data format ........................102 6.5.2 Command Format ......................102 Transfer Mode ........................103 6.6.1 DMA Transfer Mode ..................... 103 6.6.2 Register Transfer Mode ....................104 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 7 Source TLB base address of next frame ..............123 9.4.17 Destination TLB base address of next frame .............. 123 9.4.18 ADDRESS Mapping ....................124 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 8 10.3.3 LVDS Input Clock Edge-Delay Control ................ 151 10.3.4 Output data start-edge Control ..................152 10.3.5 PLL Input Divider Value Setting ................... 152 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 9 CIM Data Sampling Modes ....................175 11.3.1 Gated Clock Mode ....................... 175 11.3.2 ITU656 Interlace Mode ....................176 11.3.3 ITU656 Progressive Mode................... 177 11.4 DMA Descriptors ......................... 178 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 10 AC ‘97 CODEC Power Down ..................218 12.4.2 Cold and Warm AC ‘97 CODEC Reset ................ 218 12.4.3 12.4.4 External CODEC Registers Access Operation ............219 viii JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 11 14.1 Overview ..........................247 14.2 Features ..........................247 14.2.1 Signal Descriptions ...................... 248 14.2.2 Block Diagram ......................249 14.2.3 Application schematic ....................250 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 12 14.18.3 STANDBY mode ...................... 300 14.18.4 SLEEP mode ......................300 14.18.5 Initial all the gain ...................... 301 14.18.6 Soft Mute mode ......................301 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 13 RCMDCTRL0 (Performance rcmd request control) ..........341 15.2.12 RCMDCTRL1 (Performance rcmd request control) ..........343 15.2.13 WDATTHD0 (performance wcmd request control) ..........343 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 14 BCH Interrupt Status Register (BHINT) ............... 392 17.2.9 BCH Interrupt Enable Set Register (BHINTES) ............394 17.2.10 BCH Interrupt Enable Clear Register (BHINTEC) ........... 394 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 15 Timer Mast Register (TMR) ..................470 19.3.12 Timer Mask Set Register (TMSR) ................471 19.3.13 Timer Mask Clear Register (TMCR) ................ 471 xiii JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 16 Interrupt Controller Mask Clear Register (ICMCR0) ............ 492 21.2.8 Interrupt Controller Mask Clear Register (ICMCR1) ............ 492 21.2.9 Interrupt Controller Pending Register (ICPR0) ............493 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 17 DMA Soft IRQ Mask ....................516 23.5.8 DMA Channel IRQ Pending to MCU ................516 23.5.9 DMA Channel IRQ to MCU Mask ................516 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 18 SLEEP mode Sample Operation ................. 541 24.3.4 VBAT Sample Operation ....................542 24.3.5 AUX Sample Operation ....................542 24.3.6 Disable Touch Screen ....................542 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 19 Write EFUSE Flow ...................... 570 26.3.2 Write Security Key Flow ....................570 26.3.3 Read EFUSE Flow ...................... 570 26.3.4 Read Security Key/Random Number Flow ..............571 xvii JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 20 PORT Mask Registers (PxMSK) .................. 599 28.2.6 PORT Mask Set Registers (PxMSKS) ................. 599 28.2.7 PORT Mask Clear Registers (PxMSKC) ..............600 xviii JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 21 SSI Receive Counter Register (SSIRCNT) ..............648 30.4 Functional Description ......................648 30.5 Data Formats ........................648 Motorola‘s SPI Format Details ..................649 30.5.1 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 22 Features ..........................675 32.3 Pins Description........................675 32.4 Block Diagram ........................676 32.5 MMC/SD Controller Signal I/O Description ................. 676 32.6 Register Description ......................677 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 23 Start and Stop clock ..................... 715 32.8.4 Software Reset ......................715 32.8.5 Voltage Validation and Card Registry ................716 32.8.6 Single Data Block Write ....................718 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 24 ETU Counter Value Register (SCCECR) ..............833 32.11.8 Reception Timeout Register (SCCRTOR) ............... 834 33 KMC Controller................835 33.1 Overview ..........................835 xxii JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 25 MSC0 Boot Specification ....................853 34.6 eMMC Boot Specification ....................854 34.7 msc1 boot Specification ...................... 855 34.8 Spi boot Specification ......................855 xxiii JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 27: Tables

    Table 14-2 Internal CODEC Mapped Registers Description (AIC Registers) ......251 Table 15-1 DDRC Register ......................323 Table 16-1 NEMC Pin Description ....................351 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 28 Table 32-3 MMC/SD Controller Registers Map ................677 Table 32-4 Command Data Block Structure ................703 Table 32-5 Card Status Description .................... 706 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 29 Table 33-33 Host All Channels Interrupt Mask Register: HAINTMSK ........782 Table 33-34 Host Port Control and Status Register: HPRT ............783 Table 33-35 Host Channel-n Characteristics Register: HCCHARn ..........786 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 30 Table 34-2 The definition of 5 flags in NAND flash ..............845 Table 34-3 Transfer Types Used by the Boot Program ............... 849 Table 34-4 Vendor Request 0 Setup Command Data Structure ..........851 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 31 Table 34-8 Vendor Request 4 Setup Command Data Structure ..........852 Table 34-9 Vendor Request 5 Setup Command Data Structure ..........853 Table 34-10 SPI nor flash boot flag informations................ 856 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 33: Figures

    Figure 12-22 Transmitting/Receiving FIFO access via APB Bus ..........223 Figure 12-23 One channel (Left) and Two channels (right) mode (16 bits packed mode) ..225 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 34 Figure 16-12 Basic Timing of Toggle NAND Write ..............379 Figure 16-13 Basic Timing of Toggle NAND Read ..............380 Figure 16-14 Basic Timing of Toggle NAND Page Write ............380 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 35 Figure 33-2 Interrupt Hierarchy ....................732 Figure 33-3 Core Interrupt Handler .................... 733 Figure 34-1 Boot sequence diagram of JZ4780 ................. 844 Figure 34-2 the distribution and structure of the boot code in NAND ........846 Figure 34-3 JZ4780 NAND Boot Procedure ................848 Figure 34-4 USB Communication Flow ..................
  • Page 36 Figure 34-5 Typical Procedure of USB Boot ................851 Figure 34-6 JZ4780 eMMC Boot Procedure ................855 Figure 34-7 JZ4780 SPI Boot Procedure ..................857 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 37: Section 1 Overview

    OVERVIEW Section 1 OVERVIEW JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 38: Overview

    Overview 1 Overview JZ4780 is a mobile application processor targeting for multimedia rich and mobile devices like tablet computer, smart phone, mobile digital TV, and GPS. This SOC introduces a kind of innovative architecture to fulfill both high performance mobile computing and high quality video decoding requirements addressed by mobile multimedia devices.

  • Page 39: Block Diagram

    8 entry Instruction TLB  8 entry data TLB – L1 Cache  32kB instruction cache  32kB data cache – Hardware debug support JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 40: Vpu

     Frame buffer max size = 2048 x 2048  Texture max size = 2048 x 2048 – Texture Filtering  Bilinear, Trilinear, Anisotropic JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 41: Display

    Encoded pixel data of 16, 18 or 24 BPP in TFT mode  Support up to 16,777,216 (16M) colors in TFT mode  Support 24/16 BPP compressed data JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 42 Up scaling ratios up to 1:31 in fractional steps with 1/32 accuracy  Down scaling ratios up to 31:1 in fractional steps with 1/32 accuracy JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 43: Camera

    Programmable Interrupt function supported  Support share clock mode and split clock mode.  Support mono PCM data to stereo PCM data expansion on audio play back JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 44 – Separate power-down modes for ADC and DAC path with several shutdown modes – Reduction of audible glitches systems: Pop Reduction system, Soft Mute mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 45: Memory Interface

    Clock generation and power management  – On-chip 12/24/48MHZ oscillator circuit – External 32.768KHZ input – One four-chip phase-locked loops (PLL) with programmable multiplier JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 46 – A dedicated bus interface - NIF interconnects with on-chip NEMC or off-chip NEMC. – An extra INTC IRQ can be bound to one programmable DMA channel JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 47: Peripheral

    – Support using either positive or negative edge of TSCLK – Support PID filtering function – Up to 33 PID filters can be used when PID filtering function is enabled JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 48 – Independently controlled transmit, receive (data ready or timeout), line status interrupts – Internal diagnostic capability Loopback control and break, parity, overrun and framing-error is provided JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 49 OTP Slave Interface  – Total 8K bits. Lower 192bits are read only, other higher bits are read-able and write-able – Support Security boot. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 50: Bootrom

    Analog power supply 1: 2.5V± 10% Analog power supply 2: 3.3V± 10% Core: 1.1 -0.1/+0.2 V Package BGA390 17mm x 17mm x 1.1mm, 0.8mm pitch Operating frequency 1.2GHz JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 51: Section 2 Core Functions

    CORE FUNCTIONS Section 2 CORE FUNCTIONS JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 52: Cpu

    Software reset CORE1. 1 – keeps reset; 0 – not SW reset status SW_RST1 Software reset CORE0. 1 – keeps reset; 0 – not SW reset status SW_RST0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 53: Cores Status (Cp0 Register 12, Select 3)

    Rst ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 ? ? ? ? ? ? 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 54: Spinlock (Cp0 Register 12, Select 5)

    For write operation, the value updating the register can update SPINLOCK at the same time if the value in SPINLOCK equals zero. Therefore, an atomic writing-nonzero-to-spinlock operation can be performed. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 55: Processor Identification (Cp0 Register 15, Select 0)

    Rst 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 Bits Name Description Hardwired to 1 to present the existence of Config2. 30:25 MMU Size 0x1F: 32 entries JTLB. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 56: Config7 Register (Cp0 Register 16, Select 7)

    Permit modification of EBASE[30]. 1 – permit CFG_E30 PART_K Permit partial of kernel mode resources to be used by applications in user mode, including TCSM, CACHE JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 57: Mailbox0 (Cp0 Register 20, Select 0)

    As a SMP dual-core implementation of XBurst-1, for system programmers, following points must be paid attention to: A module named DCSC (Dual Core Schedule & Control) is a global IRQs (peripheral and IPI) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 58: Mapping Of Irqs Observed By Cpu Core

    For the SMP implementation, only one core can be debugged through EJTAG at any time. CORE0 can be debugged through EJTAG by default. To toggle among cores, use above instructions before using EJTAGBOOT JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 59: Vpu

    JPEG compressing/decompressing up to 100Mega-pixels per second (baseline) 3.1 Block Diagram VMAU DBLK JPGC VPU BUS XBurst TCSM VDMA SRAM ® Figure 3-1 VPU Block Diagram JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 60: Features Of Vpu

    1/4-pixel)  Interlaced mode support  Intensity compensation support  Weighted prediction support  Automatic rotation support for rotated referenced pictures JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 61: Internal Physical Address Base Definition

    3.3 Internal physical address base definition Table 3-2 VPU Internal physical address base definition Module Physical address base 0x1320_0000 0x132A_0000 TCSM 0x132C_0000 SRAM 0x132F_0000 VDMA 0x1321_0000 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 62: Aux

    When AUX wakes up by an NMI meanwhile NMI_DIS is 1, AUX just resumes from the next PC of the WAIT instruction. 3.4.1.2 SPINLOCK JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 63 Writing has no effect, read as zero. SPIN2 The operations for SPIN1 also fit SPIN2 except the role of SPIN1 should be replaced by SPIN2. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 64 Pending status of MIRQ (message IRQ to AUX) which can only be set 1 by HW and be clear to 0 by SW. This pending IRQ is routing to AUX. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 65: Tcsm/Sram

    2. SRAM should not be accessed when it is in using by VPU internally. 3.6 Video Acceleration Block Please refer to relative programming manual documents. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 66: Gpu

    8-bit Stencil with on chip tile stencil buffer  8 parallel depth/stencil tests per clock  Scissor test  Texture support Cube Map Projected Textures Non square Textures JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 67 32 Bit IEEE Float  2-way 16 bit fixed point  4-way 8 bit integer  32bit bit-wise (logical only) Static and Dynamic flow control JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 68: Sgx540 - Performance

    Location: AHB bus   Input format  Separate frame: YUV /YCbCr (4:2:0)  Packaged data: RGB888, RGB565, RGB555, NV12, NV21,TileYUV  Output data format JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 69: Registers Descriptions

    Descript chain‘s base address WDOG_CNT 0xF018 Watch dog‘s counter LAY_GCTRL 0xE000 Destination layers global control DST_BASE 0xE004 Destination picture‘s base address DST_CTRL_STR 0xE008 Destination picture‘s stride JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 70 Resize Coefficients( h-resize-coefficient and v-resize coefficient) LAY2_BK_ARGB 0x2024 Background aRGB Chanel 3 LAY3_CTRL 0x3000 Source format control register LAY3_Y_ADDR 0x3004 Source Y (or RGB) base address JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 71 (must) WDOG_EN Watch dog enable. 1: enable; 0: disable DST_TLB_EN Destination TLB enable. 1: enable; 0: disable IRQ_EN Interrupt enable 1:enable; 0:disable JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 72 IRQ_CLR Clean the interrupt flag Reset X2D but register STOP Stop X2D immediately. 1: stop START Start X2D. 1: start 4.2.2.4 TLB address register JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 73 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:0 WDOG_CNT Watch dog counter 4.2.2.7 Destination Layers global control JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 74 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:24 Alpha Destination global alpha value JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 75 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:0 ARGB The value of the pixel when destination layer is masker JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 76 0: source over 4: destination over 5: source in 6: destination in 7: source out 8: destination out 9: source atop A: destination atop JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 77 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 78 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 79 Name Description 31:16 OUT_FM_H The width of the output destination frame (Unit: pixel). 15:0 OUT_FM_W The height of the output destination frame (Unit: pixel). JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 80 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 81: Software Stack

    // RSZ = ( uint16_t )((m/n)*512), m raw size, n: result size Uint16_t lay_verit_rsz_coef; // Current layer‘s vertical resize coefficient Uint32_t lay_bk_argb; // Current layer‘s background color or common alpha when layer mask enable JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 82: Section 3 Display/Camera/Audio

    DISPLAY/CAMERA/AUDIO Section 3 DISPLAY/CAMERA/AUDIO JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 83: Lcd Controller

    Supports one transparency for each pixel in one graphic  Supports color key and mask color key  Supports porter-duff blending  Image Enhancement JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 84: Pin Description

    Programmable special pin for generating control signals NOTE: The mode and timing of special pin Lcd_spl, Lcd_cls, Lcd_ps and Lcd_rev can be seen in part 5.7 LCD Controller Pin Mapping. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 85: Block Diagram

    DMA Arbiter DMA0 DMA1 Input Input FIFO 1 FIFO 1 SER0 SER1 Output FIFO Image Enhancement LCD/LCM Figure 5-1 Block Diagram when use OSD mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 86: Figure 5-2 Block Diagram Of Tft Mode (Not Use Osd)

    Figure 5-2 Block Diagram of TFT mode (not use OSD) DMA0 DMA1 Input Input FIFO 1 FIFO 1 SER0 SER1 Output FIFO Image Enhancement HDMI Controller Figure 5-3 Block Diagram of HDMI interface JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 87: Lcd Display Timing

    All timing parameters start with ―V‖ is measured in lcd_hsync ticks. This diagram describes the general LCD panel parameters, these can be set via the registers that describes in next section. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 88: Osd Graphic

    Color Key mode is meant to mask a chosen color and show others. Mask Color Key mode is meant to only show a chosen color and mask others. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 89 Smart LCD Controller Not use color key function Color key mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 90: Register Description

    LCDBGC1 0x00000000 0x02C4 LCDKEY0 0x00000000 0x0110 LCDKEY1 0x00000000 0x0114 LCDALPHA 0x00 0x0118 LCDIPUR 0x00000000 0x011C LCDRGBC 0x0000 0x0090 LCDVAT 0x00000000 0x000C LCDDAH 0x00000000 0x0010 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 91 0x0404 LCDENH_LUMACFG 0x00000000 0x0408 LCDENH_CHROCFG0 0x00000000 0x040C LCDENH_CHROCFG1 0x00000000 0x0410 LCDENH_DITHERCFG 0x00000000 0x0414 LCDENH_STATUS 0x00000000 0x0418 0x00000000 0x0800~ LCDENH_GAMMA 0x0FFF 0x00000000 0x1000~ LCDENH_VEE 0x17FF JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 92: Configure Register (Lcdcfg)

    V-Sync and H-Sync direction. 0: output; 1: input. PS pin reset state. CLSP CLS pin reset state. SPLP SPL pin reset state. REVP REV pin reset state. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 93 D [17:0] The direction of PIN25 is set by register LPCDR.LCS in CPM SPEC. The direction of PIN23 and PIN23 are set by register LCDCFG.SYNDIR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 94: Control Register (Lcdctrl)

    Disable controller indicate bit. 0: enable; 1: in disabling or disabled. Enable controller. 0: disable; 1: enable. BPP0 Bits Per Pixel of foreground0. Bits Per Pixel 1bpp 2bpp JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 95: Status Register (Lcdstate)

    PREMULTI1 Premulti enable of foreground1 : 0 : data has been premultied and don‘t need premulti 1 : data should be premultied by lcd JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 96 OSDEN OSD mod enable. 1: enabled. And you can use F0 F1 0: disabled Set this bit to 1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 97: Osd Control Register (Lcdosdctrl)

    SOF0 Start of frame flag for foreground 0. EOF0 End of frame flag for foreground 0. Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 98: Background0 Color Register (Lcdbgc0)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 99: Foreground Color Key Register 1 (Lcdkey1)

    ALPHA1 The alpha value of foreground1 for one graphic with one transparency. ALPHA0 The alpha value of foreground0 for one graphic with one transparency. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 100: Ipu Restart (Lcdipur)

    This signal only use when foreground1 work in IPU mode. Trigger IPU transfer the last frame again to avoid output FIFO under run. HSYN VSYN frame front proch 5.6.13 RGB Control (LCDRGBC) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 101 RGB mode Reserved Reserved Reserved Writing has no effect, read as zero. EvenRGB Even line serial RGB data arrangement, useful for RGB serial mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 102: Virtual Area Setting (Lcdvat)

    Horizontal display area start. (in dot clock) 15:12 Reserved Writing has no effect, read as zero. 11:0 Horizontal display area end. (in dot clock) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 103: Display Area Vertical Start/End Point (Lcddav)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:28 Reserved Writing has no effect, read as zero. 27:16 YPOS The Y position of top-left part for foreground 1. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 104: Foreground 0 Size Register (Lcdsize0)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 105: Horizontal Synchronize Register (Lcdhsync)

    Writing has no effect, read as zero. 11:0 PS signal end position. (in dot clock) In STN mode, PSE defines N, which described in PSS. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 106: Cls Signal Setting (Lcdcls)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 107: Interrupt Id Register (Lcdiid)

    NOTE: If only one frame buffer is used in external memory, the LCDDAx field (word [0] of the frame descriptor) must point back to itself. That is to say, the value of LCDDAx is the physical JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 108: Source Address Registers (Lcdsa)

    The particular use of this field is up to the software. This ID register is copied to the LCD Controller Interrupt ID Register when an interrupt occurs. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 109: Dma Command Registers (Lcdcmdx)

    1: The data is command 0: The data is data Keep this bit to 0. COMPE It indicate this frm is 16/24 bpp compressed or not. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 110: Dma Offsize Registers (Lcdoffsx)

    *When you use 16x16block mode, you must use this to indicate how many word between each of block 5.6.33 DMA Page Width Registers (LCDPWx) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 111: Dma Commend Counter Registers (Lcdcnumx)

    Commands‘ number in this frame transfer by DMA. (only use in CNUM0,1 Smart LCD mode) 5.6.35 DMA Commend Counter Registers (LCDCPOSx) When LCDCMD.CMD = 0, is use as LCDPOS0, 1. 0x13050068, 0x13050078 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 112: Foreground X Size In Descriptor (Lcddessizex)

    5.6.36 Foreground x Size in Descriptor (LCDDESSIZEx) When LCDCMD.CMD = 0, 0x1305006C, 0x1305007C is use as LCDDESSIZE0, 1, to indicator the next frame foreground0, 1‘s size. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 113: Priority Level Threshold Configure Register (Lcdpcfg)

    Lcd priority mode. 0: use lcd dynamitic priority level; 1: use arbiter priority level. 30:28 HP_BST Highest priority Burst Length Selection. Burst Length 4 word JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 114: Dual Lcdc Channel Control(Lcdcdualctrl)

    1:fix the priority of lcdc0/1 in lcd internal arbiter; 0: use priority of lcdc0/1 generated by lcd in lcd internal arbiter Pri_lcd Set lcdc0/1 priority, just active when pri_lcd_en is 1 5.6.39 Image Enhancement CFG (LCDENH_CFG) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 115: Color Space Conversion Cfg (Lcdenh_Csccfg)

    0 0 0 0 0 0 0 0 0 0 0 Bits Name Description YCC2 00 : 601WIDE; 01 : 601NARROW; RGBM 10 : 709WIDE; 11 : 709NARROW JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 116: Luma Cfg (Lcdenh_Lumacfg)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 117: Chroma0 Cfg (Lcdenh_Chrocfg0)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 118: Enhance Status (Lcdenh_Status)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 119: Vee Cfg (Lcdenh_Vee)

    GSRT VSYNC VSYNC Slcd_cs Lcd_hsync/ HSYNC HSYNC GPCK HSYNC HSYNC Slcd_rs Lcd_de Lcd_ps Pulse Toggle Toggle Lcd_cls Pulse Pulse Pulse Lcd_rev Toggle Toggle Toggle JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 120 24 bit Parallel mode2 Lcd_pclk/ Slcd_clk Lcd_vsync/Sl VSYNC VSYNC cd_cs Lcd_hsync/Sl HSYNC HSYNC cd_rs Lcd_de Lcd_ps Lcd_cls Lcd_rev Lcd_spl Lcd_dat17 Lcd_dat16 Lcd_dat15 Lcd_dat14 Lcd_dat13 Lcd_dat12 Lcd_dat11 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 121: Data Mapping To Gpio Function

    Lcd_dat9/Slcd_dat9 lcd_g5 Lcd_dat8/Slcd_dat8 lcd_g4 Lcd_dat7/Slcd_dat7 lcd_g3 Lcd_dat6/Slcd_dat6 lcd_g2 Lcd_dat5/Slcd_dat5 lcd_b7 Lcd_dat4/Slcd_dat4 lcd_b6 Lcd_dat3/Slcd_dat3 lcd_b5 Lcd_dat2/Slcd_dat2 lcd_b4 Lcd_dat1/Slcd_dat1 lcd_b3 Lcd_dat0/Slcd_dat0 lcd_b2 Lcd_lo6_o[5] lcd_r1 Lcd_lo6_o[4] lcd_r0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 122: Display Timing

    Vsync n Display lines Hsync Data 1 Line Hsync m Clocks PCLK Data 16-bit/18-bit DATA Figure 5-6 General 16-bit and 18-bit TFT LCD Timing JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 123: 8-Bit Serial Tft Timing

    The Figures show the two modes as follows: (The toggle mode of signal ―SPL‖ is different with the others signal. ―SPL‖ does toggle after display line.) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 124: Figure 5-8 Special Tft Lcd Timing 1

    When LCDC is enabled ,there will be a null line to be add before transferring data to LCD panel. So the toggle mode exept SPL signal of special 3 TFT mode is when reset level is high,the first valid edge will JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 125: Delta Rgb Panel Timing

    Figure 5-10 Delta RGB timing 5.8.5 RGB Dummy mode timing This section shows the RGB Dummy diagram, the polarity of signal ―Vsync‖, ―Hsync‖, and ―PCLK‖ can be programmed. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 126: Format Of Frame Buffer

    1 Line Hsync 4*m Clocks PCLK Data *Dummy = 0 Figure 5-11 RGB Dummy timing 5.9 Format of Frame Buffer 5.9.1 16bpp 5.9.2 18bpp JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 127: 24Bpp

    Smart LCD Controller 5.9.3 24bpp 5.9.4 16bpp with alpha 5.9.5 18bpp with alpha 5.9.6 24bpp with alpha 5.9.7 24bpp compressed BLUE 1 [7:0] RED 0 [7:0] JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 128: Format Of Data Pin Utilization

    5.10 Format of Data Pin Utilization 5.10.1 18-bit Parallel TFT Col0 (RGB) 5.10.2 16-bit Parallel TFT Col0 (RGB) 5.10.3 8-bit Serial TFT (24bpp) Col0 (R) Col0 (G) Col0 (B) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 129: Lcd Controller Operation

    Disable Done bit, LCDSTATE.LDD, is set when the LCD controller finishes displaying the last frame, and the enable bit, LCDCTRL.ENA, is cleared automatically by hardware. LCDCTRL.DIS must be set zero when enabling the controller. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 130: Resetting The Controller

    CCIR656: need external encoder, or software designer need give digital blanking data and timing reference signal in data buffer. 5.11.7 OSD Operation Normal process. Configuration. * LCDRGBC and LCDIPUR JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 131: Descriptor Operation

    5.11.8 Descriptor Operation TFT panel you can use only one descriptor or several connected descriptor. As which shown below. FRM0 FRM1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 132: Ipu Direct Connect Mode

    Open all channel of DAC. (refer to TVEDAC spec) Set TVEN to 0. Disable LCD panel pins (except HSYNC/VSYNC) for save power. (refer to GPIO spec) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 133: Smart Lcd Controller

    *Please notice that the command only can transfer by DMA channel 0. No matter the DMA channel 1 or IPU are use or not. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 134: Pin Description

    MCFG SLCD Configure Register 0x0000 0x130500A0 MCTRL SLCD Control Register 0x00 0x130500A4 MSTATE SLCD Status Register 0x00 0x130500A8 MDATA SLCD Data Register 0x00000000 0x130500AC JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 135: Slcd Configure Register (Mcfg)

    1: Active Level is High RSPLY RS Polarity. 0: Command RS = 0, Data RS = 1 1: Command RS = 1, Data RS = 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 136: Slcd Control Register (Mctrl)

    Description Reserved Writing has no effect, read as zero. DMAMODE SLCD descriptor DMA mode select. 0: DMA will continually transfer data follow descriptor chain JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 137: Slcd Status Register (Mstate)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description The RS bit of data register is used to decide the meanings of the low 24-bit. 0: data 1: command JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 138: System Memory Format

    *Please notice that when you use this kind command, set CWIDTH as 8bit once and set the LCDCNUM.CNUM as doubled the real command number. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 139: Transfer Mode

    Because DMA transfer mode only can work in OSD mode, you need to configure the panel according OSD mode: Configuration. * LCDRGBC and LCDIPUR Set Color. LCDBGC, LCDKEY0, LCDKEY1, LCDALHPA Set Display. * LCDVAT, LCDDAH, LCDDAV * LCDVSYNC, LCDHSYNC JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 140: Register Transfer Mode

    RS [31] = 0 XXX [30:9] Data [8:0] RS [31] = 0 XXX [30:8] Data [7:0] 6.7 Timing 6.7.1 Parallel Timing LCD_CLK DATA Command Data JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 141: Serial Timing

    *please notice that use and only use DMA0 to transfer command no matter use DMA0 to transfer frame data or not. One recommend descriptor chain (CMD0 with CNUM>0 and CMD1 with CNUM=0): CMD0 CMD1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 142: Register Operation

    Set MCFG to configure SLCD. Wait for MSTATE.BUSY == 0. Set MDATA register. Wait for MSTATE.BUSY == 0. Set MDATA register. Wait for MSTATE.BUSY == 0. … … JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 143: Decompresser

    *In the case of compressed without alpha bpp24, there is just start command , no sequent command and last command, the length is the high 8bits of every data. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 144 The third line contains 3 repeated pixels , 2 non-repeated pixels, and 2 repeated pixels; The last line contains 2 repeated pixels , 2 non-repeated pixels, and 3 repeated pixels. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 145: Operation Guide

    LCDOFFSx should be set to how many word in per line of frame buffer for compressed frame, count in word, 64-word align or 16-word align(depend on the configuration of aosd_comp). JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 146: Image Enhancement

    1. Read corresponding bit in LCDENH_STATUS. If it‘s 1 then continue, otherwise disable corresponding function and wait it change to 1. 2. Configure corresponding registers. 3. Enable corresponding founction. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 147: Image Process Unit

    Up scaling ratios up to 1:31 in fractional steps with 1/32 accuracy  Down scaling ratios up to 31:1 in fractional steps with 1/32 accuracy *For more details, refer to Special Instruction. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 148: Block

    9.4.33 detail). There are 2 tables to support independent horizontal and vertical scaling. Each table has 32 entries that can accommodate up to 32 coefficient-groups. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 149: Registers Descriptions

    Base address of the destination‘s physical address map table DEST_TLB_ADDR_N 0x98 for next frame PIC_ENC_TABLE 0x400 Picture enhance table stone. ~0X7FF REG_EN_MSK 0x70 Register enable indicator TRIG 0x74 Ipu trigger register JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 150: Ipu Global Control Register

    Global alpha Reserved Writing has no effect, read as zero. OSD_PM IPU layer has been pre-multiply 0: without 1: has pre-multiply OSD_MOD Osd mode selector: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 151: Ipu Frame Control Register

    1: use the page mapping LCDC_SEL Output data destination choose. 0: output to external memory 1: output to LCDC FIFO SPKG_SEL Input data case choose. 0: Separated Frame JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 152: Ipu Status Register

    IPU_STATUS and clean end flag. When the IPU_CONTROL.FM_LCDC_SEL has been set 1, and the IPU has finished one JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 153: Ipu Trigger Register

    VRC_RY Vertical resize coefficient ready. HRC_RY Horizontal resize coefficient ready. RCT_RY RSZ_COEF_INDEX ready. CSCC_RY CSC_C0(1,2,3)_COEF CSC_OFSET_PARA ready. DSTR_RY New destination stride (OUT_STRIDE) ready. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 154: Data Format Register

    Output data packaged offset. (only used in RGB out OUT_FMT != 011) [31:0] 000: RGB 001: RBG 010: GBR 011: GRB 100: BRG 101: BGR JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 155: Input Y Data Address Register

    When the source frame is packed YUV444, the data format about a pixel should be as following: 24 23 16 15 9.4.8 Input Y Data Address Register JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 156: Input U Data Address Register

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 157: Input Source Tlb Base Address

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description The destination frame‘s TLB base address. (This register will 31:0 DEST_TLB_ ADDR work when the IPU_CONTROL.DPAGE_MAP==1) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 158: Input Y Data Address Of Next Frame Register

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 159: Source Tlb Base Address Of Next Frame

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description The TLB base address about the next frame‘s data that will be 31:0 DEST_TLB_AD DR_N DMA out. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 160: Address Mapping

    The height of the input frame (unit: byte). Y data width is same as this value while U/V or Cb/Cr data width should do relatively zoom in according to the source data format. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 161: Input Y Data Line Stride Register

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 162: Output Data Address Of Next Frame Register

    Writing has no effect, read as zero. 27:16 YOFT Vertical offset 15:12 Reserved Writing has no effect, read as zero. 11:0 XOFT Horizon offset JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 163: Output Geometric Size Register

    31:16 Reserved Writing has no effect, read as zero. 15:0 OUT_S The line stride of the destination data buffer in the external memory(Unit: byte). JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 164: Csc C0 Coefficient Register

    NOTE: R = C0*(Y – LUMA_OF) + C1*(Cr-CHROM_OF) G = C0*(Y – LUMA_OF) – C2*(Cb-CHROM_OF) – C3*(Cr-CHROM_OF) B = C0*(Y – LUMA_OF) + C4*(Cb-CHROM_OF) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 165: Csc C2 Coefficient Register

    R = C0*(Y – LUMA_OF) + C1*(Cr-CHROM_OF) G = C0*(Y – LUMA_OF) – C2*(Cb-CHROM_OF) – C3*(Cr-CHROM_OF) B = C0*(Y – LUMA_OF) + C4*(Cb-CHROM_OF) 9.4.31 CSC C4 Coefficient Register JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 166: Resize Coefficients Table Index Register

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 167 = 1 – ( (t*n+1)/m – [t*n/m]); t++;} else { W W_COEF = [512 * W ] (stands for get the rounding integer, [20.33] = 20 while [20.66] = JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 168 W2 = 512*SinXDivX(1-Wk) W3 = 512*SinXDivX(2-Wk) Step 3: And then the zooming weight coefficient should set to IPU as following: Prepare: Set H_CONF to 1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 169 = 0; int hcoef_real_heiht = 0 ; int vcoef_real_heiht = 0 ; int coef_tmp = 0 ; j = -1 ; for (i=0; i<=H_MAX_LUT+1; i++) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 170 = sinxdivx_table_8[(1<<9)+u_8]; cube_hcoef_table[i][1] = sinxdivx_table_8[u_8]; cube_hcoef_table[i][2] = sinxdivx_table_8[(1<<9)-u_8]; cube_hcoef_table[i][3] = sinxdivx_table_8[(2<<9)-u_8]; for (cnt =0 ; cnt<hcoef_real_heiht ; cnt ++) HRSZ_COEF_LUT_bicube[cnt] = (cube_hcoef_table[cnt], hoft_table[cnt]); JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 171: Vertical Resize Coefficients Look Up Table Register Group

    P [1] * 1/5 + P [2] * 4/5 P [2] P [3] P [2] * 3/5 + P [3] * 2/5 9.4.34 Vertical Resize Coefficients Look Up Table Register group JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 172: Calculation For Resized Width And Height

    If [(IW - 1) * (m/n)] * (n/m) ==(IW-1) then OW = [(IW - 1) * (m/n)] + 1; Else OW = [(IW - 1) * (m/n)] + 2; JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 173: Csc Offset Parameter Register

    Luma offset value. NOTE: R = C0*(Y – LUMA_OF) + C1*(Cr-CHROM_OF) G = C0*(Y – LUMA_OF) – C2*(Cb-CHROM_OF)– C3*(Cr-CHROM_OF) B = C0*(Y – LUMA_OF) + C4*(Cb-CHROM_OF) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 174: Ipu Operation Flow

    1, users need to set corresponding address ready high IPU_REG_CTRL) Just need change address and the address set mode is 1 Clean end flag Run ipu Other operation JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 175: Data Out To Lcdc

    Clean end flag set mode is 1 Run ipu Other operation Need stop IPU to Close led LCD mode Polling end flag of IPU JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 176: Operation Example

    (i=0;i<H_MAX_LUT;i++) { set_hrsz_lut_coef(h_lut[i].coef, h_lut[i].in_n, h_lut[i].out_n); start_vlut_coef_write(); NOTE: This step is necessary before write new LUT. for (i=0;i<V_MAX_LUT;i++) { set_vrsz_lut_coef(v_lut[i].coef, v_lut[i].in_n, v_lut[i].out_n); Clean_end_flag(); run_ipu(); JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 177: Table 9-3 Mapping Mode

    NOTE: this step is necessary when ipu address set mode is 1. set_csc_c0(YUV_CSC_C0); set_csc_c1(YUV_CSC_C1); set_csc_c2(YUV_CSC_C2); set_csc_c3(YUV_CSC_C3); set_csc_c4(YUV_CSC_C4); set_csc_ofset_para ( 128, 0 ) ; set_rsz_lut_end(H_MAX_LUT-1, V_MAX_LUT-1); start_hlut_coef_write(); NOTE: This step is necessary before write new LUT. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 178: Special Instruction

    D_FMT. IN_OFT (IPU_CONTROL. SPKG_SEL == 1) D_FMT.OUT_FMT = 2‘b00, 2‘b01, 2‘b10 D_FMT.RGB_OUT_OFT. CSC_C0 (1,2,3,4)_COEF, CSC_OFSET_PARA YUV (package) IPU_CONTROL.CSC_EN =0 IPU_CONTROL. SPKG_SEL D_FMT. IN_FMT D_FMT. IN_OFT (IPU_CONTROL. SPKG_SEL == 1) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 179: Yuv/Ycbcr To Rgb Csc Equations

    9.6.4 Output data package format (RGB order) Format Package Bit-31 29 20 19 10 9 RGBAAA EMPTY Bit-31 24 23 16 15 EMPTY RGB888 Bit-31 24 23 16 15 EMPTY JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 180: Input Data Package Format (Rgb Order)

    V Frame start Address, Line 0 start … V Frame end -- V (58, 39) Out data V (58,39) V (57,39) V (56,39) … JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 181 Destination data (RGB) storing format in external memory is similar with above figure, but RGB555 and RGB565 frame‘s every line start address can be half-word aligned. (RGB888 frame still need word aligned) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 182: Lvds Controller

    LVDS Transmitter‘s TXECTRL 0x00000030 0x130A03CC Enhance Control Register 10.2.1 TXCTRL (LVDS Transmitter Control Register) The register TXCTRL is used to control LVDS to work. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 183 0: LVDS output; 1: CMOS RGB output. 10:8 TX_DLY_SEL Input clock edge delay control, for setup/hold time fine tuning. TX_AMP_ADJ LVDS output swing control. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 184: Txpll0 (Lvds Transmitter's Pll Control Register 0)

    Writing has no effect, read as zero. 14:8 PLL_PLLN[6:0] PLL feedback divider value configure. PLL_TEST_DIV Output divider ratio control in test mode. 00: 1/2 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 185: Txpll1 (Lvds Transmitter's Pll Control Register 0)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Bits Name Description 31:11 Reserved Writing has no effect, read as zero. 10:9 TX_EM_S Emphasis level configure JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 186: Operate Description

    Note: When in power down mode, the LVDS output is Hi-Z state, and PLL_LOCK=0. 10.3.2 LVDS Output Amplitude Control Table 10-3 LVDS Output Amplitude Control TX_AMP_ADJ TX_LVDS Output Voltage 200mV 350mV controlled by TX_CR[2:0] and TX_CR_CK JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 187: Lvds Input Clock Edge-Delay Control

    CMOS(RGB Data) LVDS (LVDS Data) HI-Z 10.3.3 LVDS Input Clock Edge-Delay Control Table 10-6 LVDS_TX Clock Edge Delay Control TX_DLY_SEL[2] TX_DLY_SEL[1] TX_DLY_SEL[0] Edge Delay (ns) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 188: Output Data Start-Edge Control

    The feedback divider value range is 8 to 260. = (F ) * N , The F Frequency should be between 150MHz to 1GHz. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 189: Vco Gain Calibration

    Table 10-11 PLL Post Divider Configuration Post Divider Setting Post Divider Value (N (POST_DIVA[1:0]) 4 (Attention, not 3) 3 (Attention, not 4) 10.3.9 LVDS-LCDC RGB Data Mapping JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 190: Lvds Vesa/Jeida Mode

    -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- 10.3.10 LVDS VESA/JEIDA Mode VESA Mode LVDS output timing like following figure. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 191: Operate Flow

    When BG_PWD set to 1, The LVDS will enter the full power down mode for minimum power consumption JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 192: Lvds Output Mode

    10.4.3 RGB CMOS Output Mode If you wants LVDS output RGB data at CMOS voltage, please Set the LVDS registers follow 10.3.1 table 10-3. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 193: Camera Interface Module

    CIM_PCLK Pixel clock from Image Sensor CIM_VSYNC Vertical synchronous from Image Sensor CIM_HSYNC Horizontal synchronous from Image Sensor CIM_DATA[7:0] Data bus from Image Sensor JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 194: Cim Special Register

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 195 0: Data is sampled by PCLK rising edge 1: Data is sampled by PCLK falling edge 11:10 BURST_ DMA burst type. TYPE 00: INCR4 01: INCR8 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 196 Writing has no effect. Read as zero. Data sample mode. Please refer to the table below. Description 2‘b00 ITU656Progressive Mode 2‘b01 ITU656Interlace Mode 2‘b10 Gated Clock Mode 2‘b11 Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 197: Cim Control Register (Cimcr)

    Software reset enable. 0: Don‘t care 1: Reset the CIM module. DMA_EN Enable / disable the DMA function. 0: disable DMA; 1: enable DMA. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 198: Cim Control Register 2 (Cimcr2)

    1: Enable auto recovery. 21:20 Specified the horizontal ratio for down scale. 00: no scale 01: 1/2 down scale 10: 1/4 down scale 11: 1/8 down scale JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 199 0: Emergency Mode Disable 1: Emergency Mode Enable Auto Priority Mode Enable Control. 0: Auto priority mode disable. CIM uses the priority set by arbiter JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 200: Cim Status Register (Cimst)

    After reset, Y_RXFIFO is empty, and Y_RX_EMPTY is 1. 0: Y_RXFIFO is not empty 1: Y_RXFIFO is empty 15:12 Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 201 0: CIM has not been disabled. 1: CIM has been disabled. Can generate an interrupt if CIMIMR.VDDM is 0. Write 0 to this bit to clear. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 202: Cim Interrupt Mask Register (Cimimr)

    1: mask Reserved Read as zeros. VDDM The control bit to mask VDD interrupt. 0: enable 1: mask 11.2.7 CIM Interrupt ID Register (CIMIID) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 203: Cim Descriptor Address (Cimda)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 204: Cim Frame Id Register (Cimfid)

    When one frame uses several buffers, it is suggested to set SOFINTEn of first buffer only. EOFINTEn Interrupt enable for DMA ending a frame-buffer transfer. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 205: Cim Window Size (Cimwsize)

    When output data format is YCBCR4:4:4, it must be multiple of 4.  When output data format is YCBCR4:2:2, it must be multiple of 8. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 206: Cim Window Offset (Cimwoffset)

    11: One pixel includes 4 bytes. Reserved Writing has no effect, read as zero. 12:0 Horizontal size of the frame. N indicates the horizontal includes (n+1) pixels. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 207: Cim Y Frame Buffer Address Register (Cimyfa)

    When one frame uses several buffers, it is suggested to set EOFINTEn of last buffer only. EEOFINTEn Interrupt enable for DMA issuing an earlier eof interrupt. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 208: Cim Cb Frame Buffer Address Register (Cimcbfa)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 209: Cim Cr Frame Buffer Address Register (Cimcrfa)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 210: Cim Tlb Control Register (Cimtc)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:3 Reserved Read as zeros. Index It will be used with CIMCNT together. This field will be used to JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 211: Cim Tlb Content Register (Cimtcnt)

    CIM_DATA Gated Clock Mode ITU656 Interlace Mode ITU656 Progressive Mode 11.3.1 Gated Clock Mode CIM_VSYNC, CIM_HSYNC, and CIM_PCLK signals are used in this mode. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 212: Itu656 Interlace Mode

    (F=0) FIELD 1 ACTIVE VIDEO LINE311 LINE31 BLANKING (V=1) LINE336 FIELD2 FIELD 2 (V=0) (F=1) ACTIVE VIDEO EVEN LINE624 BLANKING (V=1) LINE62 LINE625 (V=1) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 213: Itu656 Progressive Mode

    VSYNC mode. CIM supports both internal and external VSYNC modes. ITU656Progressive Mode is a kind of Non-Interlace Mode. The image data are encoded within only one field. Most sensors support ITU656Progressive Mode. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 214: Dma Descriptors

    [1] contains the value for CIMFID word [2] contains the physical address for CIMYFA word [3] contains the value for CIMYCMD word [4] contains the physical address for CIMCBFA JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 215: Interrupt Generation

    When disable the module by clearing the CIMCR.ENA, the module should be disabled after transferring current valid data. Then set the CIMST.VDD bit, at the same time, if VDDM is set, VDD interrupt is generated. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 216: Software Operation

    Step 1. Configure descriptor with STOP = 1. Step 2. Wait DMA_STOP interrupt, then write 0 to CIMCTRL.ENA. Step 3. Clear state register: write 0 to register CIMSTATE. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 217: Ac97/I2S/Spdif Controller

    (Dolby Digital, DTS, etc.). This chapter describes the programming model for the AIC. The information in this chapter requires an understanding of the AC‘97 specification, Revision 2.3. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 218: Block Diagram

    8, 16, 18, 20 and 24 bit audio sample data sizes supported, 16 bits packed sample data is supported  Up to 8 channels sample data supported JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 219: Interface Diagram

    BIT_CLK Audio bit clock output SYNC Frame SYNC signal input RESET# Reset (low active) input Figure 12-2 Interface to an External AC’97 CODEC Diagram JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 220: Figure 12-3 Interface To An External Master Mode I2S/Msb-Justified Codec Diagram

    SYNC Left/right words select input  SYS_CLK Master/system clock input Figure 12-5 Interface to an External Slave Mode I2S/MSB-Justified CODEC Diagram (Share Clock Mode) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 221: Figure 12-6 Interface To An External Slave Mode I2S Codec Diagram

    Figure 12-7 Interface to a HDMI Transmitter via I2S Diagram Jz47xx HDMI Transmitter SDATA_OUT Serial audio data input 0 Figure 12-8 Interface to a HDMI Transmitter via SPDIF Diagram JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 222: Signal Descriptions

    SYNC Indicates the left- or right-channel for I2S/MSB-Justified format. SDATA_OUT SDATO Serial audio output data to CODEC / I2S line 0 / SPDIF output. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 223 SDATA_OUT is AIC output data pin, which outputs AC97/I2S serial audio data, SPDIF serial data or data of AC97 CODEC register control to an external audio CODEC device. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 224: Register Descriptions

    AIC I2S/MSB-justified Status I2SSR 0x00000000 0x1002001C Register AIC AC97 CODEC Command ACCAR 0x00000000 0x10020020 Address Register ACCDR AIC AC97 CODEC Command Data 0x00000000 0x10020024 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 225 12 AICDR is act as data input/output port to/from transmit/receive FIFO when write/read. 13 CKCFG, RGADW and RGDATA are used to access internal CODEC, please refer to CODEC Spec. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 226: Aic Configuration Register (Aicfr)

    I2S/MSB-justified format. When AC-link format is selected, ISYNC is always output and this bit is ignored. Change this bit in case of IBIT_CLK is stopped (I2SCR.ISTPBK = 1). JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 227 BIT_CLK is stopped (I2SCR.STPBK = 1). BCKD BIT_CLK Direction BIT_CLK is input from an external source. BIT_CLK is generated internally and driven out to JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 228: Table 12-3 Aic I2S Mode Configurations

    CODEC share clock I2S/MSB-justified slave mode. External CODEC share clock I2S/MSB-justified master mode. AIC roles the master with external serial clock source I2S/MSB-justified interface. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 229: Aic Common Control Register (Aiccr)

    Output Sample Size. These bits reflect output sample data size from memory or register. The data sizes supported are: 8, 16, 18, 20 and 24 bits. The sample data is LSB-justified in memory/register. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 230 Endian Switch. This bit control endian change on outgoing 16-bits size audio sample by swapping high and low bytes in the sample data. ENDSW Description No change on outgoing sample JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 231 AIC, which is used for test only. When the AIC loop back function is enabled, normal audio replay/record functions are disabled. ENLBF Description AIC Loop Back Function is Disabled. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 232: Aic Ac-Link Control Register 1 (Accr1)

    Setting the corresponding bit indicates to AIC to take an audio sample from transmit FIFO to fill the respective slot. And it indicates to JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 233: Aic Ac-Link Control Register 2 (Accr2)

    0 for low, 1 for high; otherwise, it is ignored. RESET# pin level. When AC-link is selected, this bit is used to drive the RESET# pin. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 234: Aic I2S/Msb-Justified Control Register (I2Scr)

    The frame is LR like or RL like. It takes effective immediately when the bit is changed. Change this before replay started. RFIRST Description Send L channel first. (LR) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 235: Aic Controller Fifo Status Register (Aicsr)

    12.2.6 AIC Controller FIFO Status Register (AICSR) AICSR contains bits to reflect FIFOs status. Most of the bits are read-only except two, which can be JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 236 FIFO threshold, which is controlled by AICFR.RFTH. When RFS is 1, it may trigger interrupt or DMA request depends on the interrupt enable and DMA setting. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 237: Aic Ac-Link Status Register (Acsr)

    External CODEC Low Power Mode. This bit indicates the external CODEC is switched to low power mode or BIT_CLK is active from CODEC after wake up. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 238: Aic I2S/Msb-Justified Status Register (I2Ssr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 239: Aic Ac97 Codec Command Address & Data Register (Accar, Accdr)

    Command Address Register. This is used to hold 20-bit AC ‘97 CODEC 19:0 register address transmitted in SDATA_OUT slot 1. After this field is JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 240: Aic Ac97 Codec Status Address & Data Register (Acsar, Acsdr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 241: Aic I2S/Msb-Justified Clock Divider Register (I2Sdiv)

    AICDR is act as data input port to transmit FIFO when write and data output port from receive FIFO when read, one audio sample every time. The FIFO width is 24 bits. Audio sample with size N that is JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 242: Spdif Enable Register (Spena)

    0: SPDIF transmitter is disabled 1: SPDIF transmitter is enabled 12.2.14 SPDIF Control Register (SPCTRL) The register SPCTRL is used to control SPDIF to work. SPCTRL 0x10020084 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 243 Writing has no effect, read as zero. M_TRIG Trigger interrupt mask. 0: Enabled 1: Masked M_FFUR FIFO underrun interrupt mask. 0: Enabled 1: Masked JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 244: Spdif State Register (Spstate)

    Writing has no effect, read as zero. INIT_LVL Initial level set bit. 0: SPDIF initial level is low 1: SPDIF initial level is high JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 245: Spdif Configure 2 Register (Spcfg2)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:30 Reserved Writing has no effect, read as zero. 29:26 Sampling frequency. 0000:44.1kHz 0010:48kHz 0011:32kHz 1010:96kHz 1110:192kHz Others: Reference IEC60958-3 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 246 Pre-emphasis set bit. 0: None 1: 15us/15us COPY_N Copyright set bit. 0: Copyright is asserted 1: Copyright is not asserted AUDIO_N Linear PCM identification bit. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 247: Spdif Fifo Register (Spfifo)

    Slot 0 Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Slot 11 Slot 12 Or SDATA_IN Data Phases Phase Figure 12-10 AC-link audio frame format JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 248: I2S And Msb-Justified Serial Audio Format

    … 28 29 30 31 32 33 34 35 … 60 61 62 63 Cycle No. BIT_CLK SDATA_OUT Or SDATA_IN SYNC Left Right Figure 12-13 I2S data format (A: LR mode) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 249: Figure 12-14 I2S Data Format (B: Rl Mode)

    In the C: LR mode, first send the left channel in a stereo frame. One Left slot and one Right slot make a sample frame. It is the normal mode in MSB-justified. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 250: Audio Sample Data Placement In Sdata_In/Sdata_Out

    The placement of audio sample in incoming/outgoing serial data stream for all formats support in AIC is MSB (Most Significant Bit) justified. Suppose n bit sample composed by … Following table described the how sample data bits are transferred. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 251: Table 12-4 Sample Data Bit Relate To Sdata_In/Sdata_Out Bit

    If in 16 bits packed mode, the data transferred is the same as the 16 bits normal mode as shown above. But there are two samples in one word. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 252: Spdif Protocol

    AIC controller FIFO data—An entry is placed into the transmit FIFO by writing to the I2S controller‘s Serial Audio Data register (AICDR). Writing to AICDR updates a transmit FIFO entry. Reading AICDR flushes out a receive FIFO entry. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 253: Initialization

    Enable AIC by write 1 to AICFR.ENB. If it needs to reset AIC registers and flush FIFOs, write 1 to AICFR.RST. If it need only flush JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 254: Ac '97 Codec Power Down

    RESET# is an asynchronous AC ‗97 CODEC input. rst_low rst2clk RESET# BIT_CLK Figure 12-20 Cold AC ’97 CODEC Reset Timing JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 255: External Codec Registers Access Operation

    CODEC. The ACSAR and ACSDR are used to receive a register‘s content from external AC‘97 CODEC. The register accessing request and the register‘s content returning is asynchronous. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 256: Audio Replay

    If two channels is configured, select the right-channel-first sample data or not (I2SCR.RFIRST). If two channels is configured, select the sample data switched or not (I2SCR.SWLH). JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 257: Audio Record

    Configure sample rate by clock dividers (for I2S/MSB-Justified format with BIT_CLK is provided internally) or by CODEC registers (for AC-link or BIT_CLK provided by external CODEC) or by CODEC memory mapped registers (for internal CODEC). JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 258: Fifos Operation

    Bit) in memory or processor registers. For transmitting, bits exceed sample are discarded. For receiving, these bits are set to 0. Figure 12-22 illustrates the FIFOs access. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 259: Figure 12-22 Transmitting/Receiving Fifo Access Via Apb Bus

    When AICFR.RFTH is too small, or AICFR.TFTH is too big, the DMA burst length or the number of sample can be processed by processor is too small, which JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 260: Data Flow Control

    When the interrupt found, it means there are rooms or samples in the TX or RX FIFO, and processor can store or load samples to or from the FIFO. Interrupt approach is more efficient than polling approach. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 261: Audio Samples Format

    …… bit0 bit31 …… bit0 0xXXXXX008 0xXXXXX004 0xXXXXX004 0xXXXXX000 0xXXXXX000 Figure 12-24 Four channels (Left) and Six channels (right) mode (16 bits packed mode) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 262: Figure 12-25 Eight Channels Mode (16 Bits Packed Mode)

    …… bit0 0xXXXXX00C 0xXXXXX014 0xXXXXX008 0xXXXXX010 0xXXXXX004 0xXXXXX00C 0xXXXXX000 0xXXXXX008 0xXXXXX004 0xXXXXX000 Figure 12-27 Four channels (Left) and Six channels (right) mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 263: Serial Audio Clocks And Sampling Frequencies

    But SYNC signal frequency is not fixed when using internal CODEC. BIT_CLK SYS_CLK is only for CODEC. It usually takes one of the two roles, as CODEC master clock input or as JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 264: Table 12-7 Audio Sampling Rate, Bit_Clk And Sys_Clk Frequencies

    AIC is used to divide SYS_CLK for it. Figure 12-29 SYS_CLK, BIT_CLK and SYNC generation scheme The setting of I2SDIV.DV is shown in following table. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 265: Table 12-8 Bit_Clk Divider Setting

    0.79 235.5 0.87 247.06 0.53 270.64 0.11 280.56 0.73 294.22 0.24 305.14 0.67 317.79 0.53 329.57 0.66 341.35 0.79 0.85 353.13 0.90 358.79 0.69 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 266: Table 12-10 Cpm/Aic Clock Divider Setting For Various Sampling Rate If Pll = 270.64Mhz

    0.59% 0.31% 170.67 0.79% 235.5 0.87% 247.2 0.59% 0.82% 0.35% 270.67 0.12% 271.2 0.32% 280.5 0.75% 284.4 0.81% 0.31% 305.14 0.67% 0.60% 329.45 0.70% JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 267: Interrupts

    Set SPCFG1 and SPCFG2 to configure SPDIF transmitter. Set SPCFG2.CON_PRO to 0 to choose consumer mode. Set SPCFG2. AUDIO_N to 0 to choose linear PCM audio data mode. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 268: Non-Pcm Mode Operation (Reference Iec61937)

    12.5.4 Disable operation Set SPENA.SPEN to 0 to disable SPDIF to transmitter. Wait SPSTATE.BUSY to be set to 0 by hardware. You can do other operation. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 269: Pcm Interface

    PCM Serial clock Line signal input/output PCMSYN Input/Output PCM sync signal input/output PCMDOUT Output PCM Serial data output PCMDIN Input PCM Serial data input JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 270: Block Diagram

    PCM Interrupt Control Register 0x00000000 0x1007100c PCMINTS0 PCM Interrupt Status Register 0x00000100 0x10071010 PCMDIV0 PCM Clock Divide Register 0x00000001 0x10071014 13.4.1 PCM Control Register (PCMCTL) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 271 0 to this bit has no effect and this bit is always reading 0. Reserved Writing has no effect, read as zero. CLKEN Enable the serial clock division logic. Must be HIGH for the PCM to operate. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 272: Pcm Configuration Register (Pcmcfg)

    0: MSB is captured on the falling edge of PCMCLK during the same cycle that PCMSYNC is high 1: MSB is captured on the falling edge of PCMCLK during the cycle JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 273: Pcm Fifo Data Port Register (Pcmdp)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 274: Pcm Interrupt Status Register (Pcmints)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bits Name Description 31:15 Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 275: Pcm Clock Divide Register (Pcmdiv)

    When write, clear itself. When read, indicates data has even been written to full receive FIFO. When write, not effects. 13.4.6 PCM CLOCK DIVIDE REGISTER (PCMDIV) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 276: Pcm Interface Timing

    13.5.1 Short Frame SYN PCMCLK PCMSYN Don't Care B15 PCMDOUT Don't Care B15 PCMDIN Figure 13-1 Short Frame SYN Timing (Shown with 16bit Sample) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 277: Long Frame Syn

    NOTE: Figure 13-3 shows a PCM transfer with the MSB configured one shift clock after the PCMSYN. PCMCLK PCMSYN Don't Care PCMDOUT Don't Care PCMDIN Figure 13-4 Long Frame SYN Timing (Shown with 16bit Sample) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 278: Multi-Slot Operation

    At power-on or other hardware reset (WDT and etc), PCM is disabled. Software must initiate PCM after power-on or reset. Initialize START Write the frequency divider to PCMDIV Configure PCMCFG Register Configure PCMINTC Register JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 279: Audio Replay

    Here is the audio record flow: Configure the external DEVICE as needed. Initialize PCM and configure the register. Write 1 to PCMCTL.PCMEN and PCMCTL.CLKEN. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 280: Fifos Operation

    APB Bus Write Access Read Access 8-bit 8-bit 16-bits 16-bits PCMDP.DATA (write) PCMDP.DATA (read) FIFO FIFO Figure 13-6 Transmitting/Receiving FIFO access via APB Bus JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 281: Data Flow Control

    DMA request to DMA controller. To respond the request, DMAC initiator and controls the data movement between memory and TX/RX FIFO. 13.6.6 PCM Serial Clocks and Sampling Frequencies JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 282: Interrupts

    Transmit FIFO Service (PCMINTS.TFS). It‘s also DMA Request.  Transmit Under-Run (PCMINTS.TUR).  Receive Over-Run (PCMINTS.ROR). For further details, see the corresponding register description sections. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 283: Internal Codec Interface

    TBD = parameter or document section to be defined later on TBC = parameter or document section subject to change TO BE COMPLETED = section to be filled or subject to change JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 284: Signal Descriptions

    Please refer to data sheet of the chip for details. DMIC_IN is ‗GPIO : PB18‘ , MIC_CLK is ‗GPIO : PB19‘. Please refer to GPIO specification for these pins operating. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 285: Block Diagram

    Off if SB or SB_SLEEP or SB_ADC; Enable ADC Path to AIC Off if SB or SB_SLEEP or SB_DAC; Enable DAC Path to AIC Figure 14-2 Internal CODEC works with AIC JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 286: Application Schematic

    VREFP/VCAP/VREFP and AVSCDC. This ceramic capacitor has to be kept as close as possible to IC package (closer than 0.2 inch) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 287: Mapped Register Descriptions

    A register read or a new register write cannot be issued before the previous write process is finished. In another word, RGADW should not be written before RGADW.RGWR becomes 0. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 288: Codec Internal Register Data Output (Rgdata)

    (RGADW.RGADDR field specifies the CODEC register‘s address) NOTE: AIC needs SYS_CLK (please refer to AIC spec), when write new value to or read from CODEC internal registers. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 289: Operation

    Make AIC to use internal CODEC mode: AICFR.ICDC = 1; Use internal CODEC. AICFR.AUSEL = 1; Use I2S mode. AICFR.BCKD = 0; CODEC input BIT_CLK to AIC. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 290: Power Saving

    Use internal CODEC. AICFR.AUSEL = 1; Use I2S mode. AICFR.BCKD = 0; CODEC input BIT_CLK to AIC. AICFR.SYNCD = 0; CODEC input SYNC to AIC. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 291: Timing Parameters

    Tsbyu is the reference wake-up time after complete power down. Tshd_adc is the ADC wake-up time after sleep mode. Tshd_dac is DAC wake-up time after sleep mode. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 292: C Parameters

    The current in case of short circuit is the max value. This current is only sink or drawn until the short circuit detection system acts. Please refer to Chip Datasheet for more details. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 293: Codec Internal Registers

    Register GCR_LIBYR Right channel bypass line Control Gain 00101011 / 0x2B / Register GCR_DACL Left channel DAC Gain Control Register 00101100 / 0x2C / JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 294: Codec Internal Registers

    0: SRC is not locked. Data from the audio interface are automatically muted. 1: The SRC is locked and operating normally. Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 295 Read STATE 00 : DAC not muted 01 : DAC being muted 10 : DAC leaving mute mode 11 : DAC in mute mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 296 Bits Field Description ADC_ADWL Audio Data Word Length for ADC path. Read / Write 00: 16-bit word length data 01: 18-bit word length data JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 297 Writing has no effect, read as zero. LO_SEL differential line-output Amplifier input selection Read/Write 000: DACL 001: DACR 010: DACL + DACR 011: reserved for future use JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 298 14.7.1.8 CR_DMIC: Digital Microphone Control Register Register Name: CR_DMIC Register Address: 0x10 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 DMIC_CLKON Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 299 Writing has no effect, read as zero. MIC1_SEL Microphone 1 input selection Read/Write 0 = selection of AIP1/AIN1 1 = selction of AIP2 14.7.1.10 CR_MIC2: Control Register for microphone2 inputs JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 300 1 = differential input Reserved Writing has no effect, read as zero. SB_LIBY1 Line 1 input power-down Read/Write 0 = active 1 = power-down JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 301 DAC_MUTE DAC soft mute mode. Read/Write 0: mute inactive, digital input signal transmitted to the DAC 1: puts the DAC in soft mute mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 302 1: power-down Reserved Writing has no effect, read as zero. ADC_IN_SEL selection of the signal converted by the ADC Read/Write: If MICSTEREO = 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 303 Refer to DR_MIX for MIX_LOAD description Digital mixer control registers address DAC_MIX Read/Write MIX_ADD Corresponding control register 000000 MIX_0 000001 MIX_1 000010 MIX_2 000011 MIX_3 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 304 Note: AIDACX_SEL should be configured to 01 in normal mode. MIX_1: Digital mixer control register 1 Register Name: CR_MIX Register Address: bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 MIXDACL_SEL MIXDACR_SEL Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 305 10: mixed inputs 11: 0 inputs Reserved Writing has no effect, read as zero. Note: MIXADCX_SEL should be configured to 01 in normal mode. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 306 Master Clock Frequency 0000 12 MHz 0001 Reserved for further use 0010 13 MHz …. Reserved for further use 1111 Reserved for further use JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 307 Selection of the ADC sampling rate (Fs). Read/Write The sampling frequency value is given in the FREQ table. NOTE: Please refer to section Sample frequency: FREQ. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 308 8-bit parallel control interface or 8 MCLK cycles duration when using SMB control interface 11: The generated IRQ is a low level pulse with an 8 MC_CLK cycles JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 309 0: interrupt enabled 1: interrupt masked (no IRQ generation) DAC_MUTE_ Mask for the DAC_MUTE_EVENT flag MASK Read/Write 0: interrupt enabled 1: interrupt masked (no IRQ generation) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 310 1 = indicates the beginning or the end of a soft mute on ADC data Write 0 = no effect 1 = Reset of the flag DAC_MODE_ Read JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 311 Reserved TIMER_END Reserved Bits Field Description Reserved Writing has no effect, read as zero. TIMER_END Timer status Read 0 = no event JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 312 GCR_LIBYL: left channel bypass line Gain Control Register Register Name: GCR_LIBYL Register Address: 0x2A bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-1 bit1-RW-1 bit0-RW-0 LRGI Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 313 Left channel DAC digital gain programming value. ―Programmable digital attenuation: GOD‖ NOTE: Please refer to section for more details. 14.7.1.33 GCR_DACR: right channel DAC Gain Control Register JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 314 GCR_ADCL: Left channel ADC Gain Control Register Register Name: GCR_ADCL Register Address: 0x30 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 LRGID Reserved GIDL JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 315 Writing has no effect, read as zero. GOMIXL Mixer gain for DAC path. Read/Write 00000 : 0dB 00001 : -1dB …by step of 1dB 11111 : -31dB JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 316 14.7.1.41 GCR_MIXADCR: ADC Right Digital Mixer Control Register Register Name: GCR_MIXADCR Register Address: 0x37 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 Reserved GIMIXR JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 317 NOTE: Please refer to section 14.7.1.43 DR_ADC_AGC: Automatic Gain Control Data Register Register Name: DR_ADC_AGC Register Address: 0x3B bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-1 bit1-RW-1 bit0-RW-1 ADC_AGC_DATA JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 318 Register Name: ADC_AGC_1 Register Address: bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 NG_EN NG_THR HOLD Bits Field Description NG_EN Selection of the Noise Gate system. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 319 1111: 512 ms NOTES: DCY and ATK registers values are delays between each step of gain. ―AGC system guide‖ for more details. Please refer to section JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 320 Writing has no effect, read as zero. AGC_MIN Maximum Gain Value to apply to the ADC path. NOTES: Please refer to below table for AGC_MIN setup. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 321: Programmable Gains

    (Vpp differential) (FS) 0.85*VREF 0.536*VREF 0.338*VREF 0.213*VREF 0.134*VREF 0.085*VREF 0.085*VREF 0.085*VREF NOTES: Analog input amplitude value is not more than ‘Maximum input amplitude’ for Vpp differential. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 322: Programmable Input Gain Amplifier: Gid

    The value of the gain GODL/R is programmable from +0 to –31dB with 1 dB pitch. The gain and output levels are obtained according to the following table: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 323: Programmable Attenuation: Go

    FS (Full Scale). The value is given in Vpp single-ended. These values refer to the external voltage reference VREF equal to (VREFP – VREFN). The voltage levels depend on the VREF voltage. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 324: Programmable Bypass Path Attenuation: Gi

    The following table shows the relation between the gain and GIMIX/GOMIX. GIMIX or GOMIX Gain value (dB) 00000 00001 00010 00011 … … 11101 11110 11111 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 325: Gain Refresh Strategy

    (> 24 kHz) of the output signal. The out-of-band noise, when not removed, can be damageable in some high quality applications. This filter is always working and does not need configure. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 326: Output Short-Circuit Protection (Headphone Output)

    Putting codec in sleep mode. (SB_SLEEP=1)  Putting codec in complete power-down mode. (SB=1) 14.12 Sampling frequency: FREQ The sampling frequency value is given in the FREQ table below. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 327: Programmable Data Word Length

    When the SB_HP is set to ‗1‘, the headphone output voltages (AOHPL, AOHPR) are slowly decreased in the same time from /2 down to 0. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 328: Agc System Guide

    TARGET sets the desired ADC output range level. The AGC system adapts the gain stages (GID and GIM) in order to best reach this target. AGC_MAX and AGC_MIN fix the limits of the gain variation. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 329: Figure 14-3 Agc Adjusting Waves

    The noise gate threshold is set by the NG_THR register value. The following graph shows a more detailed application. The following graph summarizes the operations and shows more details. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 330: Figure 14-4 Agc Adjust Areas

    E: If the signal level is in this range: the AGC system considers the signal as noise and does not perform gain adjustment. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 331: Digital Mixer Description

    Digital Mixer and the Data interface. The behavior is the following: AIDACLSEL1 AIDACLSEL0 I_ DAC_INL AIDACRSEL1 AIDACRSEL0 I_ DAC_INR DAC_INR DAC_INL DAC_INL DAC_INR (DAC_INL + (DAC_INL + DAC_INR)/2 DAC_INR)/2 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 332: Digital Microphone Interface

    (Fs) selected in FCR_ADC register. CODEC provides a clock (DMIC_CLK) and receives data on DMIC_IN at the same frequency. DMIC_CLK frequency depends on MCLK frequency selection in CCR register. Figure 14-5 Digital microphone interface connection JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 333: Timing Diagram

    14.17.2 Timings Parameter Symbol Unit DMIC_CLK frequency 3.25 dmic_clk DMIC_CLK duty cycle dmic_clk DMIC_IN setup time + 10 dmic_setup MCLK DMIC_IN hold time dmic_hold JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 334: Noise Template (Tbc)

    Normal mode: When CODEC is not in above mode, it is in this mode. This mode has three modes: RECORD mode, REPLAY mode, RECORD_REPLAY mode. The power diagram is shown below. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 335: Power-On Mode And Power-Off Mode

    After system reset the CODEC will exit Reset mode and go to STANDBY mode. NOTES: Except during the power-up mode, do NOT perform any reset in order to avoid audible pops. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 336: Standby Mode

    Tshd_adc (SB_ADC=0) for the ADC path or Tshd_dac (SB_DAC=0) for the DAC path. Prepare Active SB_SLEEP Shd_adc(shd_dac) Please refer to the section ―Timing parameters‖ for the Tshd_adc and Tshd_dac Value. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 337: Initial All The Gain

    Figure 14-9 DAC Gain up and gain down sequence In the opposite, when DAC_MUTE is set to 0, the DAC leaves the Soft Mute mode by increasing JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 338: Power-Down Mode And Active Mode

    But still need follow the anti-pop start or stop sequence. Please refer to ―Start up sequence‖ and ―Shutdown sequence‖. 14.18.8 Working modes summary Different working modes are sum-up in the following table (non exhaustive table): JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 339: Sys_Clk Turn-Off And Turn-On

    When SYS_CLK is turned off (SB_SLEEP=1 or SB=1), writing on register values are not taken into account, register values are not up to date when read and interrupts not generated until SYS_CLK turns on. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 340: Requirements On Outputs And Inputs Selection And Power-Down Modes

    The intent of the following sequence is to prevent for large audible glitches due to the system start-up with the CODEC. Before this sequence, setup the AIC properly. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 341: Figure 14-11 Start Up Sequence

    D: IRQ handling and gain-up cycle: the application handles the interrupt, resets the DAC_MODE_EVENT flag by writing ‗1‘ on it. The application first sets the wished gain on JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 342: Shutdown Sequence (Dac)

    The intent of the following sequence is to prevent for large audible glitches due to the system shutdown with the CODEC. Figure 14-12 Shutdown sequence JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 343: Start Up Sequence (Line Input)

    DAC path (SB_DAC register bit) to be in sleep mode or turn off the Codec (SB_SLEEP, SB register bits). 14.21.4 Start up sequence (Line input) Headphone port when driven by Line Input JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 344: Shutdown Sequence (Line Input)

    (number of gain steps * Tcrossout). G: Active mode: the signal path is now fully active. 14.21.5 Shutdown sequence (Line input) Stopping sequence from playback mode to sleep mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 345: Circuits Design Suggestions

    1uF and 10uF. Ideally use separate ground planes for analog and digital parts. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 346: Headphone Connection (Capacitor-Coupled)

    The ground of the headphone is connected to AGND, which is the PCB analog single point reference (star connection) ground. 14.22.3 Microphone connection The optimal performance for the SNR is obtained in differential Microphone inputs with a FS input level JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 347 1 uF AVSCDC Application schematic with differential MIC input (Vmicbias generated on board): XBurst Processor MICBIAS MICBIAS 1 uF MICP MICN 1 uF AVSCDC JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 348 SB_MICBIAS to 1 will close MICBIAS stage and the MICBIAS output voltage will be zero. MICBIAS output voltage scales with AVDCDC, equals to 5/6*AVDCDC (typical 2.08V). MICBIAS output current is 4mA max. MICBIAS output noise is 40uVrms max. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 349: Description Of The Connections To The Jack

    (which is using AVSCDC pin), should use the following principle to distribute the grounds. AVSHP AVSCDC (VREFN) AGND on board Rpart 1 Rpart 2 Figure 14-14 Ground distributing JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 350: Pcb Considerations

    Figure 14-15 the bottom corner of chip PCB Layer This is just an example reference diagram. You should change and select the PCB layer and route with JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 351: Analog Characteristics

    A-weighted, 1 kHz sine wave @ Full Scale and gain GIDL, GIDR = 0 dB, boost gain (TBC) (TBC) GIM1, GIM2 = 0 dB JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 352: Audio Dac To Headphone Output Path

    Max. Unit FOutput level (3) ull Scale, Gain GOL, GOR = 0 dB, GODL, 1.89 2.12 2.39 GODR = 0 dB, 10 kOhm load JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 353 Output bypass Cl (Rl = 10 kOhm) capacitor Cl (Rl = 16 Ohm) Gain range GOL, GOR 5-bit programmable range, digital control, @1 kHz JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 354: Audio Dac To Mono Line Output Path

    Note 1: The specified value is extrapolated by adding 60 dB to the measured SNR Note 2: The Full Scale input voltage scales with the nLR output: VREFP_CODEC. 14.23.4 Line input to headphone output path (analog bypass) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 355 Gain step GIL, GIR monotonic Gain accuracy GIL, GIR, @1 kHz -0.5 +0.5 Input Includes 10 pF for ESD, bonding and package capacitance pins capacitances JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 356: Micbias And Reference

    30 (TBC) 40 (TBC) uVrms Micbias decoupling capacitor Cmic 0.75 1.25 VCAP voltage 2 (TBC) VREFP_CODEC (also called 2.35 2.5 (TBC) 2.65 VREF) (TBC) (TBC) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 357: Section 4 Memory Interface

    MEMORY Section 4 MEMORY INTERFACE JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 358: Ddr Controller

    Row address width less than 16-bit & Column width less than 12-bit are supported. 15.1.2 Block Diagram Following figure shows the functional block diagram of DDRC. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 359: Register Description

    0x0C DDR Load-Mode-Register DTIMING1 0x60 DDR Timing Configure Register 1 DTIMING2 0x64 DDR Timing Configure Register 2 DTIMING3 0x68 DDR Timing Configure Register 3 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 360 (Performance control) Configuration of Internal Priority IPORTPRI 0x128 (Performance control) 0x07c 0x080 0x084 QoS configure for each channel CHDOS 0x088 (Performance control) 0x08c 0x090 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 361: Dstatus

    PDN: Indicate the power-down status of DDR memory. Bit [4] Description Remark DDR memory is NOT in power-down state. (reset value) DDR memory is in power-down state. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 362: Dcfg

    (or mask write operation) to avoid system bus being locked. A CS missing flag will set in DSTATUS. BSL: Burst length for DDR chips JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 363 COL0/1: Column Address width. Specify the Column address width of external DDR. Description Remark 8-bit Column address. (reset value) 9-bit Column address 10-bit Column address JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 364: Dctrl

    External memory data width is 32-bit. 15.2.3 DCTRL On the positive edge of START, the command selected by CMD field will be performed. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 365 If enable power-down mode, it is recommended to be set after DDR initialization. Bit [14:13] Description Remark power-down disabled, hardware never drive (reset value) SDRAM into power-down mode. Enter power-down after 8 tCK idle. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 366 UNALIGN: Enable unaligned transfer on AXI BUS. Bit [4] Description Remark Reserved Not use in this version ALH: Advanced Latency Hiding. This is a test-oriented register. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 367: Dlmr

    Bit 7~6, 2~1: Reserved. Writing has no effect, read as zero. DDR_ADDR: When performing a DDR command, DDR_ADDR[13:0] corresponding to external DDR address Pin A[13:0]; DDR_ADDR[15:14] are JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 368 Bit [0] Description Remark No command is performed. (reset value) On the positive edge of START, perform a command defined by CMD field. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 369: Dtiming1,2,3,4,5,6 (Ddr Timing Configure Register)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 370 All these registers‘ value has different rate between the tCK cycle tXSRD: exit self-refresh to READ delay. Delay time is tXSRD*4 (tCK) JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 371 After DDR memory turns into Self-Refresh or Deep-Power-Down mode, it will NOT exit until tMINSR condition meets. Delay Time = tMINSR * 8 + 1. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 372: Drefcnt (Ddr Auto-Refresh Counter)

    RST 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 373: Dmmap0,1 (Ddr Memory Map Configure Register)

    The physical base address and size of external DDR Memory can be configured by DMMAP register. The size of external DDR Memory must be: 2^(24+n), n=0, 1, 2, 3, …. When the following equation is met: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 374: Ddlp (Ddr Dfi Low Power Handshake Control Register)

    0: Use slow lp handshake process during self-refresh. SLP, FLP: slow LP handshake and fast LP handshake timing register, Just keep it as reset value. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 375: Dremap1,2,3,4,5 (Ddr Address Remapping Register 1,2,3,4,5)

    For example, If you want to remap address between address[27:25] and address[14:12], you can set BIT12MP as 0, BIT13MP as 1, BIT14MP as 2, BIT0MP as 12, BIT1MP JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 376: Wcmdctrl1 (Performance Wcmd Reorder & Grouping)

    Wpage-hit affects the reorder of wcmd, the wcmd with same page should be bonded for higher performance. This register indicates the maximum number of wcmd to be JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 377: Rcmdctrl0 (Performance Rcmd Request Control)

    If the coherency if not required in some application (such as LCD), ignoring of confliction would improve ddr read performance. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 378 0: disable rfifo_thd (recommanded) 1: enable rfifo_thd [5:0] ch0_rfifo_thd If Ch3 rfifo level threshold higher than this value, rcmd request is masked JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 379: Rcmdctrl1 (Performance Rcmd Request Control)

    RST 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 380: Wdatthd1 (Performance Wcmd Request Control)

    Port_pri: priority provided by masters. Iport_pri: register configurable which applies to each ports. The finial priority is the larger value of port_pri and iport_pri. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 381 0: disable, use external priority 1: enable, use the max priority of external and internal priority [9:8] Ch2_iport_pri Priority of channel 0x3: the highest priority JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 382: Chqos0,1,2,3,4,5 (Performance Qos Control)

    RST 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bits Name Description Rrset [31] Qos_en enable [17:16] Up-limit of priority [15:0] Threshold of timer 0x100 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 383: Cpm_Drcg

    Configure DMMAP0 = 0x. Configure DMMAP1 = 0x0000FF00. //---------------------------------------------------------------------------------------- ------------------- // INIT DDR PHY //----------------------------------------------------------------------------------------------------------- Configure DDR PHY and finish PHY training process.(relate to DDRPHY spec) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 384: Change Clock Frequency

    15.4.2 CPM driven SELF-REFRESH Mode CPM will auto drive DDRC to self-refresh mode, when use ddr2, ddr3. To change clock frequency, please refer CPM spec. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 385: Dll Bypass Mode

    CS0# BA[2] BA[1:0] BA[1:0] A[13] A[12:0] A[12:0] RAS#,CAS#,WE# RAS#,CAS#,WE# CK,CK# CK,CK# DQ[31:16] DQ[15:0] DQ[15:0] DQS[2] DQS[0] LDQS DQS[3] DQS[1] UDQS DM[2] DM[0] DM[3] DM[1] JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 386: Connection To Two 512Mb X16 Ddr2 Devices

    RAS#,CAS#,WE# RAS#,CAS#,WE# CK,CK# CK,CK# CK,CK# DQ[31:16] DQ[15:0] DQ[15:0] DQ[15:0] DQS[2] DQS[0] LDQS LDQS DQS[3] DQS[1] UDQS UDQS DM[2] DM[0] DM[3] DM[1] BA[2] A[13] JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 387: External Nand Memory Controller

    6 ~ 1 accessed. Read enable RD# / For Static memory read enable signal. Write enable WE# / Static memory write enable signal. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 388: Physical Address Space Map

    Both virtual spaces and physical spaces are 32-bit wide in this architecture. Virtual addresses are translated by MMU into physical address which is further divided into several partitions for static memory, SDRAM, and internal I/O. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 389: Figure 16-1 Physical Address Space Map

    Reserved Space (16MB) 0x15000000 Reserved Space (16MB) 0x14000000 Internal I/O Space (64MB) 0x10000000 DRAM Space (256MB) 0x00000000 Figure 16-1 Physical Address Space Map JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 390: Table 16-2 Physical Address Space Map

    CS5# Static memory bank 5 64 B 8, 32 0x17000000 0x1700003F CS6# Static memory bank 6 64 B 8, 32 0x16000000 0x1600003F NOTES: JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 391: Static Memory Interface

    0x13410034 configuration register SACR2 Static memory bank 2 address 0x000018FE 0x13410038 configuration register SACR3 Static memory bank 3 address 0x000017FF 0x1341003C configuration register JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 392 For burst ROM, these bits specify the number of wait cycles to be inserted in first data read strobe time. TAW3~0 Wait cycle Wait# Pin 0000 0 cycle Ignored JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 393 These bits specify the number of wait cycles to be inserted from negation of read/write strobe to address. TAH2~0 Wait cycle 0000 0 cycle 0001 1 cycle 0010 2 cycles JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 394 BW1~0 Bus Width 8 bits (Initial Value) Reserved Reserved Reserved Reserved Writing has no effect, read as zero. NOTE: Don‘t write Bit3 to 1. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 395 RST2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 396: Example Of Connection

    Following figures shows examples of connection to 8-bit data width normal memory. 1M x 16bit Processor SRAM SA5-0 A5-0 CSn# SD7-SD0 I/O7-I/O0 Figure 16-2 Example of 16-Bit Data Width SRAM Connection JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 397: Basic Interface

    Therefore, there is no negation period in case of access at minimum pitch. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 398: Figure 16-4 Basic Timing Of Normal Memory Read

    *In this example, SMCRn: SMT = 0, TAS = 0, TBP = 0, TAH = 0 Figure 16-5 Basic Timing of Normal Memory Write JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 399: Figure 16-6 Normal Memory Read Timing With Wait (Software Wait Only)

    *In this example, SMCRn: SMT = 0, TAS = 1, TBP = 1, TAH = 1 Figure 16-7 Normal Memory Write Timing With Wait (Software Wait Only) JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 400: Burst Rom Interface

    TAW instead of TBP is used to set the delay time of write strobe. WAIT# pin sampling is always performed when one or more wait states are set. Following figures show the timing of burst ROM. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 401: Nand Flash Interface

    Toggle NAND Control Register 3 0x0FFF770A 0x13410118 TGCR4 Toggle NAND Control Register 4 0x0FFF770A 0x1341011C TGCR5 Toggle NAND Control Register 5 0x0FFF770A 0x13410120 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 402 Toggle NAND flash, this bit is initialized to 1. TNFE Description Static bank n is used as conventional NAND flash Static bank n is used as Toggle NAND flash JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 403 Calculate number of ―0‖ in NAND read data Calculate number of ―1‖ in NAND read Data BIT_EN NAND BIT Counter Enable: Enable/disable bit counter counting. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 404 CE, CLE and ALE. Before any Toggle NAND data write access, software MUST write 1 to corresponding SDEn, and WCD shall be checked prior to a write data access. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 405: Figure 16-10 Toggle Nand Page Write/Read Operation

    Set DQS output enable (bank5): Before data write access, software MUST write 1 to SDE5. After CDQSS cycles, controller will goes into data-write-mode. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 406 Its value is the number of idle cycles (0~63 cycles) inserted between bus cycles when switching from one bank to another bank or between a read JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 407 TGSR is 32-bit read/write registers that specify the number of delay cycles (0~31 cycles) from RD# to DQS for Toggle NAND flash. On reset, TGSR is initialized to 0x14A5294A. See Figure 16-12. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 408 255 cycles is the initial value. FDA 1 Toggle NAND Flash ALE Fall to DQS Rise (Bank1). 255 cycles is the initial value. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 409 NOTE. CLR MUST smaller than FDA3 , and >=2. 15:8 CLR 2 Toggle NAND Flash CLE to RE_n Low (Bank2). 100 cycles is the initial value. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 410 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 411 Writing has no effect, read as zero. 23:16 CDQSS DQS Setup Time for data input start (bank3). (i.e. ale_fall – dqs_rise < tCDQSS3 and ale_fall – dqs_fall < tCDQSS3) JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 412 Description 31:17 Reserved Writing has no effect, read as zero. Timer Done: After set CWAW, this bit will be low CWAW cycles. When JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 413: Figure 16-11 Example Of Dqs Delay Line Auto-Detect-Operation

    Writing has no effect, read as zero. DQS Delay Detect ERROR: When hardware detect one ahb_clk cycle delay failed, ERR is set high; JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 414 DQS Hold Time for data input (bank3). 15:8 CDQSH DQS Hold Time for data input (bank2). CDQSH DQS Hold Time for data input (bank1). JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 415: Figure 16-12 Basic Timing Of Toggle Nand Write

    Wait DPHTD Wait WCD DPHTD After the Last Data Read, CS# MUST set to 1 Figure 16-12 Basic Timing of Toggle NAND Write JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 416: Figure 16-13 Basic Timing Of Toggle Nand Read

    Wait WCD DPHTD Wait DPHTD After the Last Data Write, CS# MUST set to 1 Figure 16-14 Basic Timing of Toggle NAND Page Write JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 417: Nand Flash Boot Loader

    NAND Flash Boot Loader. On-chip NEMC 16KB Boot ROM NAND SRAM Flash Off-chip memories Figure 16-16 Structure of NAND Flash Boot Loader JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 418: Nand Flash Operation

    CSn# is controlled by NFCE bit NFCSR. CSn# is always asserted when NFCE is 1. When NFCE is 0, CSn# is asserted as normal static memory access. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 419: Example Of Toggle Nand Flash Access

    RB# wait TGWE.WCD software MUST set Step 2. Wait TGPD.DPHTDx set NFCSR.FCEx TGWE.SDEx|DAE DQ[7:0] Write DATA Figure 16-20 Toggle NAND Page Program Operation JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 420: Figure 16-21 Toggle Nand Page Program Operation (Basic)

    Figure 16-21 Toggle NAND Page Program Operation (Basic) write Polling TGIT.CWAW TGIT.TD 300ns DQ[7:0] Write DATA Write DATA Figure 16-22 Program Operation with Random Data Input JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 421: Bch Controller

    BCH Error Report 5 register 0x00000000 0x134D0098 BHERR6 BCH Error Report 6 register 0x00000000 0x134D009C BHERR7 BCH Error Report 7 register 0x00000000 0x134D00A0 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 422 BCH Error Report 59 register 0x00000000 0x134D0170 BHERR60 BCH Error Report 60 register 0x00000000 0x134D0174 BHERR61 BCH Error Report 61 register 0x00000000 0x134D0178 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 423: Register Description

    BCH Encoding/Decoding Bit Select: It is used to select the correction algorithm. Only multiples of 4 are supported (i.e. ECC 4, 8, 12 ... 56, 60, 64). BSEL Description 4-bit correction JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 424: Bch Control Set Register (Bhcsr)

    BCH Encoding/Decoding Bit Select Set: It is used to set BHCR.BSEL to 1. Reserved Writing has no effect, read as zero. ENCES BCH Encoding/Decoding Select Set: It is used to set BHCR.ENCE to JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 425: Bch Control Clear Register (Bhccr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 426: Bch Data Register (Bhdr)

    When 8-bit BCH is selected, BHPAR0~BHPAR3 consist of the 112 bits of parity data and bit 0 of BHPAR0 is the 112th bit of parity data and bit 15 of BHPAR3 is the 1st bit of parity data. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 427: Bch Error Report Register (Bherrn, N=0,1,2,3,4,5,6,7

    Example, if n = 1, INDEX1 = 2, MASK1=0x5080, it means the second half word is JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 428: Bch Interrupt Status Register (Bhint)

    Bypass output: Indicates that no corrections were applied to the data block since the BPSO was asserted at the beginning of the correction operation. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 429 Error: It indicates that hardware detects error bits in data in the data block and parity block during BCH decoding. Description No error (Initial value) Error occur JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 430: Bch Interrupt Enable Set Register (Bhintes)

    SYNDROME Finish interrupt Enable Clear: It is used to clear BHINTE.SDMFE to 0. ALL_FEC ALL_F Interrupt Enable Clear: It is used to clear BHINTE.ALL_FE to JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 431: Bch Interrupt Enable Register (Bhinte)

    Encoding Finish Interrupt Enable: It is used to enable or disable encoding finish interrupt. ENCFE Description Disable Encoding Finish Interrupt (Initial value) Enable Encoding Finish Interrupt JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 432: Bch User Tag Output Register (Bhto)

    During decoding, if there are error bits in data block, after decoding BHERRn registers will hold the error location that can be read by CPU or DMA. 17.3.1 Encoding Sequence BCH encoding can be operated by CPU or DMA. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 433: Figure 17-1 Block Diagram For Bch Encoding

    BCH controller will issue encoding request to DMA when encoding ends. 10 DMA start to read out parity data. 11 After parity data is read out, DMA automatically clear BHINT.ENCF. JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 434: Decoding Sequence

    Bank0 Bank1 Bank2 Bank3 Bank4 Bank5 PDMA correct bch decoding errors 4 PDMA Figure 17-2 Block Diagram for BCH decoding JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 435: Figure 17-3 Bch Decoding Data Flow

    Channel transfer enable. TT=1? TT=1? DONE Sent Data From Sent Data From TCSM to BCH(2) TCSM to DDR(5) Figure 17-3 BCH decoding data flow JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 436: Section 5 System Functions

    BCH Controller Section 5 SYSTEM FUNCTIONS JZ4780 Mobile Application Processor Cores/Systems Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 437: Clock Reset And Power Controller

    SSI clock supports 50M clock   MSC clock supports 100M clock Functional-unit clock gating  Shut down power supply for J1, VPU, GPU, GPS, P1  JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 438: Cgu Block Diagram

    Following figure illustrates a block diagram of CGU. RTCLK 32.768K SCLK_A L2CAHE APLL AHB0 SCLK_M MPLL SCLK_E AHB2 EPLL SCLK_V VPLL SCLK_A SCLK_M SCLK_A SCLK_M SCLK_E SCLK_A SCLK_M SCLK_E JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 439 Clock Reset and Power Controller SCLK_A SCLK_M SCLK_V SCLK_A SCLK_M SCLK_E EXCLK SCLK_A SCLK_E SCLK_A SCLK_A SCLK_M EXCLK SCLK_A SCLK_M SCLK_A SCLK_A SCLK_M SCLK_V OTG_PHY JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 440: Cgu Registers

    Reset Value Address Access Size CPCCR Clock Control Register 0x95000000 0x10000000 CPCSR Clock status register 0x00000000 0x100000D4 DDCDR DDR clock divider Register 0x40000000 0x1000002C JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 441 RST 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 442 Change enable for AHB2. If CE_AHB2 is 1 , write on H2DIV, PDIV will start a frequency changing sequence immediately. If CE_AHB2 is 0, writes on H2DIV, PDIV have no affect. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 443 Divider for AHB2 Frequency. Specified the AHB2 CLK division ratio. Bit 15~12: H2DIV Description X1/2 X1/3 X1/4 X1/5 X1/6 X1/7 X1/8 X1/9 X1/10 X1/11 X1/12 X1/13 X1/14 Clr stop JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 444 L2CDIV Divider for L2CACHE Frequency. Specified the L2C CLK division ratio. Bit 7~4: L2CDIV Description X1/2 X1/3 X1/4 X1/5 X1/6 X1/7 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 445 When software sets CDIV == 1110 and CE is 1, CCLK will continue to run. CDIV value will not be changed actually, it is only clear register. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 446 DDR memory clock . This register is initialized to 0x40000000 only by any reset. Only word access can be used on DDRCDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 447 VPU clock divider Register (VPUCDR) is a 32-bit read/write register that specifies the divider of VPU clock . This register is initialized to 0x00000000 only by any reset. Only word access can be used on VPUCDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 448 I2S device clock divider Register (I2SCDR) is a 32-bit read/write register that specifies the divider of I2S device clock . This register is initialized to 0x00000000 only by any reset. Only word access can be used on I2SCDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 449 LCD pix clock divider Register (LPCDR) is a 32-bit read/write register that specifies the divider of LCD pixel clock (LPCLK). This register is initialized to 0x04000000 only by any reset. Only word access can be used on LPCDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 450 LCD1 pix clock divider Register (LPCDR1) is a 32-bit read/write register that specifies the divider of LCD1 pixel clock (LPCLK). This register is initialized to 0x04000000 only by any reset. Only word access can be used on LPCDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 451 MSC0 device clock . This register is initialized to 0x40000000 only by any reset. Only word access can be used on MSC0CDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 452 MSC1 device clock . This register is initialized to 0x00000000 only by any reset. Only word access can be used on MSC1CDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 453 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 454 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 455 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 456 CIM mclk clock divider Register (CIMCDR) is a 32-bit read/write register that specifies the divider of CIM mclk clock (CIM_MCLK). This register is initialized to 0x00000000 only by any reset. Only word access can be used on CIMCDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 457 PCM device clock . This register is initialized to 0x00000000 only by any reset. Only word access can be used on PCMCDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 458 GPU clock divider Register (GPUCDR) is a 32-bit read/write register that specifies the divider of GPU clock . This register is initialized to 0x40000000 only by any reset. Only word access can be used on GPUCDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 459 HDMI clock divider Register (HDMICDR) is a 32-bit read/write register that specifies the divider of HDMI clock . This register is initialized to 0x00000000 only by any reset. Only word access can be used on HDMICDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 460 BCH clock divider Register (BCHCDR) is a 32-bit read/write register that specifies the divider of BCH clock . This register is initialized to 0x40000000 only by any reset. Only word access can be used on BCHCDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 461 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 462 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 463 ―incr transfer‖ takes effect. Set this bit to 0 will active the enhancement. TXRISETUNE This bit adjusts the rise/fall times of the high-speed waveform JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 464 3‘b101 -10% 3‘b100 3‘b011 default 3‘b010 3‘b001 +10% 3‘b000 +15% 10:7 TXFSLSTUNE These bits control FS/LS source impedance adjustment. 4‘b1111 4‘b0111 -2.5% 4‘b0011 Default JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 465 RST ? ? ? ? ? 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 466 RST ? ? ? 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 1 1 0 0 0 0 Bits Name Description USB_SE 1: synopsys otg 0: mentor otg JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 467 3‘b111 STUNE1 +4.5% 3‘b110 3‘b101 +1.5% 3‘b100 Default 3‘b011 -1.5% 3‘b010 3‘b001 -4.5% 3‘b000 14:12 SQRXTU These bits control squelch threshold adjustment. 3‘b111 -20% JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 468 -1.25% 4‘b0011 -2.5% 4‘b0010 -3.75% 4‘b0001 4‘b0000 -6.25% TXRISET This bit adjusts the rise/fall times of the high-speed waveform UNE1 1: -8% 0: default JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 469 BW = nom_BW*sqrt(NF / 2 / NB) where nom_BW is approximately given by: nom_BW = Fref / (NR*20) and Fref is the reference clock frequency. The damping factor (D) is JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 470 ARFSLIP goes active for one or more divided feedback VCO cycles when the phase detector misses a divided reference cycle, i.e. when the VCO is running too fast. It is only used to debug JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 471 The MPLL Control Register (CPMPCR) is a 32-bit read/write register, which controls PLL multiplier, on/off state and stabilize time. It is initialized to 0x00000000 only by any reset. Only word access can JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 472 PLL will linearly settle (smoothly transition) to the new frequency. This constraint usually means that the frequency should be changed by less than 20%. Changes in excess of 20% can result in large JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 473 VCO is running too fast. It is only used to debug EFBSLIP EFBSLIP goes active for one or more divided reference cycles when JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 474 The VPLL Control Register (CPVPCR) is a 32-bit read/write register, which controls PLL multiplier, on/off state and stabilize time. It is initialized to 0x00000000 only by any reset. Only word access can be used on CPVPCR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 475 PLL to lose lock. This state may necessitate putting the PLL through the reset sequence to re-achieve lock. Each linear settling change will require on the order of JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 476: Pll Operation

    The PLL output frequency, FOUT, is determined by the ratio set between the value set in the input divider and the feedback divider. PLL output frequency FOUT is calculated from the JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 477: Main Clock Division Change Sequence

    In IDLE mode, the clock to the CPU core is stopped except the bus controller, the memory controller, the interrupt controller, and the power management block. To exit the IDLE mode, the any interrupts should be activated. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 478: Register Description

    SLPC Sleep PC Register 0x???????? 0x100000CC ERNG Enable rng regsiter 0x00000000 0x100000D8 rng regsiter 0x???????? 0x100000DC OPCR Oscillator and Power Control Register 0x000015C0 0x10000024 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 479 When GPU_IDLE high indicates that the GPU core is idle can be powered off. 19:8 Power stability Time. Specifies the Power stabilize time by unit of RTCCLK (approximate 32kHz) cycles. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 480 Memory Power control for SSI1 0: on 1: shutdown Memory Power control for CPM 0: on 1: shutdown I2S1 Memory Power control for I2S1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 481 Memory Power control for MSC2 0: on 1: shutdown MSC1 Memory Power control for MSC1 0: on 1: shutdown TSSI1 Memory Power control for TSSI1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 482 0: on 1: shutdown Memory Power control for SCC 0: on 1: shutdown SADC Memory Power control for SADC 0: on 1: shutdown Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 483 0: on 1: shutdown Important Note : Software should take care when shutting down these rams of the above modules, especially from sleep mode restore. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 484 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 485 Module Description DDR1 DDR0 After reset period, the clock is stopped. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 486 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 487 Description VPU_SR 0: VPU does not enter soft reset mode 1: VPU enters soft reset mode VPU_STP Request for VPU to Stop bus transfer. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 488 Sleep Boot Control Register (SLBC) The Sleep Boot Control Register is a 32-bit read/write register that control sleep boot mode.It is initialized to 0x0000000 0by reset. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 489 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 490 Don‘t change this bit , it is only used to debug Reserved 27:26 L2CM_PD 00 : L2CACHE memory doesn‘t power down in sleep mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 491: Doze Mode

    Clock control is in increments of approximately 3% (1/31). Doze is exited by software, interrupt, reset or SLEEP instruction. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 492: Idle Mode

    The procedure of entering Power Down mode is shown blow: set proper values for PSWC0ST, PSWC1ST, PSWC2ST, PSWC3ST. set PD_VPU bit in LCR to 1. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 493: Reset Control Module

    This bit can only be written with 0. Write with 1 will be ignored. 0: P0 reset has not occurred since the last time the software clears this JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 494: Power On Reset

    Then WDT reset source is cleared because of internal reset. The internal reset is asserted for about 10 milliseconds. CPU and peripherals are clocked by EXCLK oscillator output directly. PLL is reset to off state. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 495: Timer/Counter Unit

    In this section, we will describe the registers in timer. Following table lists all the registers definition. All timer register‘s 32bit address is physical address. And detailed function of each register will be described below. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 496 0x0000 0x1000208C TDFR5 Timer Data FULL Register 5 0x???? 0x10002090 TDHR5 Timer Data HALF Register 5 0x???? 0x10002094 TCNT5 Timer Counter 5 0x???? 0x10002098 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 497: Timer Control Register (Tcsr)

    Writing has no effect, read as zero. BYPASS PWM bypass mode. 1: If PCK_EN = 1, this channel output PIXCLK; If RTC_EN = 1, this channel output RTCCLK; JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 498 These bits select the TCNT count clock frequency. Don‘t change this PRESCALE field when the channel is running. Bit 2 Bit1 Bit 0 Description Internal clock: CLK/1 Internal clock: CLK/4 Internal clock: CLK/16 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 499: Timer Data Full Register (Tdfr)

    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDFR ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 500: Timer Data Half Register (Tdhr)

    0x0000 by any reset. It can only be set by register TESR and TECR. Since the timer enable control bits are located in the same addresses, two or more timers can be started at the same time. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 501: Timer Counter Enable Set Register (Tesr)

    Since the timer enable control set bits are located in the same addresses, two or more timers can be started at the same time. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 502: Timer Counter Enable Clear Register (Tecr)

    The TECR is a 32-bit write-only register. It contains the counter enable clear bits for each channel. Since the timer enable clear bits are located in the same addresses, two or more timers can be stop at the same time. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 503: Timer Flag Register (Tfr)

    The TFR is a 32-bit read-only register. It contains the comparison match flag bits for all the channels. It can also be set by register TFSR and TFCR. It is initialized to 0x00000000 by any reset. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 504: Timer Flag Set Register (Tfsr)

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 505: Timer Flag Clear Register (Tfcr)

    Set OSTFLAG n bit of TFR. 0: Ignore 1: Set OSTFLAG n bit to 0 14:12 Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 506: Timer Mast Register (Tmr)

    0: Comparison match interrupt not mask 1: Comparison match interrupt mask FMASK 7~0 FULL comparison match interrupt mask. 0: Comparison match interrupt not mask 1: Comparison match interrupt mask JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 507: Timer Mask Set Register (Tmsr)

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 508: Timer Stop Register (Tsr)

    0: The clock supplies to OST is supplied 1: The clock supplies to OST is stopped 14:8 Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 509: Timer Stop Set Register (Tssr)

    1: Set OSTS bit to 1 14:8 Reserved Writing has no effect, read as zero. STPS 7 Set STOP 7 bit of TSR. 0: Ignore JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 510: Timer Stop Clear Register (Tscr)

    Writing has no effect, read as zero. WDTSC Set WDTS bit of TSR. 0: Ignore 1: Set WDTS bit to 0 OSTSC Set OSTS bit of TSR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 511: Timer Status Register (Tstr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:19 Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 512: Timer Status Set Register (Tstsr)

    Writing has no effect, read as zero. 19.3.19 Timer Status Clear Register (TSTCR) The TSTCR is a 32-bit write-only register. It contains the timer status clear bits for each channel. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 513: Timer Control Mode Register (Tcumod)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:16 Reserved Writing has no effect, read as zero. 15:10 cyc_num Set the fifo cycle numbers. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 514: Timer Fifo Write Data (Tfwd)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 515: Operation

    19.4.3 Basic Operation in TCU2 Mode The value of TDFR should be bigger than TDHR, and the minimum settings are TDHR = 0 and TDFR JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 516: Disable And Shutdown Operation In Tcu2 Mode

    If TSTR.REAL is always 0, you can read some data, and lose some data that is quick different from the others. Then choose a data from them as the available data. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 517: Pulse Width Modulator (Pwm)

    After initialize the register of timer, we should start the counter as follows: Enable the counter. Setting the TESR.TCST bit to 1 to enable the TCNT. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 518: Basic Operation In Fifo Mode 1

    5. set the TCSR.PWM_EN to 1. 6. set the TESR to enable the TCNT. 7. if step 4 has been done, do not push data into fifo, JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 519 4. write_reg(0x10002100,0x00002A59); // conduct ten cycles, each cycle would match five data from fifo 5. write_reg(0x1000204C,0x00000082); 6. write_reg(0x10002014,0x00000001); 7. if(TFIFOSR. TCUMOD. cyc_timer == cyc_num finish JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 520: Operating System Timer

    Match interrupt can be generated for OST using the compare data registers   Interrupt flag and interrupt mask is same with TCU in TCU spec JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 521: Register Description

    Shut Down (SD) the PWM output. It is only used in TCU1 mode. 0: Graceful shutdown (only used when CNT_MD = 0) 1: Abrupt shutdown PRESCALE These bits select the TCNT count clock frequency. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 522: Operating System Timer Data Register (Ostdr)

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 523: Operating System Timer Counter (Ostcnth, Ostcntl)

    Writing TCSR.SD to setting the shutdown mode (Abrupt shutdown or Graceful shutdown). Writing OSTCSR.PRESCALE to set OSTCNT count clock frequency. Setting OSTCNTL/H and OSTDR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 524: Disable And Shutdown Operation

    NOTE: The input clock and PCLK should follow the rules advanced before. 20.3.2 Disable and Shutdown Operation Setting the TECR.OSTCCL bit to 1 to disable the OSTCNT. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 525: Interrupt Controller

    DSR1 IRQ Source Register1 for PDMA 0x00000000 0x10001040 DMR1 IRQ Mask Register1 for PDMA 0xFFFFFFFF 0x10001044 DPR1 IRQ Pending Register1 for PDMA 0x00000000 0x10001048 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 526: Interrupt Controller Source Register (Icsr0)

    Its value can be changed either by writing ICMSR and ICMCR or by writing itself. The masked interrupts are invisible to the processor. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 527: Interrupt Controller Mask Register (Icmr1)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 528: Interrupt Controller Mask Set Register (Icmsr1)

    21.2.8 Interrupt Controller Mask Clear Register (ICMCR1) This register is used to clear bits in the interrupt mask register. This register is write only. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 529: Interrupt Controller Pending Register (Icpr0)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 530: Interrupt Source Register0 For Pdma (Dsr0)

    The corresponding interrupt source is pending. 21.2.13 Interrupt Pending Register0 for PDMA (DPR0) This register contains the status of the interrupt sources after masking. This register is read only. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 531: Interrupt Source Register1 To Pdma (Dsr1)

    RST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 532: Interrupt Pending Register1 For Pdma (Dpr1)

    Find the highest priority interrupt and vector it. (The software decides which one has the highest priority) Mask the chosen interrupt by writing the register ICMSRx. Enable the system interrupt to allow the interrupt nesting. (software decided) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 533 Execute the interrupt handler and unmask it by writing the register ICMCRx when exit the handler. CPU restores the saved environment and exits the interrupt state. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 534: Watchdog Timer

    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 535: Watchdog Enable Register (Tcer)

    0x00 by any reset. TCER 0x10002004 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 536: Watchdog Timer Data Register (Tdr)

    Select the input clock and enable the input clock in register TCSR. After initialize the register of timer, we should start the counter as follows: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 537 The clock of WDT can be stopped by setting register TSR, and register TSR can only be set by register TSSR or TSCR. The content of register TSR, TSSR and TSCR can be found in TCU spec. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 538: Pdma Controller

    Channel 30 Channel 31 (16KB TCSM with 8 banks) (16KB TCSM with 8 banks) BUF0 BUF1 BUF0 BUF1 AHB2 Figure 23-1 Block Diagram of PDMA JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 539: Memory Mapped Register Descriptions

    Grey ones are obsolete registers defined in previous JZ SOC. They are relative to clock gating and have no real function, and they are not supported any longer. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 540: Dma Channel Register Definition

    8 bits is the number of sub-block. TC automatically counts down to 0 at the end. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 541: Dma Request Types (Drtn, N = 0 ~ 31)

    UART0 receive-fifo-full transfer request. (URBR  external address) 010101 010110 SSI0 transmit-fifo-empty transfer request. 010111 SSI0 receive-fifo-full transfer request. 011000 SSI1 transmit-fifo-empty transfer request. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 542: Dma Channel Control/Status (Dcsn, N = 0 ~ 31)

    RST ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 543: Dma Channel Command (Dcmn, N = 0 ~ 31)

    RST 0 0 0 0 0 0 0 0 ？ ？ 0 0 ？ ？ ？ ？ ？ ？ ？ ？ 0 ？ ？ ？ 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 544: Table 23-4 Available Rdil

    Recommended data unit is 3 bytes Recommended data unit is 4 bytes Recommended data unit is 8 bytes Recommended data unit is 16 bytes JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 545 TSZ means better transfer efficiency. If source port width is 32bit, source address must be 4-byte aligned and TSZ must be the JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 546 DDR memory, then no alignment constraint for source address, and if destination port width is 8bit, setting autonomy (TSZ=7) is the best choice for transfer efficiency JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 547 TSZ is recommended when condition is ok. Please refer to relative device‘s spec for detail information of how to set critical trigger value. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 548: Dma Descriptor Address (Ddan, N = 0 ~ 31)

    Source Stride Difference (next sub-block‘s start address – current 15:0 sub-block‘s end address - 1), value range is -32768 ~ 32767 23.5 DMA Global Register Definition 23.5.1 DMA Control JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 549 UNPREDICTABLE to set 0 to DMAE abruptly when some channels are still working. For more detail of CH01, refer to later chapter of special channel 0 and channel 1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 550: Dma Interrupt Pending (Dirqp)

    For example, write 0x00000001 to DDS, DB0 bit is set to 1 and enable DMA channel 0 to fetch its first descriptor. Write 0 to DDS, no meaning. 23.5.4 DMA Doorbell Set (DDS) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 551: Dma Channel Programmable (Dmacp)

    0, no soft IRQ to MCU; 1, pending soft IRQ to MCU. Note that the register is read-only for other masters but is entirely controlled (R/W) by the MCU of PDMA JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 552: Dma Soft Irq Mask

    INTC_IRQ, if DCIRQMm==0, an active INTC_IRQ request will trigger an active CIRQn immediately 23.5.9 DMA Channel IRQ to MCU Mask JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 553: Programmable Channel Bound With Intc_Irq

    DCM1.SP and DCM1.DP must be set 0 10. DCM0.TSZ and DCM1.TSZ must be set 7 11. DMACP.DCP0 and DMACP.DCP1 must be set 1 after relative firmware has been prepared. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 554: Mcu

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 555: Mcu Security Mailbox

    Write has no effect, read as zero. S_IMSK Security Mailbox IRQ mask. 1-mask; 0-not mask Can only be modified in security mode. N_IMSK Normal Mailbox IRQ mask. 1-mask; 0-not mask JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 556: Multiple Bank Tightly Coupled Sharing Memory

    SeCAUSE (13) Bit31:BD, similar as CAUSE, but being active when an IRQ interrupted a running SecurityCall routine. Bit30 ~ 0: reserved, read as zero JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 557: Normal Exceptions Accepted By Mcu

    SecurityCall relative data structure to the proper location of TCSM, must be 256-byte aligned set DMCS.SC_OFF to point to the position (0xF4000000 + DMCS.SC_OFF<<8). JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 558: Interruptable Smd Mode

    //subroutine of poping GPR (except ra) 20. lw sp, 0(k0) //restore sp in SMD mode 21. lw ra, 4*31(sp) //pop ra 22. addu sp, sp, 4*32 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 559: Dma Manipulation

    Wait for DMA request from peripherals to start channel n‘s DMA transfer. After DMA transfers described by the current descriptor complete, if current DCMn.LINK =0, JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 560: Table 23-6 Descriptor Structure

    Transfer Counter 5th (DES4) 31-16 Target Stride Address 15-0 Source Stride Address 6th(DES5) 31-6 Reserved DMA Request Type 7th(DES6) 31-0 Reserved 8th(DES7) 31-0 Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 561: Figure 23-2 Descriptor Transfer Flow

    JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 562: No-Descriptor Transfer Mode

    DMA to let DMA rerun properly later. 23.8 DMA Requests DMA transfer requests are normally generated from either the data transfer source or target, but JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 563: Auto Request

    DSIRQM.SIRQMn must be set 0, then at expected moment, the MCU sets 1 to DSIRQP.SIRQn to trigger a soft IRQ. It is the responsibility of this soft IRQ‘s handler to remove the IRQ by setting 0 to DSIRQP.SIRQn. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 564: Sar A/D Controller

    Touch screen analog differential X+ position input Touch screen analog differential Y+ position input VBAT VBAT direct input * AUX1 Auxiliary Input AUX2 Auxiliary Input JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 565: Register Description

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Bits Name Description 31:8 Reserved Writing has no effect, read as zero. POWER SADC Power control bit. 1: SADC power down JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 566: Adc Configure Register (Adcfg)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 567 The number of repeated sampling one point. When A/D is used as Touch Screen, SNUM is used as follows: SNUM Number Reserved Reserved Reserved Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 568: Adc Control Register (Adctrl)

    Pen up interrupt mask. 0: enabled 1: masked DTCHM Touch Screen Data Ready interrupt mask. 0: enabled 1: masked VRDYM VBAT data ready interrupt mask. 0: enabled JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 569: Adc Status Register (Adstate)

    VBAT data ready interrupt flag. Write 1 to this bit, the bit will clear this bit. 1: active 0: not active ARDY AUX data ready interrupt flag. Write 1 to this bit, the bit will JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 570: Adc Same Point Time Register (Adsame)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 571 Xd. The second time reading gets the data Z2d and Z1d. The touch pressure measurement formula is as follows: (You can use formula 1 or formula JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 572 Y2 and X2. When A/D is used as Touch Screen, ADCFG.XYZ=11.TYPE=0. The format of touch screen data is as follows: Type1 Reserved Data1 Type0 Reserved Data0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 573: Adc Vbat Data Register (Advdat)

     4096 24.2.9 ADC AUX Data Register (ADADAT) The read-only ADADAT is a 16-bit register, it keep the sample data. 0~11 bits are data. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 574: Adc Clock Divide Register (Adclk)

    The A/D works at the frequency between 20KHz and 200KHz. If CLKDIV = N, Then the freq of adc_clk = dev_clk / (N+1). 0 ≤ N ≤ 255 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 575: Adc Command Register (Adcmd)

    Use YN as ADC input channel control switch. 0: open; 1: close. WIPEADC Use WIPE as ADC input channel control switch. 0: open; 1: close. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 576: Sar A/D Controller Guide

    Z3 Z4 X2Y2 (Reference register bit SPZZ). Set ADCFG.SNUM to choose one point sampling times. Set ADCLK.CLKDIV, ADCLK.CLKDIV_US and ADCLK.CLKDIV_MS to set A/D clock JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 577: Sleep Mode Sample Operation

    ADENA.SLP_MD to 0. When ADSTATE.SLP_RDY = 1, the Touch Screen is have exited the SLEEP mode. Then you can do any other operations. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 578: Vbat Sample Operation

    , X2 , X2 and Y2 , Y2 , Y2 . You can use the formula (5) ,(6) to calculate the X2, Y2 value. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 579: Use Software Command Operation

    Figure 24-1 is a 6x5 keypad circuit. The blue color is for X direction network and pink color is for Y. The networks are composed by resistors and metal line. These two networks should JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 580 When no key pressing, X network and Y network is open circuit. When a key is pressed, the X network and Y network is shorted under the key position. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 581: Figure 24-1 6X5 Keypad Circuit

    When the key is not pressed, XP is open and the PEN is pulled to VDDADC, which is logic 1. When the key Kij is pressed, the circuit is: VDDADC(10kΩ resistor)R R VSSADC. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 582: Figure 24-2 Wait For Pen-Down (C=1100) Circuit

    C=0010 and C=0011 respectively. The equivalent circuits are show in Figure 24-3 and Figure 24-4, where                     JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 583: Figure 24-3 Measure X-Position (C=0010) Circuit

    C=0011, must be ≥200Ω and it better be ≥500Ω. Also consider the requirement in formula (7) and (8) = 50Ω or 100Ω, put R = 500Ω ~ 1kΩ. above, we suggest to put R JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 584 SAR A/D Controller To use the keypad, the software should set: ADENA.TCHEN = 1 ADCFG.XYZ = 10 The operation is similar to touch screen. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 585: Real Time Clock

    PWRON: Power on/off control of main power VDDRT WKUP_ Schmitt WKUP_: Wake signal after main power down VDDRT PPRST_ PPRST_: RTC power on reset and RESET-KEY reset VDDRT Schmitt input JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 586: Register Description

    : Unless otherwise stated, the reset value is for PPRST_ and Hibernating wakeup reset. WDT reset doesn‘t change the value. : The reset value can be either of 0x00000081, 0x00000091, 0x00000089, 0x00000099. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 587: Rtc Control Register (Rtccr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1* 0 0* ? 0 ? 0* JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 588 SELEXC Description OSC32K or RTCLK input clock is selected as RTCLK in rtc-hiber module. The divided EXCLK is selected as RTCLK in rtc-hiber module. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 589: Rtc Second Register (Rtcsr)

    25.2.4 RTC Regulator Register (RTCGR) RTCGR is serves as the real time clock regulator, which is used to adjust the interval of the 1Hz pulse. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 590: Hibernate Control Register (Hcr)

    Power down or power on bit. Besides writing by CPU, this bit will be set to 1 if an unknown reason main power supply off is detected. This bit JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 591: Hibernate Mode Wakeup Filter Counter Register (Hwfcr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 592: Hibernate Wakeup Control Register (Hwcr)

    0: disable 1: enable 25.2.9 HIBERNATE Wakeup Status Register (HWRSR) The HIBERNATE Wakeup Status Register is a 32-bit read/write register that reflects wakeup status bits. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 593 PPRST_ reset has occurred since last time the software clears this bit. Reserved Writing has no effect, read as zero. Wakeup Pin Status bit. The bit is cleared when chip enters hibernating JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 594: Hibernate Scratch Pattern Register (Hspr)

    This bit is read only and write to it is ignored. This bit only reset by PPRST_ and HRST_. There is an exception, when system does NOT have RTC 32Khz crystal. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 595: Clk32K Pin Control Register (Ckpcr)

    The pin value can be read by CK32RD bit or GPIO PD14 bit. The input pin should not be left floating, if pull up (CK32PULL) is disabled. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 596: Owi Pin Control Register (Owipcr)

    GPIO PF30 controls OWI pin. The pin output is set by GPIO PF30 bit. The OWI pin is output OWID bit in HIBERNATE mode. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 597: Power On Control Register (Pwroncr)

    After the true frequency of the oscillator is known, it must be split into integer and fractional portions. The integer portion of the value (minus one) is loaded into the NC1HZ field of the RTCGR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 598: Operate Mode

    PWRONCR.PWRON_EN value is 1, the power on procedure will like figure 25-2. PPRST_N PWRON 30 us Figure 25-1 Core Power On directly JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 599: Hibernate Mode

    Recover the data from flash. 25.5 Clock select There could be two clock input to RTC internal clock called rtclk. One is OSC32k clock; the other is EXCLK/512. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 600: Table 25-3 Clock Select Registers

    NOTE: If using HIBERNATE mode, MUST have both 32KHz crystal (or input 32Khz clock) and 24Mhz EXCLK crystal connected, or RTC time will be insignificant. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 601: Efuse Slave Interface (Efuse)

    EFUSE Status Register 0x00000000 0x134100D8 EFUDATA0 EFUSE Data 0 Register 0x000000?? 0x134100DC EFUDATA1 EFUSE Data 1 Register 0x00000000 0x134100E0 EFUDATA2 EFUSE Data 2 Register 0x00000000 0x134100E4 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 602: Efuse Control Register (Efuctrl)

    WR_EN Write data to EFUSE data buffer enable 1: Enable 0: Disable RD_EN Read data to EFUSE data buffer enable 1: Enable 0: Disable JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 603: Efuse Configure Register (Efucfg)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 30:16 Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 604: Efuse Data Register (Efudatan)

    1: done 0: not done *This bit only can write to 0, and write to 0 will clear this flag 26.2.4 EFUSE Data Register (EFUDATAn) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 605 2. The EFUSE 8K programmable bits are separated into seven segments as below table. The first Segment used to store 64bit random number, second segment store Ingenic chip ID, third segment used to store customer ID, forth Segment Reserved to Ingenic to program instructions, fifth segment store segment protect bit, sixth segment store HDMI key, and the last segment used to store Security boot key.

  • Page 606: Flow

    : The Security Key Segment can write use 1.3.2 flow only, The Random Number Segment will write in CP by Ingenic, others segment can write use 1.3.1 flow only. : The SC-ROM Controller can write Security Key segment 32bits once time.

  • Page 607: Read Security Key/Random Number Flow

    : The Security Key and Random Number can read use 1.3.4 flow only, others segment can read use 1.3.3 flow only. : The SC-ROM Controller can read Security Key or Random Number 32bits once time. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 608: Section 6 Peripherals

    PERIPHERAL AND CONNECTOR Section 6 PERIPHERALS JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 609: Ts Slave Interface (Tssi)

    32bit addresses are physical addresses. And detailed function of each register will be described below. The physical base address of TSSI controller is 0x134E0000. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 610: Tssi Enable Register (Tsena)

    0x00000000 0x0070 TSTC TSSI Transfer Control Register 0x00000000 0x0074 27.3.1 TSSI Enable Register (TSENA) The register TSENA is used to trigger TSSI to work. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 611: Tssi Configure Register (Tscfg)

    0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 0 Bits Name Description 16:14 F_TRIGV Specify the trigger value of FIFO. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 612 1: TSFRM is active high TSSTR_H Choose the polarity of TSSTR. 0: TSSTR is active low 1: TSSTR is active high TSFAIL_H Choose the polarity of TSFAIL. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 613: Tssi Control Register (Tsctrl)

    Writing has no effect, read as zero. F_DTRM FIFO data trigger interrupt mask. 0: enabled 1: masked F_OVRNM FIFO overrun interrupt mask. 0: enabled 1: masked JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 614: Tssi State Register (Tsstat)

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 27.3.6 TSSI PID Enable Register (TSPEN) The register TSPEN is used to control the PID filtering. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 615: Tssi Data Number Register (Tsnum)

    The register TSDTR is used to trigger the FIFO level interrupt when the current data number in the FIFO is more than the value in TSDTR. TSDTR 0x001C 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 616: Tssi Pid Filter Registers (Tspid0~15)

    It can be written by software and coped from the descriptor. Software should write the descriptor address before enable the DMA, and only the first DA needed if LINK enabled. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 617: Tssi Dma Target Address (Tsdta)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 618: Tsst Dma Status (Tsdst)

    Write has no effect, read as zero. TEND Transfer End Flag. 0: Transfer is not finished 1: Transfer is finished Write 0 will clear this field. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 619: Tssi Transfer Control Register (Tstc)

    0: TSSI calculates the priority according to the fifo status 1: TSSI calculates the priority according to OP which is configured by software Emergency Mode Enable Control. 0: Emergency Mode Disable JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 620: Tssi Timing

    Set TSENA.DMA_EN to 1 or 0 to decide whether to use the DMA mode or not. Write 0x00 to TSSTAT clear all interrupt flag. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 621: Tssi Operation With Pid Filtering Function

    Change TSPID registers and then set TSPID to enable the PID filter. 10 When PID in TS package is equal to the valve in TSPID register, the TS package will be getting. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 622: General-Purpose I/O Ports

    (U/D) Note sd0(io) sd1(io) sd2(io) sd3(io) sd4(io) msc0_d4(io) sd5(io) msc0_d5(io) sd6(io) msc0_d6(io) sd7(io) msc0_d7(io) rd_(o) rst-pe we_(o) rst-pe we_(o) rst-pe fre_(o) msc0_clk(o) ssi0_clk(o) rst-pe JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 623: Gpio Port B Summary

    Table 28-2 GPIO Port B summary Pull Shared Function Port Selected by (U/D) Note sa0_cl(o) rst-pe sa1_al(o) rst-pe sa2(o) sa3(o) sa4(o) sa5(o) ssi0_clk(o) cim_pclk(i) cim_hsyn(i) cim_vsyn(i) cim_mclk(o) cim_d0(i) cim_d1(i) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 624: Gpio Port C Summary

    Pull Shared Function Port Selected by (U/D) Note lcd_b0(o) lcd_rev(o) lcd_b1(o) lcd_ps(o) lcd_b2(o) lcd_b3(o) lcd_b4(o) lcd_b5(o) lcd_b6(o) lcd_b7(o) lcd_pclk(o) lcd_de(o) lcd_g0(o) lcd_spl(o) uart4_txd(o) rst-pe JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 625: Gpio Port D Summary

    (U/D) Note pcm0_do(o) pcm0_clk(io) pcm0_syn(io) pcm0_di(i) ps2_mclk(io) uart2_rts_(o) ps2_mdata(io) uart2_cts_(i) ps2_kclk(io) uart2_rxd(i) ps2_kdata(io) uart2_txd(o) clk48m(i) pwm6(io) SMB3_sda(io) pwm7(io) SMB3_sck(io) uart3_rxd(i) bclk0(io) lrclk0(io) exclk(o) rst-pe JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 626: Gpio Port E Summary

    Shared Function Port Selected by (U/D) Note pwm0(io) pwm1(o) pwm2(o) pwm3(io) SMB4_sda(io) pwm4(io) SMB4_sck(io) pwm5(io) uart3_txd(o) sclk_rstn(o) rst-pe aic0_sdati(i) aic0_sdato(o) uart3_cts_(i) bclk0_ad(io) uart3_rts_(o) lrclk0_ad(io) rst-pe drvvbus(o) rst-pe JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 627: Gpio Port F Summary

    Shared Function Port Selected by (U/D) Note uart0_rxd(i) gps_clk(i) uart0_cts_(i) gps_mag(i) rst-pe uart0_rts_(o) gps_sig(i) rst-pe uart0_txd(o) rst-pe cim_d0(i) cim_d1(i) cim_mclk(o) cim_pclk(i) cim_hsyn(i) cim_vsyn(i) cim_d2(i) cim_d3(i) cim_d4(i) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 628 If NAND flash is used, this pin must be used as NAND CLE. If NAND flash is used, this pin must be used as NAND ALE. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 629: Registers Description

    PADRVL 0x00000000 0x10010080 PADRVLS 0x???????? 0x10010084 PADRVLC 0x???????? 0x10010088 PADIR 0x00000000 0x10010090 PADIRS 0x???????? 0x10010094 PADIRC 0x???????? 0x10010098 PADRVH 0x00000000 0x100100A0 PADRVHS 0x???????? 0x100100A4 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 630 PORT C Pattern 1 Register 0xFFFFFFFF 0x10010230 PCPAT1S PORT C Pattern 1 Set Register 0x???????? 0x10010234 PCPAT1C PORT C Pattern 1 Clear Register 0x???????? 0x10010238 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 631 PDPENC PORT D PULL Disable Clear Register 0x???????? 0x10010378 PDDRVL 0x00000000 0x10010380 PDDRVLS 0x???????? 0x10010384 PDDRVLC 0x???????? 0x10010388 PDDIR 0x00000000 0x10010390 PDDIRS 0x???????? 0x10010394 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 632 PORT F Interrupt Mask Clear Register 0x???????? 0x10010528 PFPAT1 PORT F Pattern 1 Register 0xFFFFFFFF 0x10010530 PFPAT1S PORT F Pattern 1 Set Register 0x???????? 0x10010534 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 633: Port Pin Level Registers (Pxpin)

    Where n = 0 ~ 31 and PINL n = PINL0 ~ PINL31. The PORT PIN level can be read by reading PINL n bit in register PXPIN. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 634: Port Interrupt Registers (Pxint)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 635: Port Mask Registers (Pxmsk)

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 636: Port Mask Clear Registers (Pxmskc)

    1: Edge trigger interrupt When PINT n = 0 and PMSK = 0 (Device function): 0: Corresponding pin is used as device 0 or device 1 function JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 637: Port Pat1/Direction Set Registers (Pxpat1S)

    Writing 0 to PAT1C n will no use. 28.2.11 PORT PAT0/Data Registers (PxPAT0) PAPAT0, PBPAT0, PCPAT0, PDPAT0, PEPAT0 and PFPAT0 are six 32-bit PORT Pattern 0 or DATA JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 638: Port Pat0/Data Set Registers (Pxpat0S)

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 639: Port Pat0/Data Clear Registers (Pxpat0C)

    FLAG n is interrupt flag bit for checking the interrupt whether to happen. When GPIO is used as interrupt function and the interrupt happened, the FLAG n in PXFLG will be set to 1. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 640: Port Flag Clear Registers (Pxflgc)

    28.2.17 PORT PULL Set Registers (PxPES) PAPES, PBPES, PCPES, PDPES, PEPES and PFPES are six 32-bit PORT PULL set registers. They are write-only registers. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 641: Port Pull Clear Registers (Pxpec)

    1 1 0 1 Port is high level triggered interrupt input. Interrupt is masked. Flag is recorded. 1 1 1 0 Port is fall edge triggered interrupt input. Interrupt is masked. Flag is recorded. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 642 0 1 0 0 Port is GPIO output 0. 0 1 0 1 Port is GPIO output 1. 0 1 1 ？ Port is GPIO input. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 643: Smb Controller

    RC time constant of the bus. Totally speaking, for standard-mode SMB-bus system, the pull up resistor depends on following parameters: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 644: Registers

    SMB RxFIFO Threshold 4 bits SMBTXTL 0x3C SMB TxFIFO Threshold 4 bits SMBCINT 0x40 Clear Interrupts 1 bit SMBCRXUF 0x44 Clear RXUF Interrupt 1 bit JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 645: Registers And Fields Description

    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 Bits Name Description JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 646 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMBTAR 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 Bits Name Description JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 647 The SMBSAR holds the slave address when the SMB is operating as a slave. For 7-bit addressing, only SMBSAR[6:0] is used. This register can be written only when the SMB interface is disabled. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 648 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMBSHCNT 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 Bits Name Description JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 649 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMBFHCNT 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 Bits Name Description JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 650 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 651 When the SMBENB bit 0 is 0, the TX FIFO is flushed and held in reset. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 652 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 Bits Name Description JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 653 Reserved Writing has no effect, read as zero. TXTL Transmit FIFO Threshold Level. Controls the level of entries that trigger the TxFIFO empty interrupt. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 654 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 655 SMBINTST register. 29.2.2.18 SMBCTXABT SMBCTXABT BASE + 0x54 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 656 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 15:1 Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 657 SMBINTST register. 29.2.2.23 SMBCGC SMBCGC BASE + 0x68 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 658 When the SMB is disabled by writing 0 in bit 0 of the SMBENB register:  Bits 1 and 2 are set to 1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 659 The OR of SLVACT and MSTACT bits. 29.2.2.26 SMBABTSRC This register has 16 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 660 NOTE: SMB can be both master and slave at the same time. Reset value: 0x0. ABRT_MASTE 1: User tries to initiate a Master operation with the Master mode R_DIS disabled. Reset value: 0x0. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 661 ABRT_10ADD 1: Master is in 10-bit address mode and the first 10-bit address byte R1_NOACK was not acknowledged by any slave. Reset value: 0x0. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 662 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 15:5 Reserved Writing has no effect, read as zero. TDLR DMA Transmit Data Level. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 663 Semiconductor, THE SMB-BUS SPECIFICATION, Version 2.1. Jan, 2000‘) SMBSDASU BASE + 0x94 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 664 If SMBENB has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as ‗0‘. SMBENBST BASE + 0x9C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 665 SMB bus is idle. The CPU can safely read this bit when IC_EN (bit 0) is read as JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 666: Operating Flow

    Slave, but not both simultaneously. This is achieved by ensuring that bit 6 (SMBSLAVE_DISABLE) and 0 (SMBMASTER_MODE) of the SMBCON register are never set JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 667: Smb Behavior

    29.3.2 Master Mode Operation This section includes the following topics:  ―Initial Configuration‖  ―Dynamic SMBTAR or SMB10BITADDR_MASTER Update‖  ―Master Transmit and Master Receive‖ JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 668 12) bit fields of the SMBTAR register. You can dynamically write to the SMBTAR register provided the following conditions are met: SMB is not enabled (SMBENB=0); JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 669: Slave Mode Operation

    NOTE: Depending on the reset values chosen, steps 2 and 3 may not be necessary because the reset values can be configured. For instance, if the device is only going to be a JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 670 There is no further action required from software. The timing interval used should be similar to that described in the previous step for the JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 671 STOP condition. 29.3.3.4 Slave-Transfer Operation For Bulk Transfers In the standard SMB protocol, all transactions are single byte transactions and the programmer JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 672: Disabling Smb

    NOTE: This step can be ignored if SMB is programmed to operate as an SMB slave only. The variable POLL_COUNT is initialized to zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 673 If POLL_COUNT >= MAX_T_POLL_COUNT, exit with the relevant error code. If SMBENBST[0] is 1, then sleep for tSMB_poll and proceed to the previous step. Otherwise, exit with a relevant success code. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 674: Synchronous Serial Interface

    Input Receive data (serial data in) SSI_CLK is the bit-rate clock driven from the SSI to the peripheral. SSI_CLK is toggled only when data JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 675: Register Description

    0x1004401C NOTE: There two SSI controller. SSI0 whose base address is 0x100430xx and SSI1 whose base address is 0x100440xx. 30.3.2 SSI Data Register (SSIDR) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 676: Ssi Control Register0 (Ssicr0)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:20 Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 677 0: receive continue 1: receive finished 0: don‘t auto clear under flag, software clear under EACLRU 1: software auto clear under flag when tfifo don‘t empty JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 678: Ssi Control Register1 (Ssicr1)

    FRMHL Frame valid level select, FRMHL [1: 0] correspond to SSI_CE2_ and SSI_CE_ respectively. FRMHL[1:0] Description SSI_CE_ is low level valid and Initial value JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 679 SSI waits for data filling; SSI_CLK and SSI_CE_ /SSI_CE2_ keeps asserted, SSI_CLK stop at the current level NOTE: For TxFIFO empty before any transfer after SSI enabled, if JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 680 SSI_CE_ /SSI_CE2_ goes valid, it is initial value 1: The leading edge of SSI_CLK is used to drive data onto SSI_DT after the SSI_CE_ /SSI_CE2_ goes valid JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 681: Ssi Status Register (Ssisr)

    SSICR1.RTRG. 0: The data in receive-FIFO is less than the condition set by SSICR1.RTRG 1: The data in receive-FIFO meets the condition set by JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 682: Ssi Interval Time Control Register (Ssiitr)

    Interval time = [CNTCLK clock period] * [Value of IVLTM] + 3 * device_clock period When SSIITR.CNTCLK = 1:  Interval time [CNTCLK clock period] * [Value of IVLTM + 1] + 1 * device_clock period; JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 683: Ssi Interval Character-Per-Frame Control Register (Ssiicr)

    Device clock is generated in CPM module. The value in SSIGR can be set from 0 to 255, and initialized to 0x0000 on power-on reset. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 684: Ssi Receive Counter Register (Ssircnt)

    Four signals are used to transfer data between the processor and external peripheral. The SSI supports three formats: Motorola SPI, Texas Instruments SSP, and National Microwire. Although they JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 685: Motorola's Spi Format Details

    30.5.1 Motorola’s SPI Format Details 30.5.1.1 General Single Transfer Formats The figures below show the timing of general single transfer format. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 686: Figure 30-1 Spi Single Character Transfer Format (Pha = 0)

    SSI_CE_ / SSI_CE2_ negated one SSI_CLK period after last clock change edge; when SSICR1.TFVCK  B‘00 or SSICR1.TCKFI  B‘00, 1/2/3 more clock cycles are inserted. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 687: Figure 30-3 Spi Back-To-Back Transfer Format

    (SSIICR), then repeats the operation. When SSICR0.RFINE = 1, if transmit-FIFO is still empty after the interval time, receive-only transfer will occur. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 688: Figure 30-4 Spi Frame Interval Mode Transfer Format (Itfrm = 0, Lfst = 0)

    … SSI_CE_/ SSI_CE2_ (SSICR1.FRMHLn = … SSI_DT … SSI_DR SSI_GPC Figure 30-4 SPI Frame Interval Mode Transfer Format (ITFRM = 0, LFST = 0) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 689: Ti's Ssp Format Details

    MSB first or LSB first. At the end of the transfer, SSI_DT retains the value of the last bit sent through the next idle period. 1 SSI_CLK period … SSI_CLK … SSI_CE_ SSI_DT SSI_DR Figure 30-6 TI’s SSP Single Transfer Format JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 690: National Microwire Format Details

    … … … … … … … JZ4780 Mobile Application Processor Programming Manual … … … … … Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved. … … … … … … … … … … … …...

  • Page 691: Figure 30-8 National Microwire Format 1 Single Transfer

    … … SSI_CLK SSI_CE_ 1 -- 16-bit command … SSI_DT 2 -- 17-bit data … SSI_DR Figure 30-10 National Microwire Format 2 Read Timing JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 692: Interrupt Operation

    Either SSISR.TFHE or SSISR.RFHF can activate DMA transferring when corresponding individual interrupt mask bit in SSICR0 is cleared (masked) and DMA is enabled and configured. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 693: Uart Interface

    All UART register 32-bit access address is physical address. When ULCR.DLAB is 0, URBR, UTHR and UIER can be accessed; When ULCR.DLAB is 1, UDLLR and UDLHR can be accessed. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 694: Register Mapping

    If ULSR.DRY is 0, don‘t read URBR, otherwise wrong operation may occur. URBR 0x000 (DLAB = 0) 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 695: Uart Transmit Hold Register (Uthr)

    0x000 (DLAB = 1) 7 6 5 4 3 2 1 0 Divisor Latch Low 8-bit 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 696: Uart Interrupt Enable Register (Uier)

    1: Enable the receive data ready interrupt 31.2.6 UART Interrupt Identification Register (UIIR) The read-only UART Interrupt Identification Register (UIIR) records the prioritized pending interrupt JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 697: Table 31-3 Uart Interrupt Identification Register Description

    Overrun, Parity, Frame Reading ULSR or empty all Status Error, Break Interrupt, the error characters in DMA and FIFO Error (DMA mode mode only) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 698: Uart Fifo Control Register (Ufcr)

    UART Module Enable. 0: Disable UART 1: Enable UART DMA Mode Enable. 0: Disable DMA mode 1: Enable DMA mode TFRT Transmit Holding Register Reset. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 699: Uart Line Control Register (Ulcr)

    If PARE = 0, PARM is ignored. 0: Odd parity 1: Even parity PARE Parity Enable. Enables a parity bit to be generated on transmission or checked on JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 700: Uart Line Status Register (Ulsr)

    Set when both UTHR and shift register are empty. It is cleared when either the UTHR or the shift register contains a data character. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 701 0: No parity error 1: Parity error has occurred OVER Overrun Error. Set when both receive buffer and shifter are full and new data is received JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 702: Uart Modem Control Register (Umcr)

    RTS bit of the UMCR is connected to CTS bit of UMSR respectively. Loopback mode must be selected before the UART is enabled. 0: Normal operation mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 703: Uart Modem Status Register (Umsr)

    This Scratchpad register is used as a scratch register for the programmer and has no effect on the UART. USPR 0x01C 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 704: Infrared Selection Register (Isr)

    This bit is used to select TXD output pin is processed by the IrDA encoder before it is fed to the device pin (XMITIR = 1) or bypass IrDA JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 705: Uart M Register (Umr)

    For the detail to see For any frequency clock to use the Uart. 31.2.16 UART RXFIFO Counter Register (URCR) URCR 0x040 7 6 5 4 3 2 1 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 706: Uart Txfifo Counter Register (Utcr)

    In FIFO mode, set FME bit of UFCR to 1, reset receive and transmit FIFO, then initialize the UART as described below: Clear UFCR.UME to 0. Set value in UDLL/UDHR to generate the baud rate clock. Set data format in ULCR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 707: Data Transmission

    A sample error handling flow is as the following: If ULSR.FIFOE = 1, it means there is receive error in received data, then check what error it JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 708: Modem Transfer

    In the IrDA 1.1 specification, communication must start up at the rate of 9600bps, but then allows the JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 709: For Any Frequency Clock To Use The Uart

    Stop Stop Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 1 Bit 2 Cycle N JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 710 To set UACR value you must ensure that the max error of each bit should be less than 0.5P For example：M -M =0.15; M+1-M =0.85; Write 8 to UMR, Write 0x408 to UACR ： cycle/bit M，M，M，M+1，M，M，M，M，M，M，M+1，M ： UACR JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 711: Mmc/Sd Ce-Ata Controller

     32.3 Pins Description  MSC_CLK, output, host to card clock signal.  MSC_CMD, inout, bidirectional command/response signal.  MSC_DAT[7:0], inout, bidirectional data bus. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 712: Block Diagram

    CMD line. Each command token is preceded by a start bit (‗0‘) and succeeded by an end bit (‗1‘). The total length is 48 bits and protected by CRC bits. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 713: Register Description

    Address Offset Access Size MSC_CTRL 0x0000 0x00 MSC_STAT 0x00000040 0x04 MSC_CLKRT 0x0000 0x08 MSC_CMDAT 0x00000000 0x0c MSC_RESTO 0x100 0x10 MSC_RDTO 0xFFFFFF 0x14 MSC_BLKLEN 0x0000 0x18 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 714: Msc Control Register (Msc_Ctrl)

    CE_ATA device when set, host sends CCSD to CE_ATA device. Software set the bit only if current command is expecting CCS and interrupts are JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 715 1: Start the new operation CLOCK_CTRL These bits are used to start or stop clock. 00: Do nothing 01: Stop MMC/SD clock 10: Start MMC/SD clock 11: Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 716: Msc Control 2 Register (Msc_Ctrl2)

    3.3V regulator output should be stable within 5ms when changing voltage from 1.8V to 3.3V. Speed Mode Selection 000: Default speed 001: High speed 010: SDR12 011: SDR25 100: SDR50 Others: reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 717: Msc Status Register (Msc_Stat)

    1: Boot acknowledge received. DMAEND Indicates that the DMA has finished the current transfer. IS_RESETTING MSC is resetting after power up or MSC_CTRL[RESET] is written with 1. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 718 0: No error on received data 1: CRC error occurred on received data CRC_WRITE_ERROR Write CRC error. 00: No error on transmission of data JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 719: Msc Clock Rate Register (Msc_Clkrt)

    This field must be set to 0 when the controller works during normal writing or reading. 32.6.5 MSC Command and Data Control Register (MSC_CMDAT) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 720 1: Boot acknowledge pattern is expected BOOT_MODE Boot mode operation selection. 0: Mandatory boot operation 1: Alternative boot operation 23:19 Reserved Writing has no effect, read as zero. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 721 It is auto cleared 0 by hardware. 10:9 BUS_WIDTH Specifies the width of the data bus. 00: 1-bit 01: Reserved 10: 4-bit 11: 8bit JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 722: Msc Response Time Out Register (Msc_Resto)

    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES_TO 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 723: Msc Read Time Out Register (Msc_Rdto)

    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 724: Msc Successfully-Transferred Blocks Count Register (Msc_Snob)

    Writing has no effect. AUTO_CMD23_DONE Mask the interrupt AUTO_CMD23_DONE. 0: Not masked 1: Masked Mask the interrupt of SVS 0: Not masked 1: Masked JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 725 Mask the interrupt from the SD I/O card. 0: Not masked 1: Masked TXFIFO_WR_REQ Mask the Transmit FIFO write request interrupt. 0: Not masked 1: Masked JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 726: Msc Interrupt Flag Register (Msc_Iflg)

    0: the interrupt is not detected 1: the interrupt is detected Write 1 to clear. 28:24 PIN_LEVEL Indicates PIN_LEVEL interrupt. 0: the interrupt is not detected JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 727 1: the interrupt is detected CRC_WRITE_ERR Indicate CRC write error interrupt. 0: the interrupt is not detected 1: the interrupt is detected TIME_OUT_RES Indicate response time out interrupt. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 728: Msc Command Index Register (Msc_Cmd)

    32.6.13 MSC Command Index Register (MSC_CMD) MSC_CMD 0x2C 7 6 5 4 3 2 1 0 CMD_INDEX 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 729: Msc Command Argument Register (Msc_Arg)

    The MSC_RXFIFO is used to read the data from a card. It is read-only to the software, and is read on 32-bit boundary. The size of this FIFO is 128 x 32-bit. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 730: Msc Transmit Fifo Port Register (Msc_Txfifo)

    1: CMD and data are driven by clock rising edge which is 1ns delayed by MSC_CLK 2: CMD and data are driven by clock rising edge which is 1/4 phase delayed by MSC_CLK JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 731: Msc Dma Control Register (Msc_Dmac)

    10b: The lowest 2 bit of the data transfer start address is 10b 11b: The lowest 2 bit of the data transfer start address is 11b JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 732: Msc Dma Descriptor Address Register (Msc_Dmanda)

    SDMA Data Physical Address The data address of the current descriptor will be copied to this field. The SDMA will increment it during the data transfer automatically. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 733: Msc Dma Data Length Register (Msc_Dmalen)

    This bit should be set to 1b if the data address is not word-aligned. Reserved It has no use in the current version. ENDI Interrupt Enable for Current DMA Transfer End JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 734: Msc Rtfifo Data Counter Register(Msc_Rtcnt)

    16-bit response FIFO that is 8 entries deep, and one 32-bit receive/transmit data FIFOs that are 16 entries deep. The registers and FIFOs are accessible by the JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 735: Msc Reset

    For SD card, Identification process start at clock rate Fod, while CMD line output drives are push-pull drivers instead of open-drain. After the bus is activated the host will request the cards to send their JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 736: Card Access

    CRC protected. If a part of the CSD or CID register is stored in ROM, then this unchangeable part must match the corresponding part of the receive buffer. If this match fails, then the JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 737 Identification of these sectors is accomplished with the TAG_* commands. Either an arbitrary set of sectors within a single erase group, or an arbitrary selection of erase groups may be erase at one time, JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 738: Protection Management

    It is the responsibility of the host to protect the card. The position of the write protect switch is un-known to the internal circuitry of the card. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 739: Table 32-4 Command Data Block Structure

    Select a card (CMD7), if not previously selected already. Define the block length (CMD16), given by the 8bit card lock/unlock mode, the 8 bits JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 740 If the password is not correct then LOCK_UNLOCK_FAILED error bit will be set in the status register. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 741 PWD_LEN register content and the locked card will get unlocked. An attempt to force erase on an unlocked card will fail and LOCK_UNLOCK_FAILED error bit will be set in the status register. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 742: Card Status

    The transferred block length is not allowed for this, or the number of transferred bytes does not match the block length. 0: No Error 1: Error JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 743 E R X A general or an unknown error occurred during the operation. 0: No Error 1: Error UNDERRUN The card could not sustain data JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 744 0: idle 1: ready 2: ident 3: stby 4: tran 5: data 6: rcv 7: prg 8 : dis (9 – 15) : rsv JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 745: Sd Status

    10: In the mode 508:496 Reserved. 495:480 SD_CARD_TYPE All 0, is SD Memory cards. 479:448 SIZE_OF_PROTECTED_AREA Size of protected area. 447:312 Reserved. 311:0 Reserved for manufacturer. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 746: Sdio

    IO function zero does not support suspend/resume. The procedure used to perform the Suspend/Resume operation on the SD bus is: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 747: Clock Control

    Command 13 will be interpreted as the non standard ACMD13 but, command 7 as the standard CMD7. In order to use one of the manufacturer specific ACMD‘s the host will: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 748: Mmc/Sd Controller Operation

    MSC_RES is bit [135:8] and needs reading 8 times. The FIFO does not contain the response CRC. The status of the CRC check is in the status register, MSC_STAT. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 749: Dma And Program I/O

    A SDMA descriptor includes 4 words. Word 1: The physical address of the next SDMA descriptor. Bits Name Description 31:0 Next descriptor physical address. It should be 4-word aligned. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 750 Step 8: Waiting the DMAEND interrupt (if interrupt is used) or status (if interrupt is not used) Step 9: Disable the SDMA by configuring MSC_DMAC.DMAEN to 0b JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 751: Start And Stop Clock

    Wait until MSC_STAT[CLK_EN] becomes zero. To start the clock the software writes MSC_CTRL with 0x02. 32.8.4 Software Reset Reset includes the MSC reset and the card reset. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 752: Voltage Validation And Card Registry

    Step 1. Check whether SDIO card is inserted. Step 2. Check whether SDMEM card is inserted. Step 3. Check whether MMC cards are inserted. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 753 Because there may be several MMC card, so some steps (5 ~ 8) should be repeated several times. The commands are sent as follows: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 754: Single Data Block Write

    To address the same card, the software must wait for MSC_IFLG [PROG_DONE] interrupt. This ensures that the card is not in the busy state. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 755: Single Block Read

    If multiple block write with pre-defined block count (refer to MMC spec v-3.3) is used, CMD12 should not be sent. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 756: Multiple Block Read

    If multiple block read with pre-defined block count (refer to MMC spec v-3.3) is used, CMD12 should not be sent. For SDIO card, CMD53 (multiple_block_read) is also similar, but when IO abort (CMD52) is sent, MSC_CMDAT [IO_ABORT] should be 1. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 757: Stream Write (Mmc)

    Wait for the MSC_IFLG [PRG_DONE] interrupt. This interrupt indicates that the card has finished programming. Certainly software may start another command sequence on a different card. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 758: Stream Read (Mmc)

    For CMD7 (SELECT/DESELECT_CARD), CMD12 (STOP_TRANSMISSION) and CMD38 (ERASE), the following registers must be set before the operation is started: Update the MSC_CMDAT register as follows: Write 0x01 to the MSC_CMDAT [RESPONSE_FORMAT]. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 759: Sdio Suspend/Resume

    The proposed method is to use interrupt. Generally there are fixed necessary steps to finish each command. The steps are as follows: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 760: Table 32-9 The Mapping Between Commands And Steps

    WRITE_SINGLE_BLOCK CMD25 WRITE_MULTIPLE_BLOCK Open-ended CMD25 WRITE_MULTIPLE_BLOCK Predefine blocks CMD26 PROGRAM_CID CMD27 PROGRAM_CSD CMD28 SET_WRITE_PROT CMD29 CLR_WRITE_PROT CMD30 SEND_WRITE_PROT CMD32 ERASE_WR_BLOCK_START CMD33 ERASE_WR_BLOCK_END CMD35 ERASE_GROUP_START JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 761 NOTE: For stream read/write, STOP_CMD is sent after finishing data transfer. For write, STOP_CMD is with the last six bytes. For read, STOP_CMD is sent after receiving data and card sends some data which MSC ignores. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 762: Otg Controller

    Registers (CSRs) through the AHB Slave interface. These registers are 32 bits wide, the addresses are 32- bit block aligned and the base address is 0x13500000. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 763: Csr Memory Map

    11000h 20000h DFIFO Direct Access to Data FIFO RAM dubug for Debugging (128 KB) read/write to this 3FFFFh Figure 33-1 OTG CSR Memory Map JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 764: Register Maps

    "User HW Config2 Register (GHWCFG2)" GHWCFG3 04Ch "User HW Config3 Register (GHWCFG3)" GHWCFG4 050h "User HW Config4 Register (GHWCFG4)" GLPMCFG 054h "Core LPM Configuration Register (GLPMCFG)" JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 765: Host Mode Csr Map

    Host Channel-n DMA Buffer Address Register (HCDMABn) 6F0-7FFh Reserved 33.4.4 Device Mode CSR Map These registers must be programmed every time the core changes to Device mode. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 766: Table 33-4 Device Mode Csr Map (800H-Bffh)

    Device Control IN Endpoint 0 Control Register (DIEPCTL0) 904h Reserved DIEPCTLn 920h-AE0h Device Endpoint-n Control Register (DIEPCTLn/DOEPCTLn) DIEPINTn Device Endpoint-n Interrupt Register (DIEPINTn/DOEPINTn) 90Ch Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 767: Data Fifo (Dfifo) Access Register Map

    Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access 2000h-2FFCh WO/RO Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 768: Interrupt Hierarchy

    Device OUT Endpoint 15/Host IN Channel 15: DFIFO Read Access 33.4.6 Interrupt Hierarchy Following figure displays the DWC_otg interrupt hierarchy. Figure 33-2 Interrupt Hierarchy JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 769: Register Descriptions

    The Access column of each register description that follows specifies how the application and the core can access the register fields of the CSRs. The following conventions are used: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 770: Overview Of Commonly Used Register Bits

    This section provides an overview of the commonly used registers and bits. For a complete description of all the registers, see the corresponding sections. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 771: Table 33-6 List Of Commonly Used Register Bits

    After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 772 DMA mode In non Scatter/Gather DMA mode, this bit is reserved. FS- and LS-Only The application uses this bit to control the core's enumeration JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 773 25,50 or 75% of (micro)frame.  When any periodic endpoints are active, the internal DMA engine allocates the specified amount of time in fetching JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 774 Applies to interrupt/bulk IN and OUT endpoints only. (SetD0PID) Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 775: Global Registers

     Bit 22 - rid_c SUPPORT These bits are valid only if OTG_BC_SUPPORT=1, =1 and 0 otherwise they are reserved. otherwise. Reserved Host and JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 776 1'b1: The DWC_otg core is in B-Device mode 15:12 Reserved Host and Device Device HNP Enabled (DevHNPEn) Device 1'b0 The application sets this bit when it successfully receives Only JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 777 A-Peripheral Session Valid OverrideValue (AvalidOvVal) Host only 1'b0 This bit is used to set the Override value for Avalid signal when GOTGCTL.AvalidOvEn is set. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 778 1'b0: No session request  1'b1: Session request Session Request Success (SesReqScs) Device 1'b0 The core sets this bit when a session request initiation is only successful. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 779: Table 33-8 Interrupt Register: Gotgint

    Session Request Success Status Change Host and 1'b0 R_SS_W (SesReqSucStsChng) Device The core sets this bit on the success or failure of a JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 780: Table 33-9 Ahb Configuration Register: Gahbcfg

    This bit is programmed to enable the System DMA Done Device functionality for all the DMA write Transactions corresponding to the Channel/Endpoint. This bit is valid only when GAHBCFG.RemMemSupp is set to 1. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 781 Device Periodic TxFIFO Empty Level (PTxFEmpLvl) Host only 1'b0 Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.PTxFEmp) is JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 782  4'b0000: 1 word  4'b0001: 4 words  4'b0010: 8 words  4'b0011: 16 words  4'b0100: 32 words  4'b0101: 64 words JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 783: Table 33-10 Usb Configuration Register: Gusbcfg

    After setting the force bit, the application must wait at least 25 ms before the change to take effect. When the simulation is in scale down mode, waiting for 500 µs is sufficient. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 784 Vbus State in the RX CMD. Please refer to the ULPI Specification for more detail.  1'b0: Complement Output signal is qualified with the JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 785 This bit sets the AutoResume bit in the Interface Control Device register on the ULPIPHY.  1'b0: PHY does not use AutoResume feature.  1'b1: PHY uses AutoResume feature. This bit is invalid. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 786 USB turnaround time is not critical, these bits can be programmed to a larger value. HNP-Capable (HNPCap) Host and 1'h0 RO/R_W The application uses this bit to control the DWC_otg Device JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 787 ULPI or UTMI+ Select (ULPI_UTMI_Sel) Host and 1'h0 RO/R_W The application uses this bit to select either a UTMI+ Device interface or ULPI Interface.  1'b0: UTMI+ Interface JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 788 PHY clock you are using. 33.5.3.5 Reset Register (GRSTCTL)  Offset: 010h The application uses this register to reset various hardware features inside the core. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 789: Table 33-11 Reset Register: Grstctl

    FIFO operation TXFIFO 15 flush in device mode when in dedicated FIFO mode  5'h10: Flush all the transmit FIFOs in device or host mode. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 790 R_WS_S Resets the hclk and phy_clock domains as follows: Device  Clears the interrupts and all the CSR registers except the following register bits: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 791 PHY selection bits in the USB configuration registers listed above. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 792: Table 33-12 Interrupt Register: Gintsts

    In Host mode, this interrupt is asserted when a session Device request is detected from the device. In Host mode, this interrupt is asserted when a session request is detected JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 793 HCINTn register to clear this bit. Host Port Interrupt (PrtInt) Host 1'b0 The core sets this bit to indicate a change in port status of Only JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 794 FIFO empty" interrupt when clearing a global IN NAK handshake. Incomplete Periodic Transfer (incomplP) Device In Host mode, the core sets this interrupt bit when there are only JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 795 IN token has been received for a non-periodic endpoint, but the data for another endpoint is present in the top of the Non-periodic Transmit FIFO and JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 796 R_SS_W This field is used only if the Carkit interface was enabled. Otherwise, reads return 0. Device Global OUT NAK Effective (GOUTNakEff) Device 1'b0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 797 SOF has been sent (in case of host mode) or SOF has been received JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 798: Table 33-13 Interrupt Mask Register: Gintmsk

    Resume/Remote Wakeup Detected Interrupt Mask Host and 1'b0 (WkUpIntMsk) Device Session Request/New Session Detected Interrupt Mask Host and 1'b0 (SessReqIntMsk) Device Disconnect Detected Interrupt Mask (DisconnIntMsk) Host 1'b0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 799 Enumeration Done Mask (EnumDoneMsk) Device 1'b0 only USB Reset Mask (USBRstMsk) Device 1'b0 only USB Suspend Mask (USBSuspMsk) Device 1'b0 only Early Suspend Mask (ErlySuspMsk) Device 1'b0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 800 Do not read this register's reset value before configuring the core because the read value is "X" in the simulation. Following table shows Host mode. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 801: Table 33-14 Host Mode Receive Status Debug Read/Status Read And Pop Registers

    Data PID (DPID) 2'b0 Indicates the Data PID of the received OUT data packet  2'b00: DATA0  2'b10: DATA1  2'b01: DATA2  2'b11: MDATA JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 802: Table 33-16 Receive Fifo Size Register: Grxfsiz

    This field contains the memory start address for Non-periodic Transmit FIFO RAM.  The application can write a new value in this field. Programmed values must not exceed the power-on value set JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 803: Table 33-18 Non-Periodic Transmit Fifo Size Register: Gnptxfsiz

    OUT requests in Host mode. Device mode has only IN requests.  8'h0: Non-periodic Transmit Request Queue is full  8'h1: 1 location available  8'h2: 2 locations available JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 804: Table 33-20 User Hw Config1 Register: Ghwcfg1

    2'b11: Reserved This field is configured using "Name: OTG_EP_DIR_1(n)". 33.5.3.13 User HW Config2 Register (GHWCFG2)  Offset: 048h This register contains configuration options selected. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 805: Table 33-21 User Hw Config2 Register: Ghwcfg2

    Periodic OUT Channels Supported in Host Mode (PerioSupport) Configurable  1'b0: No  1'b1: Yes This field is configured using parameter "Name: OTG_EN_PERIO_HOST". 17:14 Number of Host Channels (NumHstChnl) Configurable JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 806 3'b001: SRP-Capable OTG (Host and Device)  3'b010: Non-HNP and Non-SRP Capable OTG (Host and Device)  3'b011: SRP-Capable Device  3'b100: Non-OTG Device JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 807: Table 33-22 User Hw Config3 Register: Ghwcfg3

    0 - No ADP logic present with HS OTG controller  1- ADP logic is present along with HS OTG controller. Reset Style for Clocked always Blocks in RTL (RstType) Configurable JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 808 Others: Reserved This field is configured using parameter "Name: OTG_PACKET_COUNT_WIDTH". Width of Transfer Size Counters (XferSizeWidth) Configurable  4'b0000: 11 bits  4'b0001: 12 bits JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 809: Table 33-23 User Hw Config4 Register: Ghwcfg4

    This field is configured using parameter "Name: OTG_EN_DED_TX_FIFO". session_end Filter Enabled (SessEndFltr) Configurable  1'b0: No filter  1'b1: Filter This field is configured using parameter "Name: OTG_EN_SESSIONEND_FILTER" JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 810 "Name: OTG_EN_PWROPT". Minimum AHB Frequency Less Than 60 MHz (AhbFreq) Configurable  1'b0: No  1'b1: Yes This field is configured using parameter "Name: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 811: Table 33-24 Global Dfifo Software Config Register: Gdfifocfg

    Maximum value is 3648 15:0 Host Periodic TxFIFO Start Address (PTxFStAddr) Configurable RO/R_W The power-on reset value of this register is the sum of the Largest Rx JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 812: Table 33-26 Device Periodic Transmit Fifo-N Register: Dptxfsizn

    If at POR, the calculated value (C) exceeds 65535, then the Reset value becomes Reset Value(A) = (C - 65536). 33.5.3.19 Device IN Endpoint Transmit FIFO Size Register: (DIEPTXFn) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 813: Host Mode Registers

    33.5.4.1 Host Configuration Register (HCFG)  Offset: 400h This register configures the core after power-on. Do not make changes to this register after initializing the host. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 814: Table 33-28 Host Configuration Register: Hcfg

    GAHBCFG.DMAEn=1, HCFG.DescDMA=1 => Scatter/Gather DMA mode In non Scatter/Gather DMA mode, this bit is reserved. 22:16 Reserved 8'd2 15:8 Resume Validation Period (ResValid) 8'd2 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 815 If FSLSPclkSel = 2'b00: Internal and external clocks have the same frequency If FSLSPclkSel = 2'b10: Internal clock is divided by eight version of external 48 MHz clock (utmifs_clk). JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 816: Table 33-29 Host Frame Interval Register: Hfir

    16'h0 Indicates the amount of time remaining in the current microframe (HS) or frame (FS/LS), in terms of PHY clocks. This field decrements on JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 817: Table 33-31 Host Periodic Transmit Fifo/Queue Status Register: Hptxsts

    Indicates the number of free locations available to be written to in the Periodic TxFIFO. Values are in terms of 32-bit words  16'h0: Periodic TxFIFO is full JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 818: Table 33-32 Host All Channels Interrupt Register: Haint

    A single register holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode for each port. It is shown in Figure 33-2. The R_SS_WC bits in this JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 819: Table 33-34 Host Port Control And Status Register: Hprt

    The application must time the reset period and clear this bit after the reset sequence is complete.  1'b0: Port not in reset JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 820 GLPMCFG.HIRD_Thres[3:0] field. If the core detects a USB remote wakeup sequence, as indicated by the Port L1 Resume/Remote L1 Wakeup Detected Interrupt JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 821 Power on the core. Load the DWC_otg driver. Connect an HS device and enumerate to HS mode. Access the HPRT register to send test packets. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 822: Table 33-35 Host Channel-N Characteristics Register: Hccharn

    Multi Count (MC) / Error Count (EC) 2'b0 When the Split Enable bit of the Host Channel-n Split Control register (HCSPLTn.SpltEna) is reset (1'b0), this field indicates to JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 823 Indicates the endpoint number on the device serving as the data source or sink. 10:0 Maximum Packet Size (MPS) 11'h0 Indicates the maximum packet size of the associated endpoint. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 824: Table 33-36 Host Channel-N Split Control Register: Hcspltn

    Host Channel-n Interrupt register. The application must clear the appropriate bit in this register to clear the corresponding bits in the HAINT and GINTSTS registers. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 825: Table 33-37 Host Channel-N Interrupt Register: Hcintn

    In Scatter/Gather DMA mode, the interrupt due to this bit is masked in the core. ACK Response Received/Transmitted Interrupt (ACK) 1'b0 R_SS_WC In Scatter/Gather DMA mode, the interrupt due to this bit is JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 826: Table 33-38 Host Channel-N Interrupt Mask Register: Hcintmskn

    This register reflects the mask for each channel status described in the previous section.  Mask interrupt: 1'b0  Unmask interrupt: 1'b1 Table 33-38 Host Channel-n Interrupt Mask Register: HCINTMSKn Field Description Reset Acces 31:11 Reserved 1'b0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 827: Table 33-39 Host Channel-N Transfer Size Register: Hctsizn

    Field Description Reset Acces 30:29 PID (Pid) 2'b00 The application programs this field with the type of PID to use for the initial transaction. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 828 A value of 8'b10101010 indicates that the corresponding interrupt channel is scheduled to issue a token every alternate microframe starting with second microframe. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 829: Table 33-40 Host Channel-N Dma Address Register: Hcdman

    IN/OUT transactions. The starting DMA address must be DWORD-aligned. Table 33-40 Host Channel-n DMA Address Register: HCDMAn Field Description Reset Acces Buffer DMA Mode 31:0 DMA Address (DMAAddr) "X" if not JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 830 CTD=5, then the core will start processing the 6 th descriptor. The address is obtained by adding a value of (8bytes*5=) 40(decimal) to DMAAddr. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 831: Device Mode Registers

    IN or OUT. To represent a bidirectional endpoint, two logical endpoints are required, one for the IN direction and the other for the OUT direction. This is also true for control endpoints. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 832: Table 33-43 Device Configuration Register: Dcfg

    NOTE: This bit must be modified only once after a reset. The following combinations are available for programming:  GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode  GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 833 If USB 1.1 Full-Speed Serial Transceiver Interface has not been selected, this bit must be zero. Non-Zero-Length Status OUT Handshake (NZStsOUTHShk) 1'b0 The application can use this field to select the handshake the JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 834: Table 33-44 Evice Control Register: Dctl

    1'b1: After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the descriptor that received the BNA interrupt. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 835 When this bit is set, there must be only one packet per descriptor. 14:13 Global Multi Count (GMC) 2'h0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 836 Global IN NAK Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared. Test Control (TstCtl) 3'h0  3'b000: Test mode disabled  3'b001: Test_J mode  3'b010: Test_K mode JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 837 LPM is enabled and the core is in the L1 (Sleep) state, when the application sets this bit, the core initiates L1 remote signaling to wake up the USB host. The application must JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 838: Table 33-45 Minimum Duration For Soft Disconnect

    The read value of this interrupt is valid only after a valid connection between host and device is established. Reserved Erratic Error (ErrticErr) 1'b0 The core sets this bit to report any erratic errors JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 839: Table 33-47 Device In Endpoint Common Interrupt Mask Register: Diepmsk

    Table 33-47 Device IN Endpoint Common Interrupt Mask Register: DIEPMSK Field Description Reset Acces 31:14 Reserved NAK interrupt Mask (NAKMsk) 1'h0 12:10 Reserved BNA Interrupt Mask (BNAInIntrMsk) 1'b0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 840: Table 33-48 Device Out Endpoint Common Interrupt Mask Register: Doepmsk

    Applies to control OUT endpoints only. Reserved OUT Token Received when Endpoint Disabled Mask 1'b0 (OUTTknEPdisMsk) Applies to control OUT endpoints only. SETUP Phase Done Mask (SetUPMsk) 1'b0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 841: Table 33-49 Device All Endpoints Interrupt Register: Daint

    31:16 OUT EP Interrupt Mask Bits (OutEpMsk) 16'h0 One per OUT Endpoint: Bit 16 for OUT EP 0, bit 31 for OUT EP 15 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 842: Table 33-51 Device In Token Sequence Learning Queue Read Register 1: Dtknqr1

    Table 33-52 Device IN Token Sequence Learning Queue Register 2: DTKNQR2 Field Description Reset Acces 31:0 Endpoint Token (EPTkn) 32'h0 Four bits per token represent the endpoint number of the token: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 843: Table 33-53 Device In Token Sequence Learning Queue Register 3: Dtknqr3

    Bits [3:0]: Endpoint number of Token 22 33.5.5.12 Device VBUS Discharge Time Register (DVBUSDIS)  Offset: 0828h This register specifies the VBUS discharge time after VBUS pulsing during SRP. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 844: Table 33-55 Device Vbus Discharge Time Register: Dvbusdis

    IN endpoint for which there is a token received on the USB. This is done to avoid getting into underrun conditions. By default the parking is enabled. Reserved 25:17 Receive Threshold Length (RxThrLen) 9'h8 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 845 When this bit is set, the core enables thresholding for isochronous IN endpoints. Non-ISO IN Endpoints Threshold Enable. (NonISOThrEn) 1'b0 When this bit is set, the core enables thresholding for Non Isochronous IN endpoints. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 846: Table 33-58 Device In Endpoint Fifo Empty Interrupt Mask Register: Diepempmsk

    IN Endpoint Interrupt Bits (EchInEpInt) 16'h0 One bit per IN Endpoint:  Bit 0 for IN endpoint 0  Bit 15 for IN endpoint 15 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 847: Table 33-60 Device Each Endpoint Interrupt Register Mask: Deachintmsk

    Status bits are masked by default.  Mask interrupt: 1'b0  Unmask interrupt: 1'b1 Table 33-61 Device Each In Endpoint-n Interrupt Register: DIEPEACHMSKn Field Description Reset Acces 31:14 Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 848: Table 33-62 Device Each Out Endpoint-N Interrupt Register: Doepeachmskn

    BNA interrupt Mask (BnaOutIntrMsk) 1'b0 OUT Packet Error Mask (OutPktErrMsk) 1'b0 Reserved Back-to-Back SETUP Packets Received Mask 1'b0 (Back2BackSETup) Applies to control OUT endpoints only. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 849: Table 33-63 Device Control In Endpoint 0 Control Register: Diepctl0

    The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint. Clear NAK (CNAK) 1'b0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 850 Maximum Packet Size (MPS) 2'h0 Applies to IN and OUT endpoints. The application must program this field with the maximum packet size for the current logical endpoint. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 851: Table 33-64 Device Out Endpoint 0 Control Register: Doepctl0

    This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 852: Table 33-65 Device Endpoint-N Control Register: Diepctln/Doepctln

     For OUT endpoint it indicates that the descriptor structure and data buffer to  receive data is setup. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 853 In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 854 The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Non-periodic IN JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 855 DATA0 or DATA1 PID.  1'b0: DATA0  1'b1: DATA1 This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 856 Before the application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to get the exact endpoint number for the Device Endpoint-n JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 857: Table 33-66 Device Endpoint-N Interrupt Register: Diepintn/Doepintn

    CRC error for an OUT packet. Dependency: This interrupt is valid only when both of the following conditions are true:  Parameter OTG_EN_DED_TX_FIFO=1 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 858 Indicates that an IN token was received when the associated TxFIFO (periodic/non- periodic) was empty. This interrupt is asserted on the endpoint for which the IN token was received. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 859 AHB as well as on the USB, for this endpoint. 33.5.5.24 Device Endpoint 0 Transfer Size Register (DIEPTSIZ0/DOEPTSIZ0)  Offset for IN endpoints: 910h JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 860: Table 33-67 Device In Endpoint 0 Transfer Size Register: Dieptsiz0

    2'b11: 3 packets 28:20 Reserved Packet Count (PktCnt) This field is decremented to zero after a packet is 1'b0 written into the RxFIFO. 18:7 Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 861: Table 33-69 Device Endpoint-N Transfer Size Register: Dieptsizn/Doeptsizn

    This is the data PID received in the last packet for this endpoint.  2'b00: DATA0  2'b01: DATA2  2'b10: DATA1  2'b11: MDATA JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 862: Table 33-70 Device Endpoint-N Dma Address Register: Diepdman/Doepdman

    These registers are implemented in RAM instead of flop-based implementation. Table 33-70 Device Endpoint-n DMA Address Register: DIEPDMAn/DOEPDMAn Field Description Reset Acces 31:0 DMA Address (DMAAddr) "X" if not JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 863: Table 33-71 Device Endpoint-N Dma Buffer Address Register: Diepdmabn/Doepdmabn

    Description Reset Acces 31:16 Reserved. 15:0 IN Endpoint TxFIFO Space Avail (INEPTxFSpcAvail) Configurable Indicates the amount of free space available in the Endpoint TxFIFO. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 864 16'h1: 1 word available  16'h2: 2 words available 16'hn: n words available (where 0  32,768)   16'h8000: 32,768 words available  Others: Reserved JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 865: Smart Card Controller

    Auto-character repeat in T=0 transmit mode Transforms inverted format to regular format and vice versa  Support stop clock function in some power consuming sensitive applications  JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 866: Pin Description

    32.11.2 FIFO Data Count Register (SCCFDR) SCCFDR 0x10041004 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 867: Control Register (Scccr)

    Rx FIFO counter meets the trigger value interrupt enable bit. TENDIE Transmission finished interrupt enable bit. (Both FIFO and transmitter are empty) RTOIE Reception timeout interrupt enable bit. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 868: Status Register (Sccsr)

    Writing has no effect, read as zero. RETR_3 Re-transmit exceed 3 times. Reserved Writing has no effect, read as zero. ECNTO ETU counter overflow. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 869: Transmission Factor Register (Scctfr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:20 Reserved Writing has no effect, read as zero. 19:0 ETU counter. Write operation will clear the internal counter automatically. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 870: Reception Timeout Register (Sccrtor)

    7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Bits Name Description Retry times when parity error detected. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 871: Kmc Controller

    KMC Transmit Data Register 0x???????? 0x10062060 KRDR KMC Receive Data Register 0x???????? 0x10062060 KCCR KMC Command Register 0x???????? 0x10062064 KCSR KMC Status Register 0x00 0x10062064 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 872 The usable command to KMC is described in back text. KCCR 0x10062064 7 6 5 4 3 2 1 0 KCCR ? ? ? ? ? ? ? ? JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 873 Address Line A2. This bit indicates which register was last written to. If this bit is 0, the last write operation is writing KTDR, otherwise is KCCR. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 874 1. When this bit is set to 0, KMC passes the incoming scan codes without translation. Following JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 875 Returns 0Fah if Password is loaded. Returns 0F1h if Password is not loaded. Current , KMC doesn‘t support password function, 0F1h always returned. Disable mouse interface. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 876 Disable keyboard or mouse. read KCSR. check if OTF == 0 then 6 else read KRDR. check if mouse transmission, then 7 else 8. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 877 MOF == 1, then 9 else 10. read KRDR for getting mouse data, then 11. 10 read KRDR for getting keyboard data. 11 receive end JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 878 BOOT Section 7 BOOT JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 879: Table 34-1 Boot Configuration Of Jz4780

    XBurst Boot ROM Specification 34 XBurst Boot ROM Specification The JZ4780 contains an internal 16KB boot ROM. The CPU boots from the boot ROM after reset. 34.1 Boot Select The boot sequence of the JZ4780 is controlled by boot_sel [2:0]. The configuration is shown as follow:...

  • Page 880: Figure 34-1 Boot Sequence Diagram Of Jz4780

    XBurst Boot ROM Specification MSC1_CMD are initialized, the boot program loads the 14KB code from MMC/SD card to tcsm and jump to it. NOTE: The JZ4780‘s tcsm is 16KB, its address is from 0xf4000000 to 0xf4004000. Reset N = 0...

  • Page 881: Table 34-2 The Definition Of 5 Flags In Nand Flash

    14KB codes in NAND will be loaded up to tcsm and branch to it at 192 bytes offset. Hardware PN and 64-bit BCH ECC will be used for every 256 bytes during reading. The ECC(112 bytes per 256 bytes JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 882: Figure 34-2 The Distribution And Structure Of The Boot Code In Nand

    The distribution and structure of the boot code in NAND is shown as Figure 36-2. The procedure of the JZ4780 NAND boot is shown as Figure 34-3. NOTE: PN is short for pseudorandom noise which is used for supporting TLC ( three-level cell ) NAND.
  • Page 883 256 Bytes Row cycle flag Row cycle flag = 0x55 ? = 0xaa ? The row The row cycle is 2 cycle is 3 JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 884: Figure 34-3 Jz4780 Nand Boot Procedure

    When boot_sel[2:0] is selected as USB boot, the internal boot ROM downloads user program from the USB port to internal SRAM and branches to the internal SRAM to execute the program. JZ4780 supports the external main crystal whose frequency is 12MHz. The boot program supports both high-speed (480MHz) and full-speed (12MHz) transfer modes. The boot program uses the following two transfer types.

  • Page 885: Table 34-3 Transfer Types Used By The Boot Program

    The six vendor requests are VR_GET_CPU_INFO (0x00), VR_SET_DATA_ADDRESS (0x01), JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 886 VR_PROGRAM_START2 (0x05). User program is transferred through Bulk IN or Bulk OUT endpoint. When JZ4780 is reset with boot_sel[2:0] equals 110b, 001b or 010b, the internal boot ROM will switch to USB boot mode and wait for USB requests from host. After connecting the USB device port to host, host will recognize the connection of a USB device, and start device enumeration.

  • Page 887: Table 34-4 Vendor Request 0 Setup Command Data Structure

    D6-D5 2: Vendor. D4-D0 0: Device. bRequest VR_GET_CPU_INFO: get CPU information. wValue 0000H Not in used. wIndex 0000H Not in used. wLength 0008H 8 bytes. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 888: Table 34-5 Vendor Request 1 Setup Command Data Structure

    Table 34-8 Vendor Request 4 Setup Command Data Structure Offset Field Size Value Description bmRequestType D7 0: Host to Device. D6-D5 2: Vendor. D4-D0 0: Device. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 889: Table 34-9 Vendor Request 5 Setup Command Data Structure

    When initializing the card, the clock of EXTCLK/128 is used. And when reading data, the clock of EXTCLK/4 is used. The procedure of the JZ4780 MMC/SD boot is shown as follow: JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 890 At last it loads 14KB code from the card to tcsm and branches to execute the code in tcsm. and the clock of EXTCLK/4 is used. The procedure of the JZ4780 eMMC boot is shown as follow: JZ4780 Mobile Application Processor Programming Manual...
  • Page 891 General-Purpose I/O Port-A 18, 20, 21, 23 pin. In spi nor flash address 0x0~0xF, this space will store 16 bytes that agreed SPI_boot flag. SPI_boot flag shown ―SPI nor flash boot flag informations‖ table. JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 892: Table 34-10 Spi Nor Flash Boot Flag Informations

    Note: Any irregularity in the above steps, SPI_boot will disable SSI controller and jump to MSC1 boot. The SPI_boot flag information table and procedure of the JZ4780 SPI boot is shown as follow: Table 34-10 SPI nor flash boot flag informations...
  • Page 893 14K bytes) Check SPL program vaild Disable ssi Branches to execute the code Jumb to MSC1 boot in tcsm Figure 34-7 JZ4780 SPI Boot Procedure JZ4780 Mobile Application Processor Programming Manual Copyright © 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

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