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Ingenic X1000 Programming Manual

Iot application processor
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X1000
IoT Application Processor
Programming Manual
Release Date: Jan. 13, 2016

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Summary of Contents for Ingenic X1000

  • Page 1 X1000 IoT Application Processor Programming Manual Release Date: Jan. 13, 2016...
  • Page 2 Ingenic Terms and Conditions of Sale. Ingenic products are not designed for and should not be used in any medical or life sustaining or supporting equipment. All information in this document should be treated as preliminary. Ingenic may make changes to this document without notice.

  • Page 3: Table Of Contents

    VDMA status (STAT) ...................... 20 3.2.3 Global control information ..................... 20 3.2.4 JPGC trigger ........................21 3.2.5 JPGC Status ........................22 3.2.6 Bitstream buffer address ....................22 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 4 Frame ID Registers (LCDFIDx) ..................42 4.4.15 DMA Command Registers (LCDCMDx) ................ 42 4.4.16 DMA OFFSIZE Registers (LCDOFFSx) ................ 43 4.4.17 DMA Page Width Registers (LCDPWx) ................. 43 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 5 CIM Control Register 2 (CIMCR2) ................67 5.2.4 CIM Status Register (CIMST) ..................68 5.2.5 CIM Interrupt Mask Register (CIMIMR) ................. 69 5.2.6 CIM Interrupt ID Register (CIMIID) ................70 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 6 I2S and MSB-justified serial audio format ..............99 6.3.2 Audio sample data placement in SDATA_IN/SDATA_OUT ......... 101 6.3.3 SPDIF Protocol ......................102 I2S Operation ........................103 6.4.1 Initialization ........................103 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 7 Application schematic ....................134 Mapped Register Descriptions .................... 134 8.3.1 CODEC internal register access control (RGADW) ............ 135 8.3.2 CODEC internal register data output (RGDATA) ............136 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 8 Requirements on outputs and inputs selection and power-down modes ......192 8.20.1 Initialization and configuration ..................192 8.21 Circuits design suggestions ....................193 8.21.1 Avoid quiet ground common currents ................193 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 9 9.2.20 CLKSTP_CFG ......................232 9.2.21 DDRC_STATUS ......................233 9.2.22 PHYRET_CFG ......................233 9.2.23 PHYRST_CFG ......................234 9.2.24 CPM_DRCG ........................ 234 Functional Description ......................235 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 10 CGU Block Diagram ....................266 11.1.2 CGU Registers ......................267 11.1.3 PLL Operation ......................292 11.1.4 Main Clock Division Change Sequence ..............294 viii X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 11 Read Counter in TCU2 Mode ..................325 12.4.6 Pulse Width Modulator (PWM) ..................326 12.4.7 Trackball Input Waveform Detect ................326 13 Operating System Timer ............... 328 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 12 Register Description ......................344 15.2.1 Watchdog Control Register (TCSR) ................345 15.2.2 Watchdog Enable Register (TCER) ................346 15.2.3 Watchdog Timer Data Register (TDR) ................. 346 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 13 How to Boot MCU Up ....................365 16.8 DMA manipulation ....................... 366 16.8.1 Descriptor Transfer Mode .................... 366 16.8.2 No-Descriptor Transfer Mode ..................369 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 14 18.3.2 Program Security Key Flow ..................393 18.3.3 Read EFUSE Flow ....................... 393 18.3.4 Read Security Key/Random Number Flow ..............393 Section 7 Peripherals X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 15 Register Description ......................481 21.3.1 Transmit/Receive FIFO Data Register (SCCDR) ............482 21.3.2 FIFO Data Count Register (SCCFDR) ................ 482 21.3.3 Control Register (SCCCR) ..................482 xiii X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 16 Transmission, reception and line status Independently ..........508 23.4.5 Slow infrared asynchronous interface ................. 508 23.5 Pins Description........................508 23.6 Data Format Description ..................... 509 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 17 Voltage Validation and Card Registry ................569 24.8.6 Single Data Block Write ....................571 24.8.7 Single Block Read ....................... 572 24.8.8 Multiple Block Write ..................... 572 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 18 27 XBurst Boot ROM Specification ............. 688 27.1 Boot Select .......................... 688 27.2 Boot Procedure........................688 27.3 SPL Structure ........................690 27.4 SPL Paramaters ........................690 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 19 27.5 USB Boot Specification ....................... 694 27.6 MSC0 Boot Specification ....................698 27.7 MSC1 boot Specification ..................... 700 27.8 SFC boot Specification......................700 xvii X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 21: Tables

    Table 15-2 WDT Registers Configuration ................... 345 Table 16-1 Registers Memory Map-Address Base ..............349 Table 16-2 DMA Channel Registers (n=0~31)................349 Table 16-3 Registers Memory Map-Address Base ..............350 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 22 Table 25-3 Core Global CSR Map (000h-3FFh) ................. 582 Table 25-4 Host Mode CSR Map (400h-7FFh) ................583 Table 25-5 Device Mode CSR Map (800h-BFFh) ............... 583 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 23 Table 25-42 Host Channel-n DMA Buffer Address Register: HCDMABn ........647 Table 25-43 Host Frame List Base Address Register: HFLBAddr..........647 Table 25-44 Device Configuration Register: DCFG ..............648 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 24 Table 27-10 SPI NOR flash boot flag informations(in spl signature) .......... 702 Table 27-11 SPI NAND flash boot flag informations(in spl signature) ........702 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 25 Figure 8-9 Digital microphone modulation noise reference spectrum (with FFT resolution = 20 Hz and 7 terms Blackman-Harris windowing) ................186 Figure 8-10 PSNT2 for VDDIO_CODEC when using PWM output..........187 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 26 Figure 22-8 TI‘s SSP Back-to-back Transfer Format ..............493 Figure 22-9 National Microwire Format 1 Single Transfer ............494 Figure 22-10 National Microwire Format 1 Back-to-back Transfer ..........494 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 27 Figure 27-7 Typical Procedure of MSC0 Boot ................699 Figure 27-8 SPL Structure of MSC0/MSC1 Boot ............... 700 Figure 27-9 X1000 SPI Boot Procedure ..................701 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 29: Section 1 Overview

    OVERVIEW Section 1 OVERVIEW X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 30: Overview

    Overview 1 Overview X1000 is a low power consumption, high performance and high integrated application processor, the application is focus on IoT devices. And it can match the requirements of many other embedded products. 1.1 Block Diagram Figure 1-1 X1000 Diagram 1.2 Features...

  • Page 31: Image Core

    – Configurable VSYNC and HSYNC signals: active high/low – Configurable PCLK: active edge rising/falling – PCLK max. 30MHz – Configurable output order AIC controller  – I2S features X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 32 – 1 MIC in path or 1 line in path Maximum (Total 1 analog input) Low power DMIC Controller  – 16 bits data interface and 20bit precision internal controller. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 33: Memory Interface

    SPI, Dual-I/O SPI, Quad-I/O SPI, Full Dual-I/O SPI, Full Quad-I/O SPI – two data transfer mode: slave mode and DMA mode – Configurable 6 phases for software flow X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 34: System Functions

    – Support up to 8 independent DMA channels – Descriptor or No-Descriptor Transfer mode ® – A simple Xburst -1 CPU supports smart transfer mode controlled by programmable X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 35: Peripherals

    – Interrupt operation – The number of devices that you can connect to the same SMB-bus is limited only by the maximum bus capacitance of 400pF X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 36 – Consumer Electronics Advanced Transport Architecture (CE-ATA – version 1.1) – Maximum data rate is 50MBps – Both support MMC data width 1bit ,4bit, only MSC0 support 8bit X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 37: Bootrom

    – Station Management Agent (SMA) – remote wake-up frame and magic packet frame processing OTP Slave Interface  – Total 1Kb. 1.2.7 Bootrom 16KB Boot ROM memory X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 38: Section 2 Core Functions

    Core Functions Section 2 CORE FUNCTIONS X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 39: Cpu

    FPU, floating point unit implemented to improve floating point number processing ability  Unified level 2 cache that is transparent for programmer 2.1 Block Diagram X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 40: Figure 2-1 Structure Of Cpu Core

    Debug D-Cache I-Cache DTLB JTLB ITLB Write Buffer JTAG L2C Bridge Unified L2 Cache Address Bus Data Bus Figure 2-1 Structure of CPU core X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 41: Extra Features Of The Cpu Core

    0 cycle penalty when BTB predicts taken Anyone and branch is taken, otherwise: 5/4/2/1 (delay slot) BTB miss, branch is taken, 3 cycles penalty. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 42 3 extra interlock cycles, LWL/LWR 4/3/2/1 Anyone LB/LBHU similarly, 2 extra for the third RAW one LH/HU and 1 extra for the forth RAW one, X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 43 No data dependency or hazards exist. Others Anyone NOTE: JMP denotes J and JR instructions; BC denotes branch conditionally instructions; BCL denotes branch conditionally and likely instructions. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 44: Pmon

    2.4 PMON PMON is a simple performance monitor. In X1000, PMON can make real-time monitoring for following hardware events.  I-cache miss times, D-cache miss times  Total issued instructions, Discarded instructions  Pipeline freeze cycles, CPU clock cycles ...

  • Page 45: Fundamental

    However, OS must make serious control for config7.bit6 and those dedicated resources to forbid this partial-kernel-mode permission for those malicious applications. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 46: Section 3 Image Core

    IMAGE CORE Section 3 IMAGE CORE X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 47: Jpeg

    JPEG 3 JPEG 3.1 Overview JPEG module is a jpeg encoding unit in chip X1000. Features:  Baseline ISO/IEC 10918-1 JPEG compliant  8-bit pixel depth support Support for YUY2 ([Y0U0Y1V0]) color  Up to four programmable Quantization tables ...

  • Page 48: Vdma Status (Stat)

    Component 1 plane vertical size of a MCU 21:20 Component 1 plane horizontal size of a MCU 19:18 Component 0 plane vertical size of a MCU X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 49: Jpgc Trigger

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 50: Jpgc Status

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 51: Component 0 Plane Buffer Address

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 52: Component 2 Plane Buffer Address

    Fixed as 0x132 19:3 Component 3 plane buffer address. Note: 1. its only used in UNIV mode reserved Writing has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 53: Mcu Number

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Bits Name Description 31:8 reserved Writing has no effect, read as zero. NBLK Number of block minus 1 in a MCU X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 54: Efe Control

    First MB position of X direction of current slice Note: Since only rectangle slice partition of a frame is supported, so FSTX should always be set as 0. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 55: Raw Plane Source Buffer Address

    RAWC_SA then binding and delivering to the buffer indicated by RAW_DBA. It should be 512 byte aligned Reserved Writing has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 56: Raw Plane Stride

    0x1400 ~ 0x17FC. More detailed information is defined as the following illustration. Mapping offset Description 0x1400 ~ 0x14FC Quantization table 0 0x1500 ~ 0x15FC Quantization table 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 57: Huffman Symbol Table

    AC Huffman Table 0 0x1AC0 ~ 0x1D7C AC Huffman Table 1 0x1D80 ~ 0x1DBC DC Huffman Table 0 0x1DC0 ~ 0x1DFC DC Huffman Table 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 58: Section 4 Display/Camera/Audio

    DISPLAY/CAMERA/AUDIO Section 4 DISPLAY/CAMERA/AUDIO X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 59: Slcd Controller

    SLCD_TE Input Smart LCD tearing effect signal SLCD_DAT [15:0] Output The data of SLCD. Serial: SLCD_DAT [15] Parallel: 16bit SLCD_DAT [15:0] 8bit SLCD_DAT [7:0] X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 60: Block Diagram

    RSW - read and write, but set to 1 by read RWC - read and write, clear to 0 by write 1, write 0 has no effect X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 61: Table 4-2 Registers Memory Map-Address Base

    Display Area 0x0010 Horizontal Start/End Point LCDDAV Display Area Vertical 0x0014 Start/End Point Foreground 0 XY 0x0120 LCDXYP0 Position Register LCDXYP1 Foreground 1 XY 0x0124 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 62 DMA1 Page Width 0x0074 LCDPW1 Registers LCDCNUM1/LCDPOS1 DMA1 Commend 0x0078 Counter Registers Foreground1 x Size in 0x007C LCDDESSIZE1 Descriptor Priority level 0x02C0 LCDPCFG threshold configure X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 63: Configure Register (Lcdcfg)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 64: Status Register (Lcdstate)

    RST 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 65: Osd Control Register (Lcdosdctrl)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 66: Display Area Horizontal Start/End Point (Lcddah)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 67: Foreground 0 Size Register (Lcdsize0)

    = REVE + 1; 4.4.11 Interrupt ID Register (LCDIID) LCDIID is a read-only register that contains a copy of the Frame ID register (LCDFID) from the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 68: Descriptor Address Registers (Lcddax)

    NOTE: If only one frame buffer is used in external memory, the LCDDAx field (word [0] of the frame descriptor) must point back to itself. That is to say, the value of LCDDAx is the physical address of itself. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 69: Source Address Registers (Lcdsa)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:0 Buffer start address. (Only for driver debug) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 70: Frame Id Registers (Lcdfidx)

    It is used to distinguish command and data in lcm mode. And it is only loaded via DMA channel 0. 1: The data is command 0: The data is data X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 71: Dma Offsize Registers (Lcdoffsx)

    30lines, the picture will be divided to 3 blocks of 30lines. Then OFFSIZE indcates the size between 2 pagewidth. But usually we will set PAGEWIDTH as large as 1line, and divide the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 72: Dma Commend Counter Registers (Lcdcnumx)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 73: Foreground X Size In Descriptor (Lcddessizex)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 74: Lcd Arbiter Priority(Lcd_Pcfg_Arb)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 75: Slcd Configure Register (Mcfg)

    Do not change this bit Reserved Writing has no effect, read as zero. CLKPLY Do not change this bit TTYPE Do not change this bit X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 76: Slcd Configure New Register (Mcfg_New)

    8-bit color depth information(RGB332) , one pixel per cycle. 2‘b01 : 2-times transfer is used to transmit 1 pixel data, such as sending 16-bit color depth information(RGB565) , one and half X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 77 24bpp data in output fifo to relative bpps as follows 24bpp data in output fifo: 8bpp output data(R3G3B20: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 78 18 bits or the total 24bits of slcd data is useful, and the cmd will be data[17:0] or data[23:0]. Note5： DTIMES_NEW and CTIMES_NEW is only useful for descrptor mode, when in regster mode, X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 79: Slcd Control Register (Mctrl)

    DMAMODE high or low depending on wether you want to use dma single mode or dma continue mode. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 80: Slcd Status Register (Mstate)

    Bits Name Description 31:30 The PTR bit of data register is used to decide the meanings of the low 24-bit. 2‘b00: data 2‘b01: command X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 81: Slcd Wait Time Register (Wtime)

    SLOW_TIME: if use the function of slcd to wait for TE‘s relative edge, slcd will wait for SLOW_TIME‘s period of pixclk before it begin to flush out data X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 82: Slcd Controller Operation

    The SLCD Controller must not be re-enabled until the QD bit is set, indicating that the quick shutdown is complete. Do not set the DIS bit when a quick disabling command has been issued. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 83: Resetting The Controller

    It is suggested that the extra bits to be set zero. 4.6 System Memory Format 4.6.1 Data format 16bpp 18bpp X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 84 30bpp 16bpp with alpha 18bpp with alpha 24bpp with alpha 24bpp compressed BLUE 1 [7:0] RED 0 [7:0] GREEN 0 [7:0] BLUE 0 [7:0] X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 85: Command Format

    RED2 [7:0] 4.6.2 Command Format 18-bit command 16-bit command 9-bit command once 8-bit command once 8-bit command twice (Command = command part + data part) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 86: Transfer Mode

    Because DMA transfer mode only can work in OSD mode, you need to configure the panel according OSD mode: Set Color. * LCDBGC0,1, LCDKEY0, LCDKEY1, LCDALHPA Set Display. * LCDVAT, LCDDAH, LCDDAV * LCDVSYNC, LCDHSYNC Set Descriptors. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 87: Register Transfer Mode

    DC [31] = 0 XXX [30:9] Data [8:0] DC [31] = 0 XXX [30:8] Data [7:0] 4.8 Timing 4.8.1 Parallel Timing LCD_PCLK DATA Command Data X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 88: Serial Timing

    *please notice that use and only use DMA0 to transfer command no matter use DMA0 to transfer frame data or not. One recommend descriptor chain (CMD0 with CNUM>0 and CMD1 with CNUM=0): CMD0 CMD1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 89: Register Operation

    5. setup SLCD for descrptor mode, here to make sure the 1 descriptor is cmd and CMDNUM>0, then the descriptor should switch between data and cmd X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 90: Camera Interface Module

    Table 5-2 CIM Registers Name Reset Value Offset Access Size CIMCFG 0x00000000 0x0000 CIMCR 0x00000000 0x0004 CIMST 0x00150002 0x0008 CIMIID 0x00000000 0x000C CIMDA 0x00000000 0x0020 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 91: Cim Configuration Register (Cimcfg)

    OByte3 stands for the 4th byte stored in memory Then BS0 = 0: IByte0 is stored in OByte0 BS0 = 1: IByte1 is stored in OByte0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 92 3 input data bytes to form 32-bit data. 0: DUMMY zero function disabled 1: DUMMY zero function enabled E_VSYN External / internal VSYNC selection. When DSM is ITU656Progressive X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 93 1: External HSYNC mode, HSYNC is provided by image sensor via pin HSYNC Data sample mode. Please refer to the table below. Description 2‘b00 ITU656Progressive Mode 2‘b01 ITU656Interlace Mode 2‘b10 Gated Clock Mode 2‘b11 Reserved X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 94: Cim Control Register (Cimcr)

    0: Not request to stop 1: Request to stop SW_RST Software reset enable. 0: Don‘t care 1: Reset the CIM module. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 95: Cim Control Register 2 (Cimcr2)

    16 < n <= 32 32 < n 2‘b01 n <= 16 16 < n <= 32 32 < n <= 64 64 < n X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 96: Cim Status Register (Cimst)

    When set to 1, indicates the DMA complete transferring data and stop the operation. Can generate an interrupt if CIMIMR.DSTPM is 0. Write 0 to clear. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 97: Cim Interrupt Mask Register (Cimimr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 1 Bits Name Description 31:12 Reserved Read as zeros. DEEOFM The control bit to mask DMA EEOF interrupt. 0: enable X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 98: Cim Interrupt Id Register (Cimiid)

    CIM state register. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 99: Cim Descriptor Address (Cimda)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 100: Cim Dma Command Register (Cimcmd)

    DMA to a frame buffer. LEN = 0 is not valid. DMA transfers data according to LEN. Each time one or more word(s) been transferred, LEN is decreased automatically. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 101: Cim Window Size (Cimwsize)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 102: Cim Data Sample Modes

    PCLK when HSYNC is active; That means, HSYNC functions like ―data enable‖ signal. Please refer to the figure below. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 103: Itu656 Interlace Mode

    Protection bits end of active start of active 313-335 1: blanking video video 336-623 0: video data Field 2 624-625 1: blanking X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 104: Itu656 Progressive Mode

    5.4 DMA Descriptors Used when output is packaged frame format. A DMA descriptor is a 4-word block corresponding to the four DMA registers – CIMDA, CIMFA, X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 105: Software Operation

    Step 1. Request CIM controller enter into idle state. Set CIMCR.STP_REQ to 1. Step 2. Wait CIM controller enter into idle state. Waiting for CIMST.STP_ACK to 1. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 106 When using hardware to deal with frame size error, the flows configuration should be used: CIMCMD.OFAR should be set to 1 when preparing the DMA descriptor(s). X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 107: Audio Interface Controller

    Supports IEC60958 two-channel PCM audio and IEC61937 multi-channel compressed audio (Dolby Digital, DTS, etc.). This chapter describes the programming model for the AIC. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 108: Block Diagram

    8, 16, 18, 20 and 24 bit audio sample data sizes supported  DMA transfer mode supported  Stop serial clock supported  Programmable Interrupt function supported X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 109: Interface Diagram

    Audio bit clock input SYNC Left/right words select input SYS_CLK Master/system clock input Figure 6-3 Interface to an External Slave Mode I2S/MSB-Justified CODEC Diagram (Share Clock Mode) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 110: Signal Descriptions

    MSB-justified format it inputs from the CODEC in slave mode and outputs to CODEC in master mode. In the master mode, the clock is generated internally that is 64 times the sampling frequency. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 111: Register Descriptions

    Register AICSR AIC FIFO Status Register 0x00000008 0x10020014 AIC I2S/MSB-justified Clock Divider 0x00000003 I2SDIV 0x10020030 Register AICDR AIC FIFO Data Port Register 0x???????? 0x10020034 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 112: Aic Configuration Register (Aicfr)

    Writing has no effect, read as zero. 20:16 TFTH Transmit FIFO threshold for interrupt or DMA request. The TFTH valid value 0 ~ 31. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 113 CODEC. SYNCD SYNC Direction. This bit specifies input/output direction of SYNC in I2S/MSB-justified format. Change this bit in case of BIT_CLK is stopped X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 114: Aic Common Control Register (Aiccr)

    LSB align. The packed mode is only support 16bit sample size. PACK16 Sample Size Unpacked data mode. One word only contains one 16bit sample X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 115 Enabled. TDMS Transmit DMA enable. This bit is used to enable or disable the DMA during transmit audio data. TDMS Transmit DMA Disabled. Enabled. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 116 Enable TUR Interrupt. This bit is used to control the TUR interrupt enable or disable. ETUR TUR Interrupt Disabled. Enabled. ERFS Enable RFS Interrupt. This bit is used to control the RFS interrupt enable X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 117: Aic I2S/Msb-Justified Control Register (I2Scr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:18 Reserved Writing has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 118: Aic Controller Fifo Status Register (Aicsr)

    6.2.4 AIC Controller FIFO Status Register (AICSR) AICSR contains bits to reflect FIFOs status. Most of the bits are read-only except two, which can be written a 0. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 119 FIFO threshold, which is controlled by AICFR.RFTH. When RFS is 1, it may trigger interrupt or DMA request depends on the interrupt enable and DMA setting. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 120: Aic I2S/Msb-Justified Status Register (I2Ssr)

    Description AIC Receiver part is idle or disabled. AIC Receiver part currently is transmitting or receiving a frame. AIC busy in I2S/MSB-justified format. Description X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 121: Aic I2S/Msb-Justified Clock Divider Register (I2Sdiv)

    RST 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 122: Spdif Enable Register (Spena)

    0: DMA transmitter disable 1: DMA transmitter enable D_TYPE If the bit number of data is less than16, the data in memory is as follows: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 123: Spdif State Register (Spstate)

    0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description Reserved Writing has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 124: Spdif Configure 1 Register (Spcfg1)

    Specify the trigger value of FIFO. TRIG Description Trigger Value is 4. Trigger Value is 8. Trigger Value is 16. Trigger Value is 32. 11:8 SRC_NUM Source number. 0000:Unspecified X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 125: Spdif Configure 2 Register (Spcfg2)

    Original sampling frequency. 1111:44.1kHz 1101:48kHz 1100:32kHz 0101:96kHz 0001:192kHz Others: Reference IEC60958-3 21:19 SAMPL_WL Sample word length. When MAX_WL=1: 001:20 bit 110:21 bit 010:22 bit 100:23 bit X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 126: Spdif Fifo Register (Spfifo)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 127: Serial Interface Protocol

    In the A: LR mode, first send the left channel in a stereo frame. One Left slot and one Right slot make a sample frame. It is the normal mode of I2S. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 128: Figure 6-6 I2S Data Format (B: Rl Mode)

    … 28 29 30 31 32 33 34 35 … 60 61 62 63 Cycle No. BIT_CLK SDATA_OUT B31 B30 Or SDATA_IN SYNC Right Left Figure 6-8 MSB-justified data format (D: RL mode) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 129: Audio Sample Data Placement In Sdata_In/Sdata_Out

    … Table 6-3 escribed the how sample data bits are transferred. Table 6-3 Sample data bit relate to SDATA_IN/SDATA_OUT bit I2S/MSB-Justified Format SDATA IN/OUT X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 130: Spdif Protocol

    Figure 6-9 Block format Sub-frame format in PCM mode is shown below: 27 28 Sync preamble Auxiliary Audio sample word Figure 6-10 Sub-frame format in PCM mode X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 131: I2S Operation

    AIC and optional, the external CODEC. Here is the initial flow. Select external CODEC (AICFR.ICDC). If I2S/MSB-Justified is selected, select between I2S and MSB-Justified (I2SCR.AMSL). X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 132: External Codec Registers Access Operation

    Configure sample rate by clock dividers (for I2S/MSB-Justified format with BIT_CLK is provided internally) or by CODEC registers (for BIT_CLK provided by external CODEC). Some other configurations: mono to stereo, endian switch, signed/unsigned data transfer, X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 133: Audio Record

    Take sample data from the receive FIFO until AICSR.RFL change to 0. So that all samples in the receive FIFO has been taken away, then we can have a clean start up next time. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 134: Fifos Operation

    In case of DMA bus initiator, one 24, 20, 18 bits audio sample must occupies one 32-bits word in memory, so 32-bits width DMA must be used. One 16 bits sample occupies one 16-bits half word in X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 135: Data Flow Control

    Through read these register fields, processor can detect when there are samples in receiving FIFO in audio record and then load them from the RX-FIFO, and when there are rooms in transmitting X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 136: Audio Samples Format

    0xXXXXX004 0xXXXXX000 0xXXXXX000 Figure 6-13 One channel (Left) and Two channels (right) mode (16 bits packed mode) Four channels mode and six channels mode: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 137: Figure 6-14 Four Channels (Left) And Six Channels (Right) Mode (16 Bits Packed Mode)

    …… bit0 0xXXXXX004 0xXXXXX000 0xXXXXX000 Figure 6-16 One channel (Left) and Two channels (right) mode Four channels mode and six channels mode: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 138: Serial Audio Clocks And Sampling Frequencies

    The BIT_CLK is the rate at which audio data bits enter or leave the AIC. BIT_CLK can be supplied either by the CODEC or an internally PLL. If it is supplied internally, BIT_CLK is configured as output X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 139: Table 6-4 Audio Sampling Rate, Bit_Clk And Sys_Clk Frequencies

    CPM divider controlled by I2SCDR. If BIT_CLK is chosen as an output, another divider in AIC is used to divide SYS_CLK for it. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 140: Table 6-5 Bit_Clk Divider Setting

    PLL frequency as close to the frequencies listed as possible, then use clock dividers to generate different SYS_CLK/BIT_CLK for different sample rate. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 141: Table 6-6 Approximate Common Multiple Of Sys_Clk For All Sample Rates

    For an EXCLK clock frequency, try to generate PLL frequencies as close to the frequencies listed in Table 6-6 as possible. Table 6-8 lists the PLL parameters and audio sample errors at different PLL frequencies for EXCLK at 12MHz. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 142: Interrupts

    The following status bits, if enabled, interrupt the processor:  Receive FIFO Service (AICSR.RFS). It‘s also DMA Request.  Transmit FIFO Service (AICSR.TFS). It‘s also DMA Request.  Transmit Under-Run (AICSR.TUR). X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 143: Spdif Guide

    Set SPCTRL.DMA_EN to choose DMA mode or CPU mode. Set SPCTRL.SIGN_N to choose whether to transfer the most significant bit by toggle or not. Set SPCTRL. SFT_RST to 1 reset FIFO. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 144: Disable Operation

    6.5.4 Disable operation Set SPENA.SPEN to 0 to disable SPDIF to transmitter. Wait SPSTATE.BUSY to be set to 0 by hardware. You can do other operation. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 145: Pcm Interface

    PCM Serial clock Line signal input/output PCMSYN Input / Output PCM sync signal input/output PCMDOUT Output PCM Serial data output PCMDIN Input PCM Serial data input X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 146: Block Diagram

    RS - read only, and set to 1 by read SPEC - special access method, relate to its description 3. Reset Value 1 - reset to 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 147: Registers Memory Map

    ERDMA Receive DMA Disabled. Enabled. ETDMA Transmit DMA Enable. This bit is used to enable or disable the DMA during transmit audio data. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 148 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 149 FIFO, indicated by PCMINTS.TFL, is less than the threshold value, PCMINTS.TFS is set. Smaller TFTH value provides lower DMA/interrupt request frequency but have more risk X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 150 TFS Interrupt Disabled. Enabled. ETUR Enable TUR Interrupt. This bit is used to control the TUR interrupt enable or disable. ETUR TUR Interrupt Disabled. Enabled. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 151 Transmit FIFO Under Run. This bit indicates that transmit FIFO has or has not experienced an under-run. Description When read, indicates under-run has not been found. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 152 PCMCLK clock divider value minus 1. Controls the divider used to create the PCMCLK based upon the CPM_PCM_SYSCLK. PCMCLK = CPM_PCM_SYSCLK / ( CLKDIV + 1 ). X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 153: Pcm Interface Timing

    Figure 7-2 Short Frame SYN Timing (Shown with 16bit Sample) NOTE: Figure 7-2 shows a PCM transfer with the MSB configured one shift clock after the PCMSYN. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 154: Long Frame Syn

    Short PCMSYN Or Long PCMSYN Don't Care PCMDOUT Don't Care PCMDIN Figure 7-5 Multi-Slot Frame SYN Timing (Shown with two Slots and 8bit Sample) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 155: Pcm Operation

    Initialize PCM and configure the register. Write 1 to PCMCTL.PCMEN and PCMCTL.CLKEN. Fill sample data to the transmit FIFO. Repeat this till finish all sample data. In this X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 156: Audio Record

    FIFO and read from receive FIFO. One time access to PCMDP.DATA process one sample. The sample data should be put in LSB X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 157: Data Flow Control

    Polling approach is in very low efficiency and is not recommended. 7.6.5.2 Interrupt and Processor Access Set proper values to PCMCFG.TFTH and PCMCFG.RFTH, the FIFO interrupts trig thresholds. Set X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 158: Pcm Serial Clocks And Sampling Frequencies

    Transmit FIFO Service (PCMINTS.TFS). It‘s also DMA Request.  Transmit Under-Run (PCMINTS.TUR).  Receive Over-Run (PCMINTS.ROR). For further details, see the corresponding register description sections. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 159: Internal Codec

    TBD = parameter or document section to be defined later on TBC = parameter or document section subject to change TO BE COMPLETED = section to be filled or subject to change X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 160: Signal Descriptions

    DMIC_IN is ‗GPIO : G3‘ , MIC_CLK is ‗GPIO : R5‘. Please refer to GPIO specification for these pins operating. nLR: Internal low noise linear regulator. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 161: Block Diagram

    Off if SB or SB_SLEEP or SB_ADC; Enable ADC Path to AIC Off if SB or SB_SLEEP or SB_DAC; Enable DAC Path to AIC Figure 8-2 Internal CODEC works with AIC X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 162: Application Schematic

    The internal CODEC software interface includes 2 registers. They are mapped to IO memory address space of AIC module so that program can access them to control the operations of the CODEC. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 163: Codec Internal Register Access Control (Rgadw)

    When it issues a writing command to CODEC‘s internal register, 14:8 RGADDR i.e.RGWR=1, this field specifies the corresponding CODEC register‘s address. In addition, this field also decides the address of the CODEC X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 164: Codec Internal Register Data Output (Rgdata)

    The internal embedded CODEC is controlled through its internal registers. These registers data can be accessed through memory-mapped registers, RGADW and RGDATA. AIC‘s BITCLK and X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 165: Access To Internal Registers Of The Embedded Codec

    CODEC input SYNC to AIC. I2SCR.AMSL = 1; Use I2S operation mode. I2SCR.ESCLK = 1; Open MCLK to internal CODEC. (if using PLL Clock) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 166: Power Saving

    CODEC input BIT_CLK to AIC. AICFR.SYNCD = 0; CODEC input SYNC to AIC. I2SCR.AMSL = 1; Use I2S operation mode. I2SCR.ESCLK = 1; Open MCLK to internal CODEC. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 167: Timing Parameters

    Tsbyu is the reference wake-up time after complete power down. Tshd_adc is the ADC wake-up time after sleep mode. Tshd_dac is DAC wake-up time after sleep mode. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 168: C Parameters

    The current in case of short circuit is the max value. This current is only sink or drawn until the short circuit detection system acts. Please refer to Chip Datasheet for more details. 8.7 CODEC internal Registers X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 169: Registers Memory Map

    0x0E CR_ADC ADC control register 0x0F CR_MIX Digital mixer control register 0x10 DR_MIX Digital mixer data register 0x1A MIX_0 Digital mixer control register 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 170 DAC2 soft clipping DRC control register 1 DAC2_AGC_2 DAC2 soft clipping DRC control register 2 DAC2_AGC_3 DAC2 soft clipping DRC control register 3 CR_ADC_AGC ADC automatic gain control register 0x2F X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 171: Register Description

    0: SRC is not locked. Data from the audio interface are automatically muted. 1: The SRC is locked and operating normally. Reserved Writing has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 172 Writing has no effect, read as zero. 8.7.2.5 SIGR3: Signature Register 3 Register Name: SIGR3 Register Address: 0x04 bit7-R-? bit6-R-? bit5-R-? bit4-R-? bit3-R-? bit2-R-? bit1-R-? bit0-R-? Reserved X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 173 DAC_MUTE Read 00 : DAC not muted 01 : DAC being muted 10 : DAC leaving mute mode 11 : DAC in mute mode X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 174 Audio Data Word Length for ADC path. Read / Write 00: 16-bit word length data 01: 18-bit word length data 10: 20-bit word length data X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 175 SB_MIC1 MICBIAS1_V Reserved Bits Field Description Reserved Writing has no effect, read as zero. MICIDFF1 Microphone 1 input mode selection Read/Write 0= single-ended input X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 176 1: puts the DAC in soft mute mode Reserved Writing has no effect, read as zero. Reserved Writing has no effect, read as one.. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 177 8.7.2.16 CR_ADC: Control Register for ADC Register Name: CR_ADC Register Address: 0x0F bit7-RW-1 bit6-RW-0 bit5-RW-0 bit4-RW-1 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 ADC_SOFT_ ADC_DMIC_ Reserved SB_ADC Reserved MUTE X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 178 Refer to DR_MIX for MIX_LOAD description MIX_ADD Digital mixer control registers address Read/Write MIX_ADD Corresponding control register 000000 MIX_0 000001 MIX_1 000010 MIX_2 000011 MIX_3 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 179 MIX_1: Digital mixer control register 1 Register Name: CR_MIX Indirect register Address: 0x01 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 MIXDACL_SEL MIXDACR_SEL Reserved X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 180 Reserved Writing has no effect, read as zero. Note: MIXADCX_SEL should be configured to 01 in normal mode. MIX_4: Digital mixer control register 4 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 181 Reserved MCLK_DIV Reserved SHUTDOWN_ CRYSTAL CLOCK Bits Field Description Reserved Writing has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 182 8.7.2.22 SFCCR_DAC: DAC Sample frequency fine control register Register Name: SFCCR_DAC Register Address: 0x15 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 DACFREQ_ DAC_FREQ_ADJ[14:8] VALID X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 183 Selection of the ADC sampling rate (Fs). Read/Write The sampling frequency value is given in the FREQ table. NOTE: Please refer to section Sample frequency: FREQ. 8.7.2.25 CR_TIMER_MSB: counter MSB X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 184 8-bit parallel control interface or 8 MCLK cycles duration when using SMB control interface Reserved Writing has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 185 8.7.2.29 IFR: Interrupt Flag Register Register Name: IFR Register Address: 0x1C bit7-RWC-? bit6-RWC-? bit5-RWC-? bit4-R-? bit3-R-? bit2-RWC-? bit1-RWC-? bit0-RWC-? ADAS_LOCK_ Reserved ADC_MUTE_ Reserved DAC_MUTE_ EVENT EVENT EVENT X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 186 Mask for the TIMER_END flag MASK Read/Write 0: interrupt enabled 1: interrupt masked (no IRQ generation) Reserved Writing has no effect, read as one.. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 187 8.7.2.33 GCR_DACR: right channel DAC Gain Control Register Register Name: GCR_DACR Register Address: 0x20 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 Reserved GODR X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 188 Reserved GIM1 Bits Field Description Reserved Writing has no effect, read as zero. GIM1 Microphone 1 boost stage gain programming value. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 189 Reserved Bits Field Description Reserved Writing has no effect, read as zero. ―Programmable input attenuation amplifier: GID‖. NOTE: Please refer to the section X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 190 8.7.2.42 GCR_MIXADCL: ADC Left Digital Mixer Control Register Register Name: GCR_MIXADCL Register Address: 0x29 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 LRGIMIX Reserved GIMIXL X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 191 DAC_AGC_ADD LOAD Bits Field Description DAC_AGC_EN Enable of the AGC system. Read/Write 0 : inactive 1 : enable the automatic level control DAC_AGC_LOAD Read/Write X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 192 00000: Full scale 00001: Full scale -1dB 00010: Full scale -2dB by step of - dB 11110: Full scale -30dB 11111: Full scale -31dB X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 193 8.7.2.45.4 DAC_AGC_3: DAC Soft clipping DRC control register 3 Register Name: DAC_AGC_3 Indirect register address: 0x03 bit7-RW-0 bit6-RW-0 bit5-RW-0 bit4-RW-0 bit3-RW-0 bit2-RW-0 bit1-RW-0 bit0-RW-0 Reserved RCOMP X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 194 1: Left and right channels DRC parameters are the same: LTHRES and LCOMP are used for both left and right channels Reserved Writing has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 195 00010: Full scale -2dB by step of - dB 11110: Full scale -30dB 11111: Full scale -31dB 8.7.2.47.4 DAC2_AGC_3: DAC Soft clipping DRC control register 3 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 196 Instructions for writing into a register The data must firstly be written into the DR_ADC_AGC register. The register address must then be written in CR_ADC_AGC X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 197 000: -72 dB 001: -66 dB …by step of 6dB 111: -30 dB HOLD Hold time before starting AGC adjustment to the TARGET value. Read/Write X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 198 Reserved AGC_MAX Bits Field Description Reserved Writing has no effect, read as zero. AGC_MAX Maximum Gain Value to apply to the ADC path. NOTES: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 199 11101 39.5 00110 01110 10110 11110 00111 10.5 01111 22.5 10111 30.5 11111 42.5 Please refer to section ―AGC system guide‖ for more details. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 200 Register Address:0x34 bit7-RW-? bit6-RW-? bit5-RW-? bit4-RW-? bit3-RW-? bit2-RW-? bit1-RW-? bit0-RW-? Reserved Bits Field Description Reserved Writing has no effect. 8.7.2.54 CR_TR: Test Mode Control Register X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 201 Reserved Bits Field Description Reserved Writing has no effect. 8.7.2.58 SR_TR_SRCDAC: DAC test Mode Status Register X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 202: Programmable Gains

    If the HPF is activated, data are valid after about 64 sample periods but the offset cancellation is not still completed at this time due to its internal time constant. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 203: Programmable Input Gain Amplifier: Gid

    The value of the gain GODL/R is programmable from +0 to –31dB with 1 dB pitch. The gain and output levels are obtained according to the following table: Decimal decoded value Gain Value (dB) … X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 204: Programmable Attenuation: Go

    Programmable digital mixer gain: GIMIX and GOMIX The following table shows the relation between the gain and GIMIX/GOMIX. GIMIX or GOMIX Gain value (dB) 00000 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 205: Gain Refresh Strategy

    LOAD Rhpdo value capacitor values value Driving Headphone 16 Ohm / 220uF 470 Ohm typ. Driving Lineout 10k Ohm / 1uF 4.7k Ohm max. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 206: Out-Of-Band Noise Filtering

    0000 8 kHz 0001 11.025 kHz 0010 12 kHz 0011 16 kHz 0100 22.05 kHz 0101 24 kHz 0110 32 kHz 0111 44.1 kHz X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 207: Programmable Data Word Length

    After power supplies ramp up, the CODEC starts its internal initialization sequence and SR. PON_ACK register is changed when the initialization sequence is complete. An interrupt request is sent when the ramp completes. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 208: Agc System Guide

    GIM) in order to best reach this target. AGC_MAX and AGC_MIN fix the limits of the gain variation. ―CODEC Operating modes‖ for the AGC System diagram in the ―CODEC Power Please refer to Diagram‖. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 209: Figure 8-3 Agc Adjusting Waves

    The noise gate threshold is set by the NG_THR register value. The following graph shows a more detailed application. The following graph summarizes the operations and shows more details. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 210: Drc Description

    The part above the threshold id divided by the compression rate (programmed in soft clipping registers DAC_AGC_*); thus, the signal above threshold at the output of the soft clipping DRC is: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 211: Digital Mixer Description

    AIDAC*SEL, AIADC*SEL, MIXDAC*SEL and MIXADC*SEL functionality are applied between the Digital Mixer and the Data interface. The behavior is the following: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 212: Digital Microphone Interface

    CODEC accepts bitstream from digital microphone and converts it into audio data at the sample rate (Fs) selected in FCR_ADC register. CODEC provides a clock (DMIC_CLK) and receives data on X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 213: Timing Diagram

    CODEC can receive simultaneously data from two digital microphones. 8.17.1 Timing Diagram Figure 8-8 Digital microphone timing diagram at MCLK = 12 MHz (DMIC_CLK = 3 MHz) 8.17.2 Timings X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 214: Noise Template (Tbc)

    The following graphic represents the maximum noise allowed on CODEC_AVDD to reach SNR performances of 80 or 95 or 105 dB on the DAC outputs. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 215: Codec Operating Modes

    Normal mode: When CODEC is not in above mode, it is in this mode. This mode has three modes: RECORD mode, REPLAY mode, RECORD_REPLAY mode. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 216: Initial All The Gain

    Power-on sequence When the power supply ramps up, CODEC enters the power-on sequence. During this mode, the CODEC needs to be put in power-down in order to reduce audible pops. Power-down sequence X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 217: Soft Mute Mode

    The CODEC then generates an IRQ and set DAC_MUTE_EVENT (respectively ADC_MUTE_EVENT) register bit to ‘1‘. Figure 8-13 ADC Gain up and gain down sequence X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 218: Power-Down And Sleep Modes

    When SB_SLEEP is set to ‘1‘, CODEC enters the sleep mode. Analog functions - except the voltage biasing references - enter the power-down mode. Thus, the power consumption is reduced without penalizing the start-up time. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 219: Working Modes Summary

    Different working modes are sum-up in the following table (non exhaustive table): Mode Register signal values after a reset mode power-down mode Sleep mode X X X X X X X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 220: Mclk Turn-Off And Turn-On

    To use the embedded CODEC with AIC, the following AIC registers should be set up before start the CODEC: AICFR.ICDC = 1 AICFR.AUSEL = 1 AICFR.BCKD = 0 AICFR.SYNCD = 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 221: Circuits Design Suggestions

    (PSNT2) described in the sections Power Supply Noise Tolerance Template. X1000 Audio codec power supply VDDIO_CODEC VSSIO_CODEC AGND Figure 8-15 Peripheral power supply connection X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 222: Microphone Connection

    Application schematic with differential MIC input (Vmicbias generated on board): XBurst Processor MICBIAS MICBIAS 1 uF MICP MICN 1 uF CODEC_AVSS Application schematic with single-ended MIC input (using MICBIAS pin): X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 223 MICBIAS output current is 4mA max. MICBIAS output noise is 40uVrms max. This configuration is better suited for microphone with single wire + shielding. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 224: Pcb Considerations

    The track length between any signal input of the amplifier and the components must be shorter than 1 cm. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 225: Figure 8-17 Pcb Optimization For Avoiding Emi Issue

    Cmic Micbias decoupling capacitor Refer to +/-20% Microphon Rmic Microphone external resistor connection Cbyline Input bypass capacitor +/-20% > maximum analog power X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 226: Analog Characteristics

    1 kHz sine wave @ Full Scale -1 dB and gains = 0 dB Fs≤ 16 kHz 1 kHz sine wave @ Full Scale -1 dB and gains = 0 dB Fs > 16 kHz X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 227: Microphone / Line Input To Adc Path

    A-weighted, 1 kHz sine wave @ Full Scale -60 over gain range dB and gain GIL*= 0 dB, boost gain GIM* = (DRgr) [0-20]dB X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 228: Table 8-3 Microphone/Line Input Performances

    AIP-AIN to DIL (1) Scales with VREF = VREFP_CODEC- CODEC_AVSS (2) The specified value is extrapolated by adding 60 dB to the measured SNR X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 229: Micbias And Reference

    Parameter Min. Max. Unit Fall Time Rise Time Difference between Fall Time and Rise Time Skew between PWM outputs (*LP, *LN, *RP, *RN) (1) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 230: Characteristics Of The Adc High Pass Filter

    24MHz Wind Noise Filter corner Mode 1 -3 dB 59 Hz frequency Mode 2 -3 dB 117 Hz Mode 3 -3 dB 235 Hz X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 231: Section 5 Memory Interface

    MEMORY INTERFACE Section 5 MEMORY INTERFACE X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 232: Ddr Controller

    Row address width less than 16-bit & Column width less than 12-bit are supported. 9.1.2 Block Diagram Following figure shows the functional block diagram of DDR system. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 233: Register Description

    Please Note that: the DDRC_AHB_CFG_GROUP must not be access under retention mode. Table 9-1 DDRC Register Address Name Group Width Access Description offset DSTATUS DDRC_AHB 0x00 DDR Status Register X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 234 DDRC_AHB 0x34 Multi-media stride register WCMDCT Write command reorder & grouping DDRC_AHB 0x100 (Performance control) RCMDCT Read Channel mode control DDRC_AHB 0x104 (Performance control) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 235 0x310 Bus efficiency data ALUE CLKSTP_ DDRC_APB 0x068 Auto Clock Gating configuration DDRC_S DDRC_APB 0x06C DDR status TATUS PHYRET_ DDRC_APB 0x034 Retention Mode Configuration X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 236: Dstatus

    (reset value) DFI initialization completed ENDIAN: Read-only, indicate the data endian status. Bit [7] Description Remark Little data Endian. (reset value) Big data Endian. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 237 (reset value) CKE1 Pin is high. CKE0: Indicate the CKE0 Pin status of DDR memory. Bit [0] Description Remark CKE0 Pin is low. (reset value) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 238: Dcfg

    1: On-die-termination on; TYPE: Select external memory device type. Bit [19:17] Description Remark Reserved (reset value) Reserved Normal DDR1 (Not support in these version) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 239 If DDR memory is connected to ddr pin cs0, set CS0EN=1. Bit [6] Description Remark DDR Pin CS0 is not in use. (reset value) DDR Pin CS0 is in use. CL: CAS Latency. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 240: Dctrl

    1: Clock can be stopped after some bank‘s row actived ACTPD: Active Power-Down. Some SDRAM devices support Active-Power-Down. By default, ACTPD=0, hardware will percharge all active banks before X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 241 When external device goes to Deep-Power-Down mode, it lose all data store in memory and registers. The memory chip will cut off inner power supply for power saving. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 242 Slow exit power-down enable. CKE: Control the status of CKE pin. Write CKE=1 can set CKE pin to HIGH state. Write CKE=0 would be ignored. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 243: Dlmr

    {MA[9:0],OP[9:0]} for LPDDR2(not support in this version) 0000_0000 For other DDR the low bit 14 bit (reset value) corresponding to external DDR address Pin A[13:0]. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 244: Dtiming1,2,3,4,5,6 (Ddr Timing Configure Register)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 245 RST 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 If the DDR clock period are tCK. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 246 Valid clock after enter self-refresh(tCKSRX = tCKSRE in this version). Delay time is tCKSRE*8 (tCK) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 247 0010 3*8 + 1 tCK. 0011 4*8 + 1 tCK. … … … tMINSR * 8 + 1 … 1101 14*8 + 1 tCK. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 248: Drefcnt (Ddr Auto-Refresh Counter)

    CNT: 8-bit counter; When the value of CNT match the value of CON, flag bit EQU is set high and an auto-refresh command will be issued to DDR memory. READ only. CLK_DIV : Clock Divider. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 249: Dmmap0,1 (Ddr Memory Map Configure Register)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BASE MASK X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 250: Ddlp (Ddr Dfi Low Power Handshake Control Register)

    RST 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 251 BIT12MP as 0, BIT13MP as 1, BIT14MP as 2, BIT0MP as 12, BIT1MP as 13 and BIT2MP as 14. Original address: 11~0 Reserved Remapped address 11~0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 252: Wcmdctrl1 (Performance Wcmd Reorder & Grouping)

    Pend_QoS once, the priority of this command will increase 1, up to 3, which increases the priority to be processed. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 253: Rcmdctrl0 (Performance Rcmd Request Control)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 254: Rcmdctrl1 (Performance Rcmd Request Control)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 255: Boundarysel (Channel Boundary Select)

    Debug usage, don't change this bit [27] CH3_block_wready 0: No wready block (default) 1: Wready bolck Debug usage, don't change this bit [26] CH2_block_wready 0: No wready block (default) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 256 1: 1024byte boundary 2: 2048byte boundary 3: 4096byte boundary [1:0] CH0_boundary 0: 512byte boundary (default) 1: 1024byte boundary 2: 2048byte boundary 3: 4096byte boundary X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 257: Wdatthd0 (Performance Wcmd Request Control)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 Bits Name Description [14] Ch5_wfifo_thd_en 1: Enable 1: Disable (recommended) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 258: Iportpri (Performance Priority Control)

    0: disable, use external priority 1: enable, use the max priority of external and internal priority [15:0] Chn_iport_wpri Priority of channel Chn_iport_rpri 0x3: the highest priority X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 259: Chxqos0,1,2,3,4,5 (Performance Qos Control)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 260: Autosr_En

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Bits Name Description Rrset [31] clkstp_en Function enable X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 261: Ddrc_Status

    DDR PHY can be set into retention mode, which allow power cutting-down. This can save the leakage power in highest level. However, when use this function, please flow the retention flow. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 262: Phyrst_Cfg

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 263: Functional Description

    // INIT DDR PHY //----------------------------------------------------------------------------------------------------------- Configure DDR PHY and finish PHY training process.(relate to DDRPHY spec) //----------------------------------------------------------------------------------------------------------- // DDRC performance control configure (optional) //----------------------------------------------------------------------------------------------------------- X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 264: Change Clock Frequency

    The clock frequency on which DLL in ddr phy works much faster than 200MHz, As the result, when ddr clock is failed to meet this condition (for example, work in 12MHz) , the DLL must be bypassed in X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 265: Data Endian

    S7: further configure for power save Description: S0: Prepare Retention Program Before perform retention enter flow, the program for this flow should be mapped to on chip RAM X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 266: Exit Retention Mode

    Please note that, the retention mode is only used in system sleep mode, which still powering on GPIO. Because GPIO is must for exiting retention operation. 9.6.2 Exit Retention mode Soft ware control flow X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 267 Turn off CPM: ddr gating if it is gated in 'Enter Retention Mode: S7'.  Disable PHY clock isolation PHYRET_CFG.clk_iso_en <= 0  Disable Auto-clk-stp mode CLKSTP.clkstp_en <= 0 S4: Soft reset DDR PHY X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 268 Configure register to exit DCTL.SR <= 0 S17: Polling register to ensure ddrc exit self-refresh mode DDRC_STATUS.ddr_sr_mode = 0 S18: Perform Data training X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 269 CLKSTP_CFG.clkstp_en <= 1  ..others ..S21: Finish DDR is thoroughly get out of Retention mode. Change PC to DDR for normal operation. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 270: Spi Flash Controller(Sfc)

    Dual-I/O SPI, Quad-I/O SPI, Full Dual-I/O SPI, Full Quad-I/O SPI  two data transfer mode: slave mode and DMA mode  Configurable 6 phases for software flow X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 271: Block Diagram

    SINGLE transfer is supported. 10.4.1.2 AHB Master Interface  transfer data in DMA mode  SINGLE, INCR, INCR4, INCR8, INCR16, INCR32 are supported. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 272: Configurable Timing Parameter

    Figure 10-3 Sample point(has delay) 10.4.2.2 AC timing tSETUP(tSLCH), tHOLD(tCHSH), tSH(tSHSL) are configurable. sfc.ce … tSETUP tHOLD sfc.clk … … dev.do … Figure 10-4 AC timing X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 273: Pin Description

    … … … … … command address dummy data sfc.dr … … … … … Full Dual I/O SPI Figure 10-6 Data Format(Dual SPI) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 274: Endian Description

    Following chapter will descript the functions of all software accessible registers. Conventions: Register Address = Base + Address offset The registers can be read and written by AHB2 bus Register read/write attribute X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 275: Map

    DEV_ADR3 0x0000_0000 Base+0x003c Device address of phase3 0xFFFF_FFFF DEV_ADR4 0x0000_0000 Base+0x0040 Device address of phase4 0xFFFF_FFFF DEV_ADR5 0x0000_0000 Base+0x0044 Device address of phase5 0xFFFF_FFFF X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 276: Registers

    1: DMA mode The number of phase in one flow. 001: 1 phase (default) PHASE_NUM 010: 2 phases 011: 3 phases 100: 4 phases X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 277 Hold time of SFC_CE, the time between the last edge of SFC_CLK and SFC_CE de-assertion. 12:11 THOLD 00: half SFC_CLK cycle (default) 01: one SFC_CLK cycle 10: one and a half SFC_CLK cycle X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 278 The default invalid level of SFC_HOLD pin HOLD_DL 0: low 1: high (default) The default invalid level of SFC_WP pin WP_DL 0: low 1: high (default) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 279 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description Flash status mask for comparing. 31:0 DEV_STA_MSK 1: this bit will be checked. 0: this bit will not be checked. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 280 0: format0(default) 1: format1 The needed dummy cycle num (unit: SFC_CLK cycle) 000000: no dummy transfer (default) 22:17 DMY_BITS ..000100: 4 dummy cycles X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 281 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 282 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:3 Reserved Write has no effect. Read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 283 1: FIFO is over-run. This bit will generate the INT_OVER interrupt. 0: no error. UNDER 1: FIFO is under-run This bit will generate INT_UNDR signal. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 284 0: the INT_END is not masked MASK_END 1: the INT_END will be masked (default) 0: the INT_TREQ is not masked MASK_TREQ 1: the INT_TREQ will be masked (default) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 285 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 286: Software Guideline

    In all phases, only one phase can have DATA section.(we call this phase as data phase, other are command phase)  Sections in a phase will be operated by two sequence format: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 287: Multi Phases Flow

    Repeat step 2 for other flow 10.8.3 One phase flow The flow can also be executed by only one phase. The NAND write perspective flow shown in the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 288: Meters Of Dma Operation Need Attention

    (PL) sfc.ce sfc.clk … … … … sfc.io … … … … command Dummy[3:0], address tran Configure the parameter of PL into phase0 registers: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 289: Example (Nand Flash Write With Single Phase In Reg Mode)

    END bit zone 10.8.7 Example (NAND flash write with single phase in REG mode) configure SFC_DEV_CONF and SFC_GLB register program load (PL) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 290 Waiting END and clear. get features command to read the status sfc.ce sfc.clk … … … sfc.io … … … command address rece X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 291: Index

    Time from select pull high to select pull low. See a NOR Flash device spec tSLCH Time from select pull low to clock pull high. See a NOR Flash device spec X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 292: Section 6 System Functions

    SYSTEM FUNCTIONS Section 6 SYSTEM FUNCTIONS X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 293: Clock Reset And Power Controller

    CCLK, HHCLK, H2CLK, PCLK, H0CLK, DDR_CLK frequency can be changed separately for  software by setting registers  MSC clock supports 50M clock Functional-unit clock gating  X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 294: Cgu Block Diagram

    CGU Block Diagram Following figure illustrates a block diagram of CGU. 32.768K SCLK_A L2CAHE 24M/ APLL AHB0 SCLK_M MPLL AHB2 SCLK_A SCLK_M SCLK_A other module SCLK_M X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 295: Cgu Registers

    0x00000000 0x0070 LPCDR LCD pix clock divider Register 0x00000000 0x0064 MSC0CDR MSC0 clock divider Register 0x40000000 0x0068 MSC1CDR MSC1 clock divider Register 0x00000000 0x00A4 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 296 When switching clock source, it should be ensured that the clock switched from and the clock switched to both are running. 29:28 SEL_CPLL 00: stop MUX clock output X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 297 0, writes on H2DIV, PDIV have no affect. 19:16 PDIV Divider for Peripheral Frequency. Specified the PCLK division ratio. Bit 19~16: PDIV Description X1/2 X1/3 X1/4 X1/5 X1/6 X1/7 X1/8 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 298 Divider for AHB0 Frequency. Specified the AHB0 CLK division ratio. Bit 11~8: H0DIV Description X1/2 X1/3 X1/4 X1/5 X1/6 X1/7 X1/8 X1/9 X1/10 X1/11 X1/12 X1/13 X1/14 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 299 Import Note1 : for PDIV and AHB2DIV, AHB2’s clock frequency must be 1 or 2 times of PDIV’s clock frequency. For L2CDIV and CDIV, CPU’s clock frequency must be 1,2,3, or 4 times of X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 300 Software should be wait until H2DIV_BUSY == 0, then may begin another frequency change. H0DIV_B The bit is a read-only bit. It indicates whether the frequency change has X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 301 When DDR_STOP is 1 and CE_DDR is 1, the DDR clock will stop. When DDR_STOP is 0 and CE_DDR is 1, the DDR clock will continue. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 302 When MAC_STOP is 1 and CE_MAC is 1, the MAC clock will stop. When MAC_STOP is 0 and CE_MAC is 1, the MAC clock will continue. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 303 Recommend the De_p is less than 5% and De_n is great than -5%. If the parameter D of AIC M/N divider is in automatic calculation mode, namely I2S_DEN X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 304 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 305 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description MPCS 0: select SCLK_A clock output 1: select MPLL clock output X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 306 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 307 0: USB clock source is EXCLK 1: USB clock source is PLL output divided by USBCDR If UCS == 0, the clock divider is gated, don‘t set CE_USB X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 308 SFC device clock . This register is initialized to 0x00000000 only by any reset. Only word access can be used on SSICDR.the clk relation ship of SFC and SSI is as follows: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 309 When the bit is 0, it indicates frequency change has finished., otherwise it indicates the frequency change is on going Software should be wait until SSI_BUSY == 0, may begin another X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 310 When the bit is 0, it indicates frequency change has finished., otherwise it indicates the frequency change is on going Software should be wait until CIM_BUSY == 0, may begin another frequency change. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 311 50%. Error of duty cycle is: De_p = (ceill( N / M) - (N / M)) / (N / M). ceil: Round toward positive infinity. and: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 312 T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 313 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:3 Reserved Writing has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 314 RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 315 This bit is the power control for otg block in OTG PHY. 19:17 COMPDISTUNE These bits control disconnect threshold adjustment. 3‘b111 +4.5% 3‘b110 3‘b101 +1.5% 3‘b100 Default 3‘b011 -1.5% X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 316 +15mv 2‘b01 -15mv 2‘b00 reserved TXVREFTUNE These bits control HS DC voltage level adjustment. 4‘b1111 +12.5% 4‘b1110 +11.25% 4‘b1101 +10% 4‘b1100 +8.75% 4‘b1011 +7.5% X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 317 RST 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 318 11 PHYCLOCK cycles. Reserved Writing has no effect, read as zero. WORD_I This bit selects utmi data bus width of otg 1: 16bit/30M X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 319 PLL Stabilize Time. Specifies the PLL stabilize time by unit of RTCCLK (approximate 32kHz) cycles. It is used when change PLL multiplier or change PLL from off to on. It is initialized to H‘20. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 320: Pll Operation

    The PLL developed as a macro cell for clock generator. It can generate a stable high-speed clock from a slower clock signal. The output frequency is adjustable and can be up to 1000MHz. The PLL X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 321: Figure 11-1 Block Diagram Of Pll

    PLL output frequency FOUT is calculated from the following equations: NF = 1+ M0 + M1*2 + M2*4 + M3*8 + M4*16 + M5*32 + M6*64 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 322: Main Clock Division Change Sequence

    But, the clock to each peripheral, except the basic blocks, can be stopped selectively by software to reduce the power consumption. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 323: Register Description

    0x00CC CLKGR Clock Gate Register0 0x1FFFFF80 0x 0020 OPCR Oscillator and Power Control Register 0x10801500 0x 0024 MESTSEL asnyc handshake control register 0x00000000 0x00EC X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 324 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 325 The reset value of this register reflects the clock gate information of the relative modules. RST 0: After reset period, the clock is not stopped. RST 1: After reset period, the clock is stopped. Module Description X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 326 CPM will not wait for XX module‘s stop_ack if you stop it‘s clk by set CLKGR.XX. Note2: Scc‘s clk is 1/8 of exclk. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 327 28:26 Reserved Write has no effect, Read as 0 LCD_SR 0: LCD does not enter soft reset mode 1: LCD enters soft reset mode X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 328 Write has no effect, Read as 0 ERNG 0: not enable 1: enable 11.2.2.10 RNG Register (RNG) The RNG Register is a 32-bit read only registers. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 329 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Bits Name Description 31:0 SLPC When SLBC is 1, sleep boot is jumped to SLPC, not true boot as any X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 330 DDRCDR.DCS is stopped in sleep mode 1: those clk is not stopped in sleep mode 21：20 Reserved Write has no effect, read as 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 331: Idle Mode

    When current operation of CPU core has finished and CPU core is idle, CCLK supply to CPU core is stopped. IDLE mode is exited by an interrupt (IRQ or on-chip devices) or a reset. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 332: Sleep Mode

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? ? ? X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 333: Power On Reset

    Then WDT reset source is cleared because of internal reset. The internal reset is asserted for about 10 milliseconds. CPU and peripherals are clocked by EXCLK oscillator output directly. PLL is reset to off state. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 334: Timer/Counter Unit

    TCU2: It can work in sleep mode, but operated more complicated than TCU1 12.2 Pin Description Table 12-1 PWM Pins Description Name Description PWM [4:0] Output PWM channel output signals. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 335: Register Description

    Timer Counter Enable Clear 0x???? 0x018 Register Timer Flag Register 0x003F003F 0x020 TFSR Timer Flag Set Register 0x???????? 0x024 TFCR Timer Flag Clear Register 0x???????? 0x028 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 336: Timer Control Register (Tcsr)

    12.3.1 Timer Control Register (TCSR) The TCSR is a 16-bit read/write register. It contains the control bits for each channel. It is initialized to 0x00 by any reset. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 337 INITL Selects an initial output level for PWM output. 0: Low 1: High PWM_EN PWM output pin control bit. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 338 PCK_EN == 0, RTC_EN == 0 and EXT_EN == 1 < ½ f DIV_CLK PCLK (IN_CLK = EXTAL) PCK_EN == 1, RTC_EN == 0 and EXT_EN == 0 (IN_CLK = PCLK) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 339: Timer Data Full Register (Tdfr)

    But it can be cleared to 0 by setting TCSR.CLRZ to 1, and if the counter is really cleared, TCSR.CLRZ will be set to 0 by hardware. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 340: Timer Counter Enable Register (Ter)

    TCEN 3 Enable the counter in timer 3. 0: Stop counting up 1: Begin counting up TCEN 2 Enable the counter in timer 2. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 341: Timer Counter Enable Set Register (Tesr)

    TCST 3 Set TCEN 3 bit of TER. 0: Ignore 1: Set TCEN 3 bit to 1 TCST 2 Set TCEN 2 bit of TER. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 342: Timer Counter Enable Clear Register (Tecr)

    TCCL 3 Set TCEN 3 bit of TER. 0: Ignore 1: Set TCEN 3 bit to 0 TCCL 2 Set TCEN 2 bit of TER. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 343: Timer Flag Register (Tfr)

    12.3.9 Timer Flag Set Register (TFSR) The TFSR is a 32-bit write-only register. It contains the comparison match flag set bits for all the channels. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 344: Timer Flag Clear Register (Tfcr)

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 345: Timer Mast Register (Tmr)

    Writing has no effect, read as zero. FMASK 7~0 FULL comparison match interrupt mask. 0: Comparison match interrupt not mask 1: Comparison match interrupt mask X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 346: Timer Mask Set Register (Tmsr)

    Writing has no effect, read as zero. 23:16 HMCL 7~0 Set HMASK n bit of TMR. 0: Ignore 1: Set HMASK n bit to 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 347: Timer Stop Register (Tsr)

    1: The clock supplies to timer 3 is stopped STOP 2 0: The clock supplies to timer 2 is supplied 1: The clock supplies to timer 2 is stopped X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 348: Timer Stop Set Register (Tssr)

    1: Set STOP 4 bit to 1 0: Ignore STPS 3 Set STOP 3 bit of TSR. 0: Ignore 1: Set STOP 3 bit to 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 349: Timer Stop Clear Register (Tscr)

    Set STOP 5 bit of TSR. 0: Ignore 1: Set STOP 5 bit to 0 STPC 4 Set STOP 4 bit of TSR. 0: Ignore X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 350: Timer Status Register (Tstr)

    1: The counter 2 is busy now BUSY1 0: The counter 1 is ready now 1: The counter 1 is busy now Reserved Writing has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 351: Timer Status Set Register (Tstsr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:19 Reserved Writing has no effect, read as zero. REALC 2 Clear REAL 2 bit of TSTR. 0: Ignore X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 352: Operation

    Enable the counter. Setting the TESR.TCST bit to 1 to enable the TCNT. NOTE: The input clock and PCLK should follow the rules advanced before. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 353: Disable And Shutdown Operation In Tcu1 Mode

    12.4.5 Read Counter in TCU2 Mode If you want to read the data from register TCNT when the TCU is working, you can check X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 354: Pulse Width Modulator (Pwm)

    Writing TCSR.SD to setting the shutdown mode (Abrupt shutdown or Graceful shutdown). Writing TCSR.PRESCALE to set to 0. Setting TCNT, TDHR and TDFR. Enable the clock. Writing TCSR.PWM_EN to disable PWM. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 355 Enable the counter. Setting the TESR.TCST bit to 1 to enable the TCNT. NOTE: The input clock and PCLK should follow the rules adviced before. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 356: Operating System Timer

    0 - reset to 0 ? - value unknown after reset Table 13-1 Registers Memory Map-Address Base Name Base Description SYS_OST 0x12000000 Address base of SYS_OST X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 357: Timer Clock Control Register (Ostccr)

    Internal clock: CLK/16 Reserved These bits select the TCNT count clock frequency for ost1. Don‘t PRESCALE1 change this field when the channel is running. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 358: Timer Counter Enable Register (Oster, Ostesr, Ostecr)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:2 Reserved Writing has no effect, read as zero. OST2ENS Enable the counter in channel2‘s timer. 0: no effect X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 359: Timer Counter Clear Register (Ostcr)

    Write 1 at this bit to clear channel2's timer OST1CLR Clear the counter in channel1‘s timer. Write 1 at this bit to clear channel1's timer X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 360: Timer Data Full Register (Ost1Dfr)

    Reserved Writing has no effect, read as zero. FFLAG channel1‘s FULL comparison match flag. (OST1CNT = OSTDFR) 0: Comparison not match 1: Comparison match X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 361: Timer Mask Register (Ost1Mr)

    13.2.9 Operating System Timer Counter high 32 bits buffer (OSTCNT2HBUF) The operating system timer counter high 32 bits buffer OSTCNT2HBUF is used to store the high 32 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 362: Operation

    OSTCCR third: Setting the OSTESR.TCST bit to 1 to enable the TCNT again. Setting the TESR.OSTST bit to 1 to enable the OSTCNT again. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 363: Interrupt Controller

    SPEC - special access method, relate to its description 3. Reset Value 1 - reset to 1 0 - reset to 0 ? - value unknown after reset X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 364: Interrupt Controller Source Register (Icsr0)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 365: Interrupt Controller Source Register (Icsr1)

    RST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bits Of ICMR0 Description The corresponding interrupt is not masked. The corresponding interrupt is masked. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 366: Interrupt Controller Mask Register (Icmr1)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 367: Interrupt Controller Mask Clear Register (Icmcr0)

    Will clear the corresponding interrupt mask bit. 14.2.9 Interrupt Controller Pending Register (ICPR0) This register contains the status of the interrupt sources after masking. This register is read only. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 368: Interrupt Controller Pending Register (Icpr1)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 369: Interrupt Mask Register0 For Pdma (Dmr0)

    The corresponding interrupt is active and is not masked to the processor. 14.2.14 Interrupt Source Register1 to PDMA (DSR1) This register contains status of all interrupts. A ―1‖ indicates the corresponding interrupt is pending. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 370: Interrupt Mask Register1 For Pdma (Dmr1)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 371: Software Considerations

    Execute the interrupt handler and unmask it by writing the register ICMCRx when exit the handler. CPU restores the saved environment and exits the interrupt state. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 372: Watchdog Timer

    0 - reset to 0 ? - value unknown after reset Table 15-1 Registers Memory Map-Address Base Name Base Description 0x10002000 Address base of WDT X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 373: Watchdog Control Register (Tcsr)

    Select PCLK as the timer clock input. 1: Enable 0: Disable NOTE: The input clock of timer and the PCLK should keep to the rules as follows: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 374: Watchdog Enable Register (Tcer)

    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 375: Watchdog Timer Counter (Tcnt)

    The clock of WDT can be stopped by setting register TSR, and register TSR can only be set by register TSSR or TSCR. The content of register TSR, TSSR and TSCR can be found in TCU spec. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 376: Pdma Controller

    Features  Support up to 8 independent DMA channels  Descriptor or No-Descriptor Transfer mode compatible with previous Ingenic SOC  A simple Xburst-1 CPU supports smart transfer mode controlled by programmable firmware  Transfer data units: 1-byte, 2-byte, 4-byte, 16-byte, 32-byte, 64-byte, 128-byte ...

  • Page 377: Memory Mapped Register Descriptions

    Channel n Command 0x14 + n*0x20 DDAn Channel n Descriptor Address 0x18 + n*0x20 DSDn Channel n Stride Difference 0x1C + n*0x20 16.4.2 Global Control Registers X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 378: Dma Channel Register Definition

    MCU Interrupt 0x103C NOTES: Grey ones are obsolete registers defined in previous Ingenic SOC. They are relative to clock gating and have no real function, and they are not supported any longer. 16.5 DMA Channel Register Definition 16.5.1 DMA Source Address (DSAn, n = 0 ~ 7)

  • Page 379: Dma Target Address (Dtan, N = 0 ~ 7)

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ？ ？ ？ ？ ？ ？ Bits Name Description 31:6 Reserved Write has no effect, read as zero. Transfer request type. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 380: Dma Channel Control/Status (Dcsn, N = 0 ~ 7)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 381: Dma Channel Command (Dcmn, N = 0 ~ 7)

    RST 0 0 0 0 0 0 0 0 ？ ？ 0 0 ？ ？ ？ ？ ？ ？ ？ ？ 0 ？ ？ ？ 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 382: Table 16-6 Available Rdil

    Programmer must care the detail of the FIFO of the device binding with relative DMA channel to set the correct and best recommended data unit value according to FIFO‘s data width and depth, refer to following table. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 383 4-byte; when setting non-autonomy (TSZ!=7), for transferred bytes in a bus transaction denoted by TSZ, it must not exceed the critical value of triggering DMA request meanwhile must be the times of 4-byte. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 384: Dma Descriptor Address (Ddan, N = 0 ~ 7)

    RST ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ ？ X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 385: Dma Global Register Definition

    MSC(MSC1, MSC2), SSI(SSI1), UART0~4, AIC will be in fast mode. DMAE is a global switch, so software must be careful to toggle it from 0 to 1 or 1 to 0. It is X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 386: Dma Interrupt Pending (Dirqp)

    For example, write 0x00000001 to DDS, DDB0 bit is set to 1 and enable DMA channel 0 to fetch its first descriptor. Write 0 to DDS, no meaning. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 387: Dma Doorbell Set (Dds)

    Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 388: Dma Channel Programmable (Dmacp)

    Description 31:0 DCPn Channel programmable enable. 0, compatible with previous Ingenic SOC; 1, firmware controlled channel 16.6.8 DMA Soft IRQ Pending (DSIRQP) DSIRQP BASE+0x 1020 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

  • Page 389: Dma Soft Irq Mask (Dsirqm)

    1 immediately to raise an IRQ to MCU. Moreover, when an channel m with above attribute is bound with the INTC_IRQ, if DCIRQMm==0, an active INTC_IRQ request will trigger an active CIRQn immediately X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 390: Dma Channel Irq To Mcu Mask (Dcirqm)

    Write has no effect, read as zero. 23:8 SC_OFF Set the offset of the caller‘s data structure for SC_CALL reserved Write has no effect, read as zero. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 391: Mcu Normal Mailbox

    IRQ to main CPU when relative MASK field in DMINT is not set. Note that writing the register is inhibited by HW when DMCS.SCMD == 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 392: Mcu Interrupt

    Available CP0 registers of MCU are not entirely compatible with MIPS PRA spec, they are listed below. CP0 Name Description (number) STATUS (12) Bit 31~27:: reserved, read as zero Bit26: readable; only 1 can bet written into*1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 393: Normal Exceptions Accepted By Mcu

    CPU so that MCU can acknowledge a RESET exception, now MCU begins to run from the PC 0xF4000000. Following is a simple example. Prepare a simple RESET exception handler, total 3 instructions: WAIT //sleep //endless loop X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 394: Dma Manipulation

    0 to DCSn.CTE, and then safely clear DCSn.TT or DCSn.HLT to 0. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 395: Table 16-8 Descriptor Structure

    Transfer Counter 5th (DES4) 31-16 Target Stride Address 15-0 Source Stride Address 6th(DES5) 31-6 Reserved DMA Request Type 7th(DES6) 31-0 Reserved 8th(DES7) 31-0 Reserved X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 396: Figure 16-2 Descriptor Transfer Flow

    X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 397: Descriptor Transfer Mode

    DMA to let DMA rerun properly later. 16.8.3 Descriptor Transfer Interrupt/Stop control DMA descriptor provides a more fast and easy way to transfer data. Usually in a long descriptor X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 398 Note: DIP will raise if the two conditions satisfy, one is this is not the last descriptor, the other is the current TIE in DCMn or TIE in current descriptor is set. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 399: Dma Requests

    DSIRQM.SIRQMn must be set 0, then at expected moment, the MCU sets 1 to DSIRQP.SIRQn to trigger a soft IRQ. It is the responsibility of this soft IRQ‘s handler to remove the IRQ by setting 0 to DSIRQP.SIRQn. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 400: Real Time Clock

    Alarm wakeup  External pin wakeup with up to 2s glitch filter 17.3 Block Diagram PWRDET EXCLK/512 RTCLK RTCLK XRTCLK PPRST_ HIBER WKUP_ PWRON X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 401: Pins Description

    RSW - read and write, but set to 1 by read RWC - read and write, clear to 0 by write 1, write 0 has no effect X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 402: Table 15-1 Registers Memory Map-Address Base

    Hibernate mode Wakeup Status Register in HWRSR 0x00000??? 0x030 Hibernate mode HSPR Scratch pattern register 0x???????? 0x034 WENR Write enable pattern register 0x00000000 0x03C X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 403: Rtc Control Register (Rtccr)

    Write 1 to this bit is ignored. 1HZIE 1Hz interrupt enable. Writing to this bit takes effect immediately without delay. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 404: Rtc Second Register (Rtcsr)

    1Hz pulse if the real time clock is enabled (RTCCR.RTCE = 1). When read, it should be read continued more than once and take the value if the adjacent results are the same. RTCSR is not initialized by any reset. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 405: Rtc Second Alarm Register (Rtcsar)

    (any type of) resets. LOCK Description Write to RTCGR is allowed. Write to RTCGR is forbidden. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 406: Hibernate Control Register (Hcr)

    The HIBERNATE mode Wakeup Filter Counter Register (HWFCR) is a 32-bit read/write register .It filter the glitch generated by a dedicated wakeup pin. The HWFCR is not initialized by any reset. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 407: Hibernate Reset Counter Register (Hrcr)

    The HIBERNATE Wakeup Control Register is a 32-bit read/write register that controls real time clock alarm wake up enable. The reset value only for PPRST_ . X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 408: Hibernate Wakeup Status Register (Hwrsr)

    APD is set and remains set until software clears it. This bit can only be X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 409: Hibernate Scratch Pattern Register (Hspr)

    RST ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 410: Write Enable Pattern Register (Wenr)

    This is a register used to control the enable and set the judge time to reset the chip when extend press the WKUP pin. The are only initialized by PPRST_ and HRST_. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 411: Operation Flow

    Check RTCCR.WRDY, make sure it equals to 1 Write the target register Waiting RTCCR.WRDY equals to 1 to make sure the current write processing was finished. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 412: Normal Mode

    Check RSR to determine what caused the reset. Check PIN/ALM bits of HWRSR in order to know whether or not the power-up is caused by which wake-up from HIBERNATE mode. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 413: Time Regulation

    There could be two clock input to RTC internal clock called rtclk. One is OSC32k clock; the other is EXCLK/512. The software MUST make sure the RTC run in valid clock configuration. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 414: Table 17-4 Clock Select Registers

    NOTE: If using HIBERNATE mode, MUST have both 32KHz crystal (or input 32Khz clock) and 24Mhz EXCLK crystal connected, or RTC time will be insignificant. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 415: Efuse Slave Interface (Efuse)

    RWS - read and write, set to 1 by write 1, write 0 has no effect RC - read only, and clear to 0 by read RS - read only, and set to 1 by read X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 416: Registers Memory Map

    RST 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 417 RD_STROBE Adjust number of h2clk cycles when EFUSE reading STROBE Signed value, h2clk period multiply(RD_ADJ + 3 + RD_STROBE) should greater than 15 ns. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 418 1: protect, security boot enable can write 0: no protect, security boot enable can't write DIS_JTAG Disable JTAG 1: disable JTAG 0: enable JTAG X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 419 2. The EFUSE 1K programmable bits are separated into thirteen segments as below table. The first Segment used to store Ingenic chip id, second segment store 128bit random number, third segment used to store customer id, forth segment store segment protect bit, fifth segment used to store root key, sixth segment used to store chip key, seventh used to sore user key, the last segment used to store NKU.

  • Page 420: Flow

    6. Write control register WR_EN bit to 1 7. Wait status register WR_DONE set to 1. 8. Disconnect VDDQ pin from 2.5V. 9. Write control register PG_EN bit to 0. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 421: Program Security Key Flow

    Use on-chip counter and GPIO to coordinate external supply source. : Only the 1.3.2 flow can be used to program the User Key and NKU Segment, The Root key and Chip key Segment will be programmed at CP by Ingenic, other segments only can program use 1.3.1 flow.
  • Page 422 PERIPHERALS Section 7 PERIPHERALS X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 423: General-Purpose I/O Ports

    PA00, will decide is high level value value value default value the FUNC0 "sd0_(io-0)", "sd0" X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 424: Gpio Port A Summary

    PA28 PRUW08DGZ_G (i-0) sfc_dr(io-0) ssi0_dr(i-0) (i-0) PA29 PRUW08DGZ_G (i-0) sfc_dt(io-0) ssi0_dt(o) (i-0) PA30 PRUW08DGZ_G (i-0) sfc_wp(io-0) ssi0_ce1(o) (i-0) PA31 (i-0) sfc_hold(io-0) ssi0_gpc(o) (i-0) PRUW08DGZ_G X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 425: Gpio Port B Summary

    PB31 is RTC WKUP pin, can only be used as input and interrupt, no pull-up and pull-down. The SLCD rd and ce function only can be used by set PB16/PB18 as normal GPIO function. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 426: Gpio Port C Summary

    The group is a dummy group which is not mapping to any on-chip ports. It is used to avoid 3rd (intermittent) state error during configuration. Please refer 1.4.5 and 1.4.6 for detailed information. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 427: Registers Description

    Address base of GPIO Port B 0x10010200 Address base of GPIO Port C 0x10010300 Address base of GPIO Port D 0x10010700 Address base of GPIO Group Z (Shadow group) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 428: Table 19-7 Gpio Registers

    RW PORT B PULL Disable Register 0x70000000 0x70 PBPENS PORT B PULL Disable Set Register 0x00000000 0x74 PBPENC PORT B PULL Disable Clear Register 0x00000000 0x78 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 429 RW PORT D Pattern 1 Register 0x0000003F 0x30 PDPAT1S PORT D Pattern 1 Set Register 0x00000000 0x34 PDPAT1C PORT D Pattern 1 Clear Register 0x00000000 0x38 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 430: Port A Register Group

    Where n = 0 ~ 31 and PAPINL n = PAPINL0 ~ PAPINL31. The PORT A PIN level can be read by reading PINL n bit in register PAPINL. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 431 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 432 MSKS n Writing 1 to MSKS n will set MSK n to 1 in register PAMSK. Writing 0 to MSKS n will no use. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 433 When INT n = 0 and MSK = 1 (GPIO function): 0: Corresponding pin is used as gpio output 1: Corresponding pin is used as gpio input X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 434 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 435 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 436 FLAGC n When GPIO is used as interrupt function and when write 1 to the bit, the bit FLAG n in PAFLG will be cleared. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 437 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 438: Port B Register Group

    Where n = 0 ~ 31 and INT n = INT31 ~ INT00. Interrupt enable. 0: Corresponding pin is used as device functions or normal gpio 1: Corresponding pin is used as interrupt X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 439 RST 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 440 MSKC n Writing 1 to MSKC n will set MSK n to 0 in register PBMSK. Writing 0 to MSKC n will no use. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 441 PAT1S n Writing 1 to PAT1S n will set PAT1 n to 1 in register PBPAT1. Writing 0 to PAT1S n will no use. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 442 When INTn = 0 and MSK = 1 and PAT1 = 0: 0: Port is GPIO output 0 1: Port is GPIO output 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 443 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 444 Where n = 0 ~ 31 and PEN n = PEN0 ~ PEN31. PEN n is used for setting the port to be PULL function enable. 0: port PULL enable 1: port PULL disable X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 445: Port C Register Group

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 446 Writing 1 to INTS n will set INT n to 1 in register PCINT. Writing 0 to INTS n will no use. 19.4.3.4 PORT C Interrupt Clear Registers (PCINTC,0x18) PORT C GROUP interrupt clear registers. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 447 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 448 When INT n = 0 and MSK = 1 (GPIO function): 0: Corresponding pin is used as gpio output 1: Corresponding pin is used as gpio input X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 449 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:0 PAT0 n Where n = 0 ~ 31 and PAT0 n = PAT00 ~ PAT031. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 450 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 451 FLAGC n When GPIO is used as interrupt function and when write 1 to the bit, the bit FLAG n in PCFLG will be cleared. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 452 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 453 Writing 1 to GFCFG0S n will set glitch filter control signal GFCFG0 n to 0 in register PCGFCFG0. Writing 0 to GFCFG0S n will no use. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 454 Not every PAD support glitch filter control, please check out Function Overview chapter for details. 19.4.3.23 PORT C GLITCH FILTER Configure Register 1 (PCGFCFG1S,0x414) PORT C GROUP glitch filter control bit 1 set registers. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 455 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 456 Writing 1 to GFCFG2C n will clear glitch filter control signal GFCFG2 n to 0 in register PAGFCFG2. Writing 0 to GFCFG2C n will no use. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 457 Writing 0 to GFCFG3S n will no use. 19.4.3.30 PORT C GLITCH FILTER Configure Clear Register 3 (PCGFCFG3C,0x438) PORT C GROUP glitch filter control bit 3 clear registers. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 458: Port D Register Group

    Not every bit for each port is implement this function. please refer 1.3. 19.4.4 PORT D Register Group 19.4.4.1 PORT D PIN Level Registers (PDPINL,0x00) PORT D GROUP level registers. They are read-only registers. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 459 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 460 1: Disable the pin as an interrupt source When INT n = 0: 0: Corresponding pin will be used as device function 1: Corresponding pin will be used as gpio X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 461 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 462 PAT1C n Writing 1 to PAT1C n will set PAT1 n to 0 in register PAPAT1. Writing 0 to PAT1C n will no use. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 463 PAT0S n Writing 1 to PAT0S n will set PAT0 n to 1 in register PAPAT0. Writing 0 to PAT0S n will no use. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 464 Not every PAD support Input Enable Control, please check out Function Overview chapter for details. 19.4.4.15 PORT D FLAG Clear Registers (PDFLGC,0x58) PORT D GROUP flag clear registers. They are read-only registers. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 465 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 466: Port Z Shadow Register Group

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 467 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 468: Gpioz Group Id To Load Register (Pzgid2Ld,0Xf0)

    Shadow register load to work groups Load to GPIO Port A Load to GPIO Port B Load to GPIO Port C Load to GPIO Port D Reserved Reserved X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 469: Program Guide

    GPIOZ. When assert GPIOZ.LD, all the four registers will load their content into target group at the same time. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 470 PzINT, PzMSK, PzPAT0, PzPAT1 are also can be configured straightly. Step2: configure PzGID2LD to specify which port group to load PzGID2LD = 0x1; (0x1 stands for GPIO Port B) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 471: Smb Controller

    PA01/ PC27 SMB serial data SCL1 1-bit PA00/ PC26 SMB serial clock SDA2 1-bit PD01 SMB serial data SCL2 1-bit PD00 SMB serial clock X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 472: Registers

    Fast speed SMB SCL high count 16bits 0x003C SMB_FLCNT 0x20 Fast speed SMB SCL low count 16bits 0x0082 SMB_INTST 0x2C SMB Interrupt Status 12bits 0x000 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 473: Registers And Fields Description

    15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 474 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMBTAR 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 475 20.2.2.3 SMB_SAR (SMB Slave Address Register) SMB_SAR BASE + 0x08 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 476 SMB_CON.RESTART is 0, a STOP followed by a START is issued instead. STOP This bit controls whether a STOP is issued after the byte is sent or received. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 477 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMBSHCNT 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 478 This register must be set before any SMB bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast speed. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 479 Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling SMB or when the CPU X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 480 When there is no longer activity, then with SMB_ENB[0]=0. TXOF Set during transmit if the transmit buffer is filled to X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 481 Writing has no effect, read as zero. MIGC These bits mask their corresponding interrupt status bits in the SMBINTST register. MISTT MISTP MIACT MRXDN X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 482 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TXTL 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 483 15:1 Reserved Writing has no effect, read as zero. CRXUF Read this register to clear the RXUF interrupt (bit 0) of the SMB_INTST register. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 484 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 485 15:1 Reserved Writing has no effect, read as zero. CRXDN Read this register to clear the RX_DONE interrupt (bit 7) of the SMB_INTST register. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 486 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 487 ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 488 1: Slave FSM is not in IDLE state so the Slave part of SMB is Active MSTACT Master FSM Activity Status. 0: Master FSM is in IDLE state so the Master part of SMB is not Active X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 489 0 0 0 0 0 0 Bits Name Description 31:6 Reserved Reserved. TXFLR Contains the number of valid data entries in the transmit FIFO X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 490 Reserved SDAHD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:16 Reserved Reserved. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 491 SCL, if what is on the data bus is not what is supposed to be transmitted, then SMB no longer own the bus. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 492 ABRT_GCALL 1: SMB in master mode sent a General Call and no slave on the bus _NOACK acknowledged the General Call. Reset value: 0x0. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 493 Reset value: 0x0. RDEN Receive DMA Enable. This bit enables/disables the receive DMA channel. 0: Receive DMA disabled 1: Receive DMA enabled Reset value: 0x0. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 494 5)as detailed in the I2C SU:DAT Bus Specification(Please Google "UM10204 pdf"). NOTE: The length of setup time is calculated using [(SMB_SDASU - 1) * (apb_clk_period)], so if the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 495 ACK General Call. When set to 1, SMB responds with an ACK when it receives a General Call. When set to 0, the SMB does not generate General Call interrupts. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 496 When read as 1, SMB is deemed to have forced a NACK during any part of an SMB transfer, irrespective of whether the SMB address matches the slave address set in SMB (SMBSAR register) OR if the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 497: Operating Flow

    1 being set. 20.3 Operating Flow This section provides information on the following topics:  ―Slave Mode Operation‖  ―Master Mode Operation‖ X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 498: Smb Behavior

    STOP condition or addresses another slave after issuing a RESTART condition. 20.3.2 Master Mode Operation This section includes the following topics: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 499 SMB transaction. If the TX FIFO is completely emptied at any stage and SMB_CON.STPHLD is 0, then further writes to the TX FIFO results in an independent SMB transaction. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 500: Slave Mode Operation

    NOTE: Slaves and masters do not have to be programmed with the same type of addressing 7- or 10-bit address. For instance, a slave can be programmed with 7-bit addressing X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 501 SMB_INTM[6] register (MTX_ABRT bit field) being set to 0, then it is recommended that re-using the timing routine (described in the previous step), or a similar one, be used to read the SMBINTST register. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 502 (RFNE) set at 1, must then be treated by software as the equivalent of the RX_FULL interrupt being asserted. Software may read the byte from the SMB_DC register (bits 7:0). X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 503: Disabling Smb

    SMB transfer speed used in the system and supported by SMB. For example, if the highest SMB transfer mode is 400 kb/s, then this tSMB_poll is 25us. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 504: Summary The Condition Could Flush Tx Fifo

    Figure 20-1 illustrates the behavior of the SMB when the Tx FIFO becomes empty while operating as a master transmitter, as well as showing the generation of a STOP condition. Figure 20-1 Master Transmitter — Tx FIFO Empties/STOP Generation X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 505: Figure 20-2 Master Receiver - Tx Fifo Empties/Stop Generation

    Figure 20-5 illustrates operation as a master transmitter where the Stop bit of the SMB_DC register is set and the Tx FIFO is not empty X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 506: Figure 20-5 Master Transmitter - Stop Bit Of Smb_Dc Set/Tx Fifo Not Empty

    Figure 20-8 illustrates operation as a master receiver where the first command loaded after the Tx FIFO is allowed to empty and the Restart bit is set X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 507: Figure 20-8 Master Receiver - First Command Loaded After Tx Fifo Allowed To Empty/Restart

    SMB Controller Figure 20-8 Master Receiver — First Command Loaded After Tx FIFO Allowed to Empty/Restart Bit Set X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 508: Smart Card Controller

    Auto-character repeat in T=0 transmit mode.  Transforms inverted format to regular format and vice versa.   Support stop clock function in some power consuming sensitive applications. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 509: Pin Description

    SCCDR 0x?? 0x10040000 SCCFDR 0x00 0x10040004 SCCCR 0x00000000 0x10040008 SCCSR 0x8000 0x1004000C SCCTFR 0x0173 0x10040010 SCCEGTR 0x00 0x10040014 SCCECR 0x00000000 0x10040018 SCCRTOR 0x00 0x1004001C X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 510: Transmit/Receive Fifo Data Register (Sccdr)

    Transmit or Receive Select. 0 – Reception mode. 1 – Transmission mode. Auto-T2R support. T2R means Transmit turn to Reception. 0 – controlled by SW. 1 – controlled by HW. 28:26 Reserved X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 511 SCC clock stop. 0 – SCC has left or is leaving clock stop mode. 1 – SCC CLKSTP has entered or is entering clock stop mode. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 512: Status Register (Sccsr)

    0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 Bits Name Description 15:11 Reserved 10:0 Value of F/D. The initial value is 0x173(371). X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 513: Extra Guard Timer Register (Sccegtr)

    7 6 5 4 3 2 1 0 RTOR 0 0 0 0 0 0 0 0 Bits Name Description Retry times when parity error detected. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 514: Synchronous Serial Interface(Ssi)

    Two slave select signal (SSI_CE0 / SSI_CE1) supporting up to 2 slave devices  Back-to-back character transmission/reception mode   Loop back mode for testing X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 515: Block Diagram

    FIFO. Read operations automatically target the receive FIFO, while write operations write data to the transmit FIFO. Both the transmit and receive FIFO buffers are 128 entries deep by 17 bits wide. As the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 516: Pin Description

    While SSP and SPI are full-duplex protocols, Microwire uses a half-duplex master-slave messaging protocol. At the start of a frame, a 1 or 2-byte control message is transmitted from the controller to the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 517: Motorola's Spi Format Details

    SSI_CLK … (POL = 1) SSI_CE0/ SSI_CE1 (SSICR1.FRMHLn= 0) … SSI_DT … SSI_DR SSI_GPC Figure 22-3 SPI Single Character Transfer Format (PHA = 1) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 518: Figure 22-4 Spi Back-To-Back Transfer Format

    Back-to-back transfer is performed as transmit-only/full-duplex operation when transmit-FIFO is not empty before the completion of the last character‘s transfer or performed as receive-only operation. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 519: Figure 22-5 Spi Frame Interval Mode Transfer Format (Itfrm = 0, Lfst = 0)

    … SSI_CE0/ SSI_CE1 (SSICR1.FRMHLn = … SSI_DT … SSI_DR SSI_GPC Figure 22-5 SPI Frame Interval Mode Transfer Format (ITFRM = 0, LFST = 0) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 520: Ti's Ssp Format Details

    MSB first or LSB first. At the end of the transfer, SSI_DT retains the value of the last bit sent through the next idle period. 1 SSI_CLK period … SSI_CLK … SSI_CE0 SSI_DT SSI_DR Figure 22-7 TI’s SSP Single Transfer Format X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 521: National Microwire Format Details

    … … … … … … … … … … … X1000 IoT Application Processor Programming Manual … Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved. … … … … … … … … … … … …...

  • Page 522: Figure 22-9 National Microwire Format 1 Single Transfer

    … … SSI_CLK SSI_CE0 1 -- 16-bit command … SSI_DT 2 -- 17-bit data … SSI_DR Figure 22-11 National Microwire Format 2 Read Timing X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 523: Register Description

    The SSI has the following registers: one data, two control, one status, one bit-rate control, and two interval control registers. The table lists these registers. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 524: Ssi Data Register (Ssidr)

    16, the maximum length of one written or read data (is defined in FLEN) can be 17. Transmit-FIFO only contain one read operation command once, or one X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 525: Ssi Control Register0 (Ssicr0)

    And do not output any valid signals on the pins. 0: normal SSI mode; 1: LOOP mode. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 526 SSI will stop the SSI_CLK and negate the SSI_CE0 / SSI_CE1 if necessary. To make sure present transfer is completed, user must read and get SSISR.END = 1 (or SSISR.BUSY = 0). X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 527: Ssi Control Register1 (Ssicr1)

    3 more SSI_CLK cycle delay is added Reserved Writing has no effect, read as zero. ITFRM Frame during interval, selects if the Frame (SSI_CE0 /SSI_CE1) signal is X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 528 These bits set the bit length of every character to be transmitted/received. The maximum data length can be configured is 32 bits. For data length X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 529: Ssi Status Register (Ssisr)

    1: Transmission and/or reception is in process This bit denotes transmit-FIFO is full or not. 0: Transmit-FIFO is not full 1: Transmit-FIFO is full X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 530: Ssi Interval Time Control Register (Ssiitr)

    Counting clock source select. 0: Use SSI bit clock (SSI_CLK) as the interval counter clock source 1: Use 32K clock as the interval counter clock source X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 531: Ssi Interval Character-Per-Frame Control Register (Ssiicr)

    SSIICR is ignored for SSICR1.FMAT  B‘00. The desired transfer number of characters-per-frame is (SSIICR set value + 1). 22.7.8 SSI Clock Generator Register (SSIGR) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 532: Ssi Receive Counter Register (Ssircnt)

    RCNT, the receiving operation will be stopped automatically. 22.8 Software Guideline 22.8.1 Common flow The initial steps are: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 533: Interrupt Operation

    The convention used to interpret the bytes making up a data word when those bytes are stored in computer memory. See Endianness at Wikipedia FIFO First In, First Out, a method for organizing and manipulating a data buffer X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 534 Synchronous Serial Interface(SSI) See Endian See Endian Quad SPI See SPI Serial Peripheral Interface Standard SPI See SPI X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 535: Universal Asynchronous Receiver/Transmitter(Uart)

    UART; From PIN to receive the data processing and put it on the APB bus. For the transmission direction,UART gets the data from the APB bus and sent to the PIN. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 536: Functional Description

    Clear to Send --- Modem Transmission enabled RTS_ Output Request to Send --- UART Transmission request NOTE: UART2, UART1, UART0 support RxD, TxD, RTS_, CTS_. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 537: Data Format Description

    Table 23-2 Registers Memory Map Base Address Name Base Description UART0 0x10030000 Address base of UART0 UART1 0x10031000 Address base of UART1 UART2 0x10032000 Address base of UART2 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 538: Register And Fields Description

    RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ？ ？ ？ ？ ？ ？ ？ ？ Bits Name Description X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 539 Divisor is shown by the formula when UMR and UACR are not set: Baud Rate = (UART device clock) / (16 * Divisor) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 540 The UART Interrupt Enable Register (UIER) contains the interrupt enable bits for the five types of interrupts (receive data ready, timeout, line status, and transmit data request, and modem status) that set a value in UIIR. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 541 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 542: Table 23-4 Uart Interrupt Identification Register Description

    FIFO mode: Trigger FIFO mode: Reading URBR Highest Ready threshold was reached till below trigger threshold. Non-FIFO mode: URBR Non-FIFO mode: Empty full URBR X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 543 1: Enable UART DMA Mode Enable. 0: Disable DMA mode 1: Enable DMA mode TFRT Transmit Holding Register Reset. 0: Not reset 1: Reset transmit FIFO X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 544 0: Odd parity 1: Even parity PARE Parity Enable. Enables a parity bit to be generated on transmission or checked on reception. 0: No parity X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 545 RTS bit of the UMCR is connected to CTS bit of UMSR respectively. Loopback mode must be selected before the UART is enabled. 0: Normal operation mode X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 546 1: All the data in the transmit shifter and UTHR has been shifted out TDRQ Transmit Data Request. Set when UTHR has half or more empty location (FIFO mode) or empty X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 547 Set when both receive buffer and shifter are full and new data is received which will be lost. Cleared when the processor reads the ULSR. 0: No data has been lost 1: Receive data has been lost X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 548 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 549 IrDA decoder before it is fed to the UART (RCVEIR = 1) or bypass IrDA decoder and is fed directly to the UART (RCVEIR = 0). X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 550 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:12 Reserved Writing has no effect, read as zero. 11:0 If the nth bit of the register is： X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 551 Description 31:7 Reserved Writing has no effect, read as zero. TCNT TXFIFO Counter. Indicates there are n data in TXFIFO when this field is X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 552: Operation Flow

    If ULSR.DRY = 1 or receive data request interrupt generates, then read ULSR.FIFOE or see if there is error interrupt, if FIFOE = 1, it means received data has receive error, then go to error X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 553: Receive Error Handling

    Each UART supports slow infra-red (SIR) transmission and reception by setting ISR.XMITIR and ISR.RCVEIR to 1 (make sure the two bits are not set to 1 at the same time because SIR can‘t operate X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 554: For Any Frequency Clock To Use The Uart

    A 12-bit register is used to indicate where to insert the extra cycles. The first line is the time expected The second line is the time actual The third line is the time error X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 555 M+1 cycles to transmit or receive the bit To set UACR value you must ensure that the max error of each bit should be less than 0.5P X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 556: Index

    Write 0x408 to UACR ： cycle/bit M，M，M，M+1，M，M，M，M，M，M，M+1，M ： UACR 23.9 Index Table 23-5 Description of Proprietary Vocabulary Name Description UART universal asynchronous receiver/transmitter Serial infrared X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 557: Mmc/Sd Ce-Ata Controller（Msc

    Supports CE-ATA digital protocol commands  Support Command Completion Signal and interrupt to CPU  Command Completion Signal disable feature  The maximum block length is 4096bytes X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 558: Block Diagram

    CMD/DAT will return to push-pull mode, to have maximum driving for maximum operation frequency. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 559: Msc Reset

    Inactive State. The host then issue the command All_Send_CID (CMD2) to each card and get its unique card identification (CID) number. Card that is unidentified, that is, which is in Ready State, send X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 560: Card Access

    WRITE_BLOCK command. The host may poll the status of the card with a SEND_STATUS command (CMD13) at any time, and the card will respond with its status. The status X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 561 To facilitate selection, a first command with the starting address is followed by a second command with the final address, and all sectors (or groups) within this range will be selected for erase. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 562: Protection Management

    The password and its size is kept in an 128-bit PWD and 8-bit PWD_LEN registers, respectively. These registers are non-volatile so that a power cycle will not erase them. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 563: Table 24-1 Command Data Block Structure

    16-bit CRC. The data block shall indicate the mode (SET_PWD), the length (PWD_LEN) and the password itself. In case that a password replacement is done, then X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 564 (PWD_LEN is not 0), then the card will be locked automatically after power on reset. An attempt to lock a locked card or to lock a card that X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 565: Card Status

    (which may be stored in a local status register) to the host. If not specified otherwise, the status entries are always related to the previous issued command. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 566: Table 24-2 Card Status Description

    An invalid selection of sectors or groups for erase occurred. 0: No Error 1: Error WP_VIOLATION E R X Attempt to program a write X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 567 The card could not sustain data programming in stream write mode. 0: No Error 1: Error CID/CSD_OVERWRITE E R X Can be either one of the following errors. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 568 0: No Ready 1: Ready Reserved APP_CMD The card will expect ACMD, or indication that the command has been interpreted as ACMD. 0: Disable X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 569: Sd Status

    I/O device. I/O functions may be identical or completely different from each other. All I/O functions are organized as a collection of registers, and there is a maximum of 131,072 registers X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 570 SDIO device. To determine if a card supports the Read Wait protocol, the host must test capability bits in CCCR. The timing for Read Wait is base on the Interrupt Period. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 571: Clock Control

    CMD16. The response to CMD56 will be R1b (card status + busy indication). 24.5 Pins Description  MSC_CLK, output, host to card clock signal.  MSC_CMD, inout, bidirectional command/response signal.  MSC_DAT[7:0], inout, bidirectional data bus. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 572: Data Format Description

    . . . Block length Figure 24-2 msc data format 24.7 Register Description Following chapter will describe the functions of all software accessible registers. Conventions: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 573: Register Memory Map

    MSC_RDTO 0x00FFFFFF 0x14 MSC_BLKLEN 0x0000 0x18 MSC_NOB 0x0000 0x1C MSC_SNOB 0x???? 0x20 MSC_IMASK 0xFFFFFFFF 0x24 MSC_IFLG 0x2000 0x28 MSC_CMD 0x00 0x2C 0x00000000 0x30 MSC_ARG X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 574: Register And Fields Description

    CE_ATA device. After sending CMD12, MSC_STAT. AUTO_CMD12_DONE is set and generates interrupt to CPU. After sending the CCSD, controller automatically clears the SEND_AS_CCSD bit. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 575 RST 0 0 0 ? ? ? ? ? 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 576 Indicates whether data transmission to card has completed. 0: not completed 1: completed END_CMD_RES Indicates whether command and response/no-response sequence have been completed 0: not completed 1: completed X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 577 24.7.2.3 MSC Clock Rate Register (MSC_CLKRT,0x08) The MSC_CLKRT register specifies the frequency division of the MMC/SD bus clock. The software is responsible for setting this register. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 578 CCS from device 1: interrupts are enabled in CE_ATA device, or RW_BLK command expects command completion signal from device If the command expects Command Completion Signal X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 579 , RXFIFO_RD_REQ will be set to 1. 00: more than or equal to 16 01: more than or equal to 32 10: more than or equal to 64 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 580 It is also used to reset RX_FIFO and TX_FIFO. 0: Current command without data transfer 1: Current command with data transfer RESPONSE_FORMAT Response Type Selection. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 581 MMC/SD host controller turns on the time-out error for the received data. The unit is MSC_CLK. 24.7.2.7 MSC Block Size Register (MSC_BLKLEN,0x18) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 582 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Bits Name Description 15:0 MSC_SNOB Specify the number of successfully transferred blocks for a multiple block transfer. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 583 Mask the interrupt of DMA end. 0: Not masked. 1: Masked. AUTO_CMD12_DONE Mask the interrupt AUTO_CMD12_DONE. 0: Not masked 1: Masked DATA_FIFO_FULL 0: Not masked X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 584 TXFIFO_WR_REQ, and RXFIFO_RD_REQ are masked off with the DMA function is used. The software is responsible for monitoring these bit in program I/O mode. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 585 Indicates the BAR interrupt. 0: the interrupt is not detected 1: the interrupt is detected Write 1 to clear. DMAEND Indicates the DMA end interrupt. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 586 Receive FIFO read request. Set if data FIFO becomes half full (the number of words is >= 8) or the entries in data FIFO are the last read data. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 587 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 588 The MSC_TXFIFO is used to write the data to a card. It is write-only to the software, and is written on 32-bit boundary. The size of this FIFO is 128 x 32-bit. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 589 Clock will stop when card in idle (should be normally set to only MMC and SD cards. For SDIO cards, if interrupts must be detected, clock should not be stopped) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 590 0: Special DMA in MSC controller is used 1: Common DMA in DMAC controller is used DMAEN DMA Function Enable 0: Disable DMA function 1:Enable DMA function X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 591 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 592 If the interrupt mask bit MSC_IMASK.DMAEND is 0b, the interrupt flag MSC_IFLG. DMAEND will be set to 1b also. 1: DMA will continue to fetch another descriptor. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 593 RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:0 RTCNT This field indicates how many data in word units are stored in RTFIFO. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 594: Operation Flow

    24.8.2 DMA and Program I/O Software may communicate to the MSC controller via the DMA or program I/O. The SDMA and CDMA X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 595 Step 1: Prepare the descriptor in system memory Step 2: If the address is not word boundary, it is suggested to configure MSC_DMAC.ALIGNEN and X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 596: Start And Stop Clock

    Write MSC_CTRL with 0x01 to stop the MMC/SD bus clock. Wait until MSC_STAT[CLK_EN] becomes zero. To start the clock the software writes MSC_CTRL with 0x02. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 597: Software Reset

    Step 1. Check whether SDIO card is inserted. Step 2. Check whether SDMEM card is inserted. Step 3. Check whether MMC cards are inserted. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 598 Because there may be several MMC card, so some steps (5 ~ 8) should be repeated several times. The commands are sent as follows: Step 1. Send CMD1 (SEND_OP_CMD) to validate voltage (the general OCR value is 0x00FF88000). X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 599: Single Data Block Write

    MSC_IFLG [PROG_DONE] interrupt. This ensures that the card is not in the busy state. In addition, CMD26 (PROGRAM_CID), CMD27 (PROGRAM_CSD), CMD42 (LOCK/UNLOCK), CMD56 (GEN_CMD: write) and CMD53 (single block write) operations are similar to single block write. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 600: Single Block Read

    For SDIO card, CMD53 (multiple block write) is also similar, but when IO abort (CMD52) is sent, MSC_CMDAT [IO_ABORT] should be 1. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 601: Multiple Block Read

    Open-ended or SDIO Stop reading in advance (not Set MSC_CTRL [EXIT_MULTIPLE]. infinite write MSC_NOB blocks) Wait for DATA_TRAN_DONE interrupt. Send CMD12 or CMD52. (IO abort) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 602: Stream Write (Mmc)

    If WRITE_BL_PARTIAL is not set, 16 more stuff bytes need to be written after the useful X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 603: Stream Read (Mmc)

    Clear the MSC_CMDAT [INIT] bit. Start the operation. Write MSC_IMASK with some value to unmask the expected interrupts. Then the software must perform the following steps: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 604: Sdio Suspend/Resume

    Wait for the MSC_IFLG [DATA_TRAN_DONE] interrupt. Send STOP_TRANS (CMD12) or I/O abort (CMD52). Wait for the MSC_IFLG [END_CMD_ERS] interrupt. Wait for the MSC_IFLG [DATA_TRAN_DONE] interrupt. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 605: Index

    CMD16 SET_BLOCKLEN CMD17 READ_SINGLE_BLOCK CMD18 READ_MULTIPLE_BLOCK Open-ended CMD18 READ_MULTIPLE_BLOCK Predefine blocks CMD20 WRITE_DAT_UNTIL_STOP CMD23 SET_BLOCK_COUNT CMD24 WRITE_SINGLE_BLOCK CMD25 WRITE_MULTIPLE_BLOCK Open-ended CMD25 WRITE_MULTIPLE_BLOCK Predefine blocks X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 606 NOTE: For stream read/write, STOP_CMD is sent after finishing data transfer. For write, STOP_CMD is with the last six bytes. For read, STOP_CMD is sent after receiving data and card sends some data which MSC ignores. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 607: Otg Controller

    Supports INCR4, INCR8, INCR16, INCR, and SINGLE transfers on the AHB Slave interface   Software-selectable AHB burst type on AHB Master interface in DMA mode X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 608: Block Diagram

    Figure 25-2 OTG Internal DMA mode 25.3 Pin Description Table 25-1 OTG Pins Description Name Type Description Inout Data Positive Inout Data Minus Inout Identification DRVVBUS Charge pump enable X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 609: Register Map

    3FFFFh Figure 25-3 OTG CSR Memory Map 25.4.2 Register Maps The tables in this section provide high-level summaries of each register and register group. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 610: Global Csr Map

    054h "Core LPM Configuration Register (GLPMCFG)" 0x58h Reserved GDFIFOCFG 05Ch "DFIFO Software Config Register (GDFIFOCFG)" GADPCTL 0x60h "ADP Timer, Control and Status Register (GADPCTL)" X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 611: Host Mode Csr Map

    Table 25-5 Device Mode CSR Map (800h-BFFh) Acronym Offset Address Register Name 800h-ACh Device Logical IN Endpoint-Specific Registers DCFG 800h Device Configuration Register (DCFG) DCTL 804h Device Control Register (DCTL) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 612 Device Endpoint-n Interrupt Register (DIEPINTn/DOEPINTn) 90Ch Reserved DIEPTSIZ0 910h Device Endpoint 0 Transfer Size Register (DIEPTSIZ0/DOEPTSIZ0) DIEPTSIZn 910h Device Endpoint-n Transfer Size Register (DIEPTSIZn/DOEPTSIZn) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 613: Data Fifo (Dfifo) Access Register Map

    F000h-FFFCh WO/RO Access Device OUT Endpoint 14/Host IN Channel 14: DFIFO Read Access Device IN Endpoint 15/Host OUT Channel 15: DFIFO Write 10000h-10FFCh WO/RO X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 614: Register Descriptions

    Register field can be read by the application (Read), can be set to 1'b1 by Self Clear or Write the core on certain internal or USB or AHB events (Self Set), and can be X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 615: Overview Of Commonly Used Register Bits

    Host mode or Device mode. It contains USB and USB-PHY related configuration parameters. The application must program this register before starting any transactions on either the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 616 UTMI+ PHY with an 8- or 16-bit interface. 1'b0: 8 bits 1'b1: 16 bits "Host Configuration This register configures the core after power-on. Do not make X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 617 The application programs this field with the type of PID to use for the initial transaction. The host maintains this field for the rest of the transfer.  2'b00: DATA0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 618 USB host to which the core is connected. See "Device Initialization" in the Programming Guide for details. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 619: Global Registers

    Table 25-8 Control and Status Register: GOTGCTL Field Description Mode Reset Access 31:26 Reserved Host and Device Chirp On Enable (ChirpEn) Device 1'b0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 620 Note: If you do not enable OTG features (such as SRP and HNP), the read reset value will be 1.The vbus assigns the values internally for non- SRP or non-HNP configurations. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 621 B-Peripheral Session Valid OverrideValue (BvalidOvVal) Device 1'b0 This bit is used to set the Override value for Bvalid signal only when GOTGCTL.BvalidOvEn is set. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 622 1'b0 The application sets this bit to initiate a session request only on the USB. The application can clear this bit by writing a X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 623: Table 25-9 Interrupt Register: Gotgint

    Configuration register (GUSBCFG.HNPCap or GUSBCFG.SRPCap, respectively). A-Device Timeout Change (ADevTOUTChg) Host and 1'b0 R_SS_W The core sets this bit to indicate that the A-device has Device X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 624: Table 25-10 Ahb Configuration Register: Gahbcfg

    Mode Reset Access 31:25 Reserved Host and Device 1‘b0 Inverse Descriptor Endianness(InvDescEndianness) Host and 1'b0: Descriptor endianness is similar to the AHB Master Device X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 625 Host and 1'b0 This bit is programmed to enable the functionality to wait Device for the system DMA Done Signal for the DMA Write X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 626  1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is half empty  1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 627  1'b0: Mask the interrupt assertion to the application.  1'b1: Unmask the interrupt assertion to the application. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 628: Table 25-11 Usb Configuration Register: Gusbcfg

    IC_USB TrafficPullRemove Control (IC_USBTrafCtl) Device 1'h0 When this bit is set, pullup/pulldown resistors are detached from the USB during traffic signaling, per section 6.3.4 of the IC_USB X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 629 SRP.  1'b0: Data line pulsing using utmi_txvalid (default).  1'b1: Data line pulsing using utmi_termsel. ULPI External VBUS Indicator (ULPIExtVbusIndicator) Host 1'b0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 630 In FS and LS modes, the PHY can usually operate on a 48-MHz clock to save power.  1'b0: 480-MHz Internal PLL clock  1'b1: 48-MHz External Clock X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 631 PHY domain must be tied to the appropriate values. ULPI DDR Select (DDRSel) Host and 1'h0 The application uses this bit to select a Single Data Rate Device X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 632 The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for full-speed operation is 16 to 18 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 633: Table 25-12 Reset Register: Grstctl

    Non-periodic TxFIFO flush in Host mode Non-periodic TxFIFO flush in device mode when in shared FIFO operation Tx FIFO 0 flush in device mode when in dedicated FIFO mode X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 634 The application must only write to this bit after checking X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 635 Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed.  Any transactions on the AHB Master are terminated X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 636: Table 25-13 Interrupt Register: Gintsts

    Field Description Mode Reset Access Resume/Remote Wakeup Detected Interrupt (WkUpInt) Host 1'b0 R_SS_W Wakeup Interrupt during Suspend(L2) or LPM(L1) state.  During Suspend(L2): Device X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 637 LPM- Capable (LPMCap) field is set to 1 and the User HW Config3 register's OTG_ENABLE_LPM bit is set Periodic TxFIFO Empty (PTxFEmp) Host 1'b1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 638 For example, after detecting an endpoint mismatch, the application:  Sets a global non-periodic IN NAK handshake X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 639 OUT endpoint on which the interrupt occurred, and then read the corresponding Device OUT Endpoint-n Interrupt (DOEPINTn) register to determine the exact cause of the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 640 USB Reset (USBRst) Device 1'b0 R_SS_W The core sets this bit to indicate that a reset is detected on only X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 641 Non-periodic Transmit Request Queue. The half or completely empty status is determined by the Non-periodic TxFIFO Empty Level bit in the Core AHB Configuration register X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 642 Current Mode of Operation (CurMod) Host 1'b0 Indicates the current mode.  1'b0: Device mode Device  1'b1: Host mode X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 643: Table 25-14 Interrupt Mask Register: Gintmsk

    This bit is enabled only when device periodic endpoints are enabled in Dedicated TxFIFO mode. OUT Endpoints Interrupt Mask (OEPIntMsk) Device 1'b0 only IN Endpoints Interrupt Mask (IEPIntMsk) Device 1'b0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 644 Reserved Host and Device 25.5.3.8 Receive Status Debug Read/Status Read and Pop Registers (GRXSTSR/GRXSTSP)  Offset for Read: 01Ch  Offset for Pop: 020h X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 645: Table 25-15 Host Mode Receive Status Debug Read/Status Read And Pop Registers

    This is the least significant 4 bits of the (micro)frame number in which the packet is received on the USB. This field is supported only when isochronous OUT endpoints are supported. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 646: Table 25-17 Receive Fifo Size Register: Grxfsiz

    The application can program the RAM size and the memory start address for the Non-periodic TxFIFO. Note: The fields of this register change, depending on host or device mode. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 647: Table 25-18 Non-Periodic Transmit Fifo Size Register: Gnptxfsiz

    Description Reset Access 31:24 Top of the Non-periodic Transmit Request Queue (NPTxQTop) 7'b0 Entry in the Non-periodic Tx Request Queue that is currently being X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 648: Table 25-21 User Hw Config1 Register: Ghwcfg1

    This 32-bit field uses two bits per endpoint to determine the endpoint direction. Endpoint  Bits [31:30]: Endpoint 15 direction  Bits [29:28]: Endpoint 14 direction X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 649: Table 25-22 User Hw Config2 Register: Ghwcfg2

     2'b10: 8  Others: Reserved This field is configured using parameter "Name: OTG_NPERIO_TX_QUEUE_DEPTH". Reserved Multi Processor Interrupt Enabled (MultiProcIntrpt) Configurable  1'b0: No X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 650 1'b0: Multi-point application (hub and split support) 1'b1: Single-point application (no hub and no split support) This field is configured using parameter "Name: OTG_SINGLE_POINT". X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 651: Table 25-23 User Hw Config3 Register: Ghwcfg3

     0 - No Battery Charger Support  1 - Battery Charger support present. OTG_ENABLE_HSIC HSIC mode specified for Mode of Operation in coreConsultant X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 652 The application uses this bit to indicate the DWC_otg core's OTG capabilities.  1'b0: Not OTG capable  1'b1: OTG Capable This field is configured using parameter "Name: OTG_MODE". X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 653: Table 25-24 User Hw Config4 Register: Ghwcfg4

    OTG_EN_DESC_DMA". 29:26 Number of Device Mode IN Endpoints Including Control Endpoints Configurable (INEps) Range 0 -15  0:1 IN Endpoint  1:2 IN Endpoints X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 654 UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width Configurable (PhyDataWidth) When a ULPI PHY is used, an internal wrapper converts ULPI to UTMI+.  2'b00: 8 bits X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 655: Table 25-25 Global Dfifo Software Config Register: Gdfifocfg

    "FIFO RAM Allocation" in the Programming Guide. The DWC_otg core does not have any corrective logic if the FIFO sizes are programmed incorrectly. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 656: Table 25-26 Host Periodic Transmit Fifo Size Register: Hptxfsiz

    The power- on reset value of this register is the sum of the Largest Rx Data FIFO Depth, Largest Non-periodic Tx Data FIFO Depth, and all lower numbered Largest Device Mode Periodic Tx Data FIFOn Depth specified . X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 657: Host Mode Registers

    OTG_TX_DINEP_DFIFO_DEPTH_ 1. 25.5.4 Host Mode Registers These registers affect the operation of the core in the Host mode. Host mode registers must not be X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 658: Table 25-29 Host Configuration Register: Hcfg

    NOTE: This bit must be modified only once after a reset. The following combinations are available for programming:  GAHBCFG.DMAEn=0, HCFG.DescDMA=0 => Slave mode X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 659 48MHZ. When you select a 6 MHz clock during LS Mode, you must do a soft reset (for 1.1 FS transceiver Interface)  Others: Reserved X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 660: Table 25-30 Host Frame Interval Register: Hfir

    25.5.4.3 Host Frame Number/Frame Time Remaining Register (HFNUM)  Offset: 408h This register indicates the current frame number. It also indicates the time remaining (in terms of the number of X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 661: Table 25-31 Host Frame Number/Frame Time Remaining Register: Hfnum

    Periodic Transmit Request Queue. This queue holds both IN and OUT requests.  8'h0: Periodic Transmit Request Queue is full  8'h1: 1 location available  8'h2: 2 locations available X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 662: Table 25-33 Host All Channels Interrupt Register: Haint

    Reset Access 31:16 Reserved 15:0 Channel Interrupt Mask (HAINTMsk) 16'h0 One bit per channel: Bit 0 for channel 0, bit 15 for channel 15 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 663: Table 25-35 Host Port Control And Status Register: Hprt

    2'b0 Indicates the current logic level USB data lines  Bit [10]: Logic level of D+  Bit [11]: Logic level of D- Reserved X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 664 1'b1: Resume driven When LPM is enabled and the core is in the L1 (Sleep) state, setting this bit results in the following behavior: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 665 25.5.4.7.1 Moving the Host Core to Test Mode To move the DWC_otg core to test mode, you must set HPRT.Port Test Control. Complete the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 666: Table 25-36 Host Channel-N Characteristics Register: Hccharn

    This field is not applicable for Scatter/Gather DMA mode and need not be programmed by the application and is ignored by the core. 28:22 Device Address (DevAddr) 7'h0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 667 1'b0: OUT  1'b1: IN 14:11 Endpoint Number (EPNum) 4'h0 Indicates the endpoint number on the device serving as the data source or sink. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 668: Table 25-37 Host Channel-N Split Control Register: Hcspltn

    Host Channels Interrupt bit of the Core Interrupt register (GINTSTS.HChInt) is set. Before the application can read this register, it must first read the Host All X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 669: Table 25-38 Host Channel-N Interrupt Register: Hcintn

    Bit stuff error  False EOP In Scatter/Gather DMA mode, the interrupt due to this bit is not set. NYET Response Received Interrupt (NYET) 1'b0 R_SS_WC X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 670  Offset: 50Ch + (Channel_number * 20h) This register reflects the mask for each channel status described in the previous section.  Mask interrupt: 1'b0  Unmask interrupt: 1'b1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 671: Table 25-39 Host Channel-N Interrupt Mask Register: Hcintmskn

    Host Channel-n Transfer Size Register (HCTSIZn)  Channel_number: 0n15  Offset: 510h + (Channel_number * 20h) In Scatter/Gather DMA mode, the HCTSIZn register is defined as described inTable 25-40. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 672: Table 25-40 Host Channel-N Transfer Size Register: Hctsizn

    SCHED_INFO (Schedule information) 8'h0 Every bit in this 8 bit register indicates scheduling for that microframe. Bit 0 indicates scheduling for 1 st microframe and bit X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 673  Offset: 514h + (Channel_number * 20h) This register is used by the OTG host in the internal DMA mode to maintain the current buffer pointer X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 674: Table 25-41 Host Channel-N Dma Address Register: Hcdman

    0 to 63. (Non 0 - 1 descriptor. lsoc) 63- 64 descriptors. This field indicates the current descriptor processed in the list. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 675: Device Mode Registers

    Some of them affect all the endpoints uniformly, while others affect only a specific endpoint. Device Mode registers fall into two categories: Device Logical IN Endpoint-Specific Registers X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 676: Table 25-44 Device Configuration Register: Dcfg

    When the Scatter/Gather DMA option selected during configuration of the RTL, the application can set this bit during initialization to enable the Scatter/Gather DMA operation. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 677 32 KHz during a suspend. This bit can only be set if USB 1.1 Full-Speed Serial Transceiver Interface has been selected. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 678: Table 25-45 Device Control Register: Dctl

    1'b0: After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the DOEPDMA descriptor. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 679 1: Packets are not flushed when an ISOC IN token is received for an elapsed frame. The core ignores the frame number, sending packets as soon as the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 680 The application must set this bit only after making sure that the Global IN NAK Effective bit in the Core Interrupt Register (GINTSTS.GINNakEff) is cleared. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 681 USB host. The application must set this bit to instruct the core to exit the Suspend state. As specified in the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 682: Table 25-46 Minimum Duration For Soft Disconnect

    When the core is operating at high speed, this field contains a microframe number. When the core is operating at full or low speed, this field contains X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 683 IN endpoint. The IN endpoint interrupt for a specific status in the DIEPINTn register can be masked by writing to the corresponding bit in this register. Status bits are X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 684: Table 25-48 Device In Endpoint Common Interrupt Mask Register: Diepmsk

    31:15 Reserved NYET Interrupt Mask (NYETMsk) 1'h0 NAK Interrupt Mask (NAKMsk) 1'h0 Babble Interrupt Mask (BbleErrMsk) 1'h0 11:10 Reserved BNA interrupt Mask (BnaOutIntrMsk) 1'h0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 685: Table 25-50 Device All Endpoints Interrupt Register: Daint

    However, the Device All Endpoints Interrupt (DAINT) register bit corresponding to that interrupt is still set. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 686: Table 25-51 Device Endpoints Interrupt Mask Register: Daintmsk

    This bit is set when the write pointer wraps. It is cleared when the learning queue is cleared. Reserved IN Token Queue Write Pointer (INTknWPtr) 5'h0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 687: Table 25-53 Device In Token Sequence Learning Queue Register 2: Dtknqr2

    A read from this register returns the last 8 endpoint entries of the learning queue. Table 25-55 Device IN Token Sequence Learning Queue Register 4: DTKNQR4 Field Description Reset Access 31:0 Endpoint Token (EPTkn) 32'h0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 688: Table 25-56 Device Vbus Discharge Time Register: Dvbusdis

    This register is valid only for device mode in Dedicated FIFO operation (OTG_EN_DED_TX_FIFO=1). Thresholding is not supported in Slave mode and so this register must not be programmed in Slave mode. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 689: Table 25-58 Device Threshold Control Register (Dthrctl)

    When the value of AHBThrRatio is 2'h00, the threshold length must be at least 8 DWORDS. If the AHBThrRatio is nonzero, the application must ensure that X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 690: Table 25-59 Device In Endpoint Fifo Empty Interrupt Mask Register: Diepempmsk

     Bits in this register are set and cleared when the application sets and clears bits in the corresponding Device Endpoint-n Interrupt register (DIEPINTn/DOEPINTn).  The interrupt is automatically cleared once the DOEPINTn / DIEPINTn interrupt is cleared by the application. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 691: Table 25-60 Device Each Endpoint Interrupt Register: Deachint

    Device Each In Endpoint-n Interrupt Register (DIEPEACHMSKn)  Offset 840h  Endpoint_number: 0=< n =< 15  Offset for IN endpoints: 840h + (Endpoint_number * 4h) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 692: Table 25-62 Device Each In Endpoint-N Interrupt Register: Diepeachmskn

    DOEPINTn register can be masked by writing 0 to the corresponding bit in this register. Status bits are masked by default.  Mask interrupt: 1'b0  Unmask interrupt: 1'b1 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 693: Table 25-63 Device Each Out Endpoint-N Interrupt Register: Doepeachmskn

    The core clears this bit before setting the following interrupts on this endpoint:  Endpoint Disabled  Transfer Completed Endpoint Disable (EPDis) 1'b0 R_WS_SC X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 694 USB Active Endpoint (USBActEP) 1'b1 This bit is always set to 1, indicating that control endpoint 0 is always active in all configurations and interfaces. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 695: Table 25-65 Device Out Endpoint 0 Control Register: Doepctl0

    1'b0 A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 696 2'b00: 64 bytes  2'b01: 32 bytes  2'b10: 16 bytes  2'b11: 8 bytes 25.5.5.22 Device Endpoint-n Control Register (DIEPCTLn/DOEPCTLn)  15  X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 697: Table 25-66 Device Endpoint-N Control Register: Diepctln/Doepctln

    Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1. This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 698 Otherwise, a separate periodic FIFO must be allocated for an interrupt IN endpoint, and the number of this FIFO must be programmed into the TxFNum field. Configuring an interrupt IN endpoint as a non-periodic X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 699 IN endpoint, even if there data is available in the TxFIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 700 Endpoint Enable (EPEna) bit is low. This field is not valid in Slave mode operation. Note: This field is valid only for Shared FIFO operations. 10:0 Maximum Packet Size (MPS) 11'h0 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 701: Table 25-67 Device Endpoint-N Interrupt Register: Diepintn/Doepintn

    Core to process, such as Host busy or DMA done. Dependency: This bit is valid only when Scatter/Gather DMA mode is enabled. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 702 IN token was received. This interrupt is asserted on the endpoint for which the IN token was received. Status Phase Received For Control Write (StsPhseRcvd) This interrupt is X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 703 Applies to IN and OUT endpoints. This bit indicates that the endpoint is disabled per the application's request. Transfer Completed Interrupt (XferCompl) 1'b0 R_SS_WC X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 704: Table 25-68 Device In Endpoint 0 Transfer Size Register: Dieptsiz0

    The core decrements this field every time a packet from the external memory is written to the TxFIFO. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 705: Table 25-69 Device Out Endpoint 0 Transfer Size Register: Doeptsiz0

    USB. The core uses this field to calculate the data PID for isochronous IN endpoints.  2'b01: 1 packet  2'b10: 2 packets X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 706 RxFIFO and written to the external memory. Note: Note for Descriptor DMA The maximum transfer size supported is 219 bytes X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 707: Table 25-71 Device Endpoint-N Dma Address Register: Diepdman/Doepdman

    Holds the current buffer address.This register is updated as and when programmed the data transfer for the corresponding end point is in progress. as the X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 708: Operation Flow

    DMA Mode bit (applicable only when the OTG_ARCHITECTURE ❑ parameter is set to Internal/External DMA) AHB Burst Length field (applicable only when the OTG_ARCHITECTURE ❑ parameter is set to Internal/External DMA) X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 709: Programming The Device Core

    The application must meet the following conditions to set up the device core to handle traffic: In Slave mode, GINTMSK.NPTxFEmpMsk, and GINTMSK.RxFLvlMsk must be unset. ■ In DMA mode, the GINTMSK.NPTxFEmpMsk, and GINTMSK.RxFLvlMsk ■ interrupts must be masked. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 710 DAINTMSK.INEP0 = 1 (control 0 IN endpoint) ❑ DAINTMSK.OUTEP0 = 1 (control 0 OUT endpoint) ❑ DOEPMSK.SETUP = 1 ❑ DOEPMSK.XferCompl = 1 ❑ X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 711 SETUP packet. In Scatter/Gather DMA mode, the descriptors must be set up in memory before enabling the endpoint. DOEPCTL0.EPEna = 1 ❑ X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 712: Programming The Host Core

    OUT transaction or to be expected from the first IN transaction). Program the Transfer Size field so that the channel‘s transfer size is a multiple of X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 713 (GINTSTS.PrtInt) to the application. When GINTSTS.PrtInt is triggered, the application reads the HPRT register to check if the HPRT.Port Connect Detected (PrtConnDet) bit is set or not. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 714: Mac

     Full-duplex and half-duplex operation MDIO Master interface for PHY device configuration and management  remote wake-up frame and magic packet frame processing  X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 715: Section 8 Boot

    BOOT Section 8 BOOT X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 716: Xburst Boot Rom Specification

    XBurst Boot ROM Specification 27 XBurst Boot ROM Specification The X1000 contains an internal 16KB boot ROM. The CPU boots from the boot ROM after reset. 27.1 Boot Select The boot sequence of the X1000 is controlled by boot_sel [2:0]. The configuration is shown as follow:...

  • Page 717: Figure 27-1 Boot Sequence Diagram Of X1000

    XBurst Boot ROM Specification Figure 27-1 Boot sequence diagram of X1000 X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 718: Spl Structure

    256 bytes space of the MBR. When NAND boot, the parameters will be placed at the end of the SPL signature. SPL Parameters‘s location and structure show below: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 719: Table 27-2 Spl Parameters Structure

    The length of SPL in bytes, and must be 512 byte aligned. the size of SPL must be not more than 26K. CPU freq： Cpu frequency conversion value in HZ. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 720 Polling Value Addr(This is lower 16 bits address , th higher 16bit address is 0xb000). The configuration value of the ―saddr‖ register value: poll_h: Polling high bit mask(32bit). poll_l: Polling low bit mask(32bit). X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 721: Figure 27-4 Spl Configuration Change Procedure

    SUCCESS poll_h != 0 while(!(*paddr & poll_h)) poll_l != 0 while(*paddr & poll_l) cnt of desc == 14? Figure 27-4 SPL configuration change Procedure X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 722: Usb Boot Specification

    When boot_sel[2:0] is selected as USB boot, the internal boot ROM downloads user program from the USB port to internal SRAM and branches to the internal SRAM to execute the program. X1000 supports the external main crystal whose frequency is 24MHz. The boot program supports both high-speed (480MHz) and full-speed (12MHz) transfer modes. The boot program uses the following two transfer types.
  • Page 723 VR_PROGRAM_START2 (0x05). User program is transferred through Bulk IN or Bulk OUT endpoint. When X1000 is reset with boot_sel[2:0] equals 111b or 001b ,the internal boot ROM will switch to USB boot mode and wait for USB requests from host. After connecting the USB device port to host, host will recognize the connection of a USB device, and start device enumeration.

  • Page 724: Figure 27-6 Typical Procedure Of Usb Boot

    Send VR_FLUSH_CACHES to flush D caches Send VR_PROGRAM_START2 Figure 27-6 Typical Procedure of USB Boot Following tables list all the vendor requests that USB boot program supports: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 725: Table 27-4 Vendor Request 0 Setup Command Data Structure

    Table 27-7 Vendor Request 3 Setup Command Data Structure Offset Field Size Value Description bmRequestType D7 0: Host to Device. D6-D5 2: Vendor. D4-D0 0: Device. bRequest VR_FLUSH_CACHES: flush I-Cache and D-Cache. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 726: Msc0 Boot Specification

    MSC0_CLK, MSC0_CMD as function pins. Only one data pin MSC0_D0 is used. Then the boot program sends CMD55 to test if it‘s SD or MMC card and initializes the card. At last it loads 12KB code X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 727: Figure 27-7 Typical Procedure Of Msc0 Boot

    When initializing the card, the clock of EXTCLK/128 is used. And when reading data, the clock of EXTCLK/4 is used. The procedure of the X1000 MMC/SD boot is shown as follow: Init gpio MSC reset...

  • Page 728: Msc1 Boot Specification

    ―SFC Boot Procedure‖ Note: Any irregularity in boot steps, SPI_boot will disable SFC controller and jump to MSC1 boot. X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 729: Figure 27-9 X1000 Spi Boot Procedure

    16 bytes that agreed SPI boot flag. The SPI boot flag information table and procedure of the T10 SPI NOR boot is shown as follow: X1000 IoT Application Processor Programming Manual Copyright © 2005-2016 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 730: Table 27-10 Spi Nor Flash Boot Flag Informations(In Spl Signature)

    When SPI NAND flash by General-Purpose I/O Port-A 1,2,3,4 pin. Like spi nor flash, in spi NAND flash address 0x0~0xF, this space will store 16 bytes that agreed SPI_boot flag. The SPI_boot flag information table and procedure of the X1000 SPI NAND boot is shown as follow: Table 27-11 SPI NAND flash boot flag informations(in spl signature)

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