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XBurst®2 CPU Core
Programming Manual
Release Date: June 2, 2017

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Summary of Contents for Ingenic XBurst 2 CPU Core

  • Page 1 XBurst®2 CPU Core Programming Manual Release Date: June 2, 2017...
  • Page 2 Ingenic Terms and Conditions of Sale. Ingenic products are not designed for and should not be used in any medical or life sustaining or supporting equipment. All information in this document should be treated as preliminary. Ingenic may make changes to this document without notice.

  • Page 3: Table Of Contents

    Kernel Mode ........................65 TLB ............................67 5.3.1 Instruction Micro TLB ....................67 5.3.2 Data Micro TLB ......................67 5.3.3 Variable Page Size TLB (VTLB) ..................67 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 4 Mailbox Register<N> ..................... 93 8.2.17 CCU Spin Lock Register ....................94 8.2.18 CCU Spin Atomic Register ..................... 94 8.2.19 Global Interrupt Mask Register ..................95 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 5 Debug Instruction Break Exception ................133 9.10.7 Debug Breakpoint Exception ..................133 9.10.8 Debug Data Break on Load/Store Exception .............. 134 9.11 Debug Mode Exceptions ..................... 134 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 6 Debug Mode Address Space in ACC Mode (AM = 1) ..........139 9.13.7 Supported JTAG Instructions in ACC Mode ..............140 Revision History ................... 141 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 7: Overview

    Therefore, except explicitly claim, a core means a logic core in later chapters. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 8: Operating Modes

    User Mode Table 2-1 the conditions of operating mode Debug.DM Status.UM Status.EXL Status.ERL Operating Mode Debug Mode Kernel Mode User Mode X denotes don't care. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 10: Cp0

    3.3.2.1 Random section 3.3.2.2 EntryLo0 section 3.3.2.3 EntryLo1 section 3.3.2.3 EntryHi section 3.3.2.4 Context section 3.3.2.5 PageMask section 3.3.2.6 PageGrain section 3.3.2.7 Wired section 3.3.2.8 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 11 3.3.9.2 LLAddr section 3.3.9.3 Kernel Mode Support KScratch1 section 3.3.10.1 KScratch2 section 3.3.10.2 KScratch3 section 3.3.10.3 KScratch4 section 3.3.10.4 KScratch5 section 3.3.10.5 KScratch6 section 3.3.10.6 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 12: Cp0 Registers Grouped By Number

    3.3.1.1 Config1 Configuration for MMU, catches etc. section 3.3.1.2 Config2 Configuration for MMU ,caches etc. section 3.3.1.3 Config3 Interrupt and ASE capabilities. section 3.3.1.4 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 13 3.3.10.3 KScratch4 Kernel scratch pad register 4. section 3.3.10.4 KScratch5 Kernel scratch pad register 5. section 3.3.10.5 KScrathc6 Kernel scratch pad register 5. section 3.3.10.6 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 14: Cp0 Register Formats

    A field to which the write operation by software is update, and assumes a zero value. always ingored. And software reading of this field will return zero. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 15: Cp0 Register Descriptions

    Hardwired to 2’b00 which indicates that the architecture type is MIPS32. This field only denotes address and register width. The exact implemented instruction sets are denoted by the ISA XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 16 Virtual instruction cache. This field is hardwired to 1'b0 to indicate the instruction cache of XBurst2 CPU is not virtual. Kseg0 cache attributes. SeeTable 6-2 Cache Coherency Attributes for detail XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 17 : Reserved 12:10 : 32-byte line size : Reserved. L1 data cache associativity.This field is encoded as follows: : Reserved : 8-way Coprocessor 2 implemented: XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 18 If an FPU is implemented, further capabilities of the FPU can be read from the capability bits in the FIR register belonging to CP1 registers. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 19 0~4, 6, 7 : Reserved : 64-byte line size L2 cache associativity.This field is encoded as follows: : Reserved : 8-way 8~14 : Reserved : 16-way XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 20 Always read as zero as microMIPS is never implemented. 15:14 Indicates Instruction Set Availability. Always read as zero, indicating that MIPS32 is implemented ULRI UserLocal register implemented. 0: UserLocal register is not implemented; XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 21 SmartMIPS ASE implemented. Always read as zero, indicating that it is not implemented. Trace Logic implemented. Read as 0 to indicate Trace Logic is not implemented. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 22 FTLB entries must be flushed before this register field value being changed by software. Encoding Page Size 00000 Reserved 00001 00010 16KB 00011-11111 Reserved FTLB Indicate the set associativity of the FTLB array. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 23 0010 0011-1111 Reserved FTLB Indicates the number of sets per way within the FTLB array. Sets Encoding Set per Way 0000-0101 Reserved 0110 0111-1111 Reserved XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 24 1: MSA instructions and registers are enabled. 26:1 Must be written as zero; returns zero on read NFExist The nested fault feature does not exist. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 25 3 - TSMC28; 4 - SAMSUNM28; 5 - TSMC22; 6 - GF22; others - reserved version(3~0): internal version of different implementation. Please refer to SOC document. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 26 This field can also be read via RDHWR register 0. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 27 Must be written as zero; returns zero on read. Control the location of exception vectors. 0: Normal 1: Bootstrap See Exception Vector Locations for detail XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 28 Segment kuseg is treated as an unmapped and uncached region. Exception Level, can be set by hardware when any exception other than reset exception is taken or by executing MTC0 $12, 0. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 29 Note that IE being cleared just prohibit acknowledging interrupts by executing IRQ handler, it can't prevent some hardware behaviors like captured interrupt signals waking the core from SLEEP state. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 30 Encoding of IPTI, IPPCI Fields Encoding IP bit Hardware Interrupt Source HW0 (INTC IRQ) HW1 (SMP MAILBOX IRQ) HW2 (OST IRQ) HW3 (Reserved) HW4(IPPCI) HW5 (IPTI) XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 31: Tlb Management Registers

    Hardware writes this field with the index of the matching TLB entry after executing of the TLBP instruction. If the TLBP fails, the contents of this field are UNPREDICTABLE. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 32 Random Register Reserved Random Name Bits Description Reset Reserved 31:5 Must be written as zero; returns zero on read Random TLB Random Index 0x1f XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 33 EntryLo0 and EntryLo1 registers becomes the G bit to be filled in Entry0/Entry1 TLB entry. If the TLB entry G bit is a one, then the ASID comparisons are ignored during TLB matches. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 34 Address space identifier. This field is written by hardware on a TLBR operation, and can be written by software to set the current process' ASID. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 35 This field is written only by hardware on a TLB exception. It contains bits VA [31:13] of the virtual address that cause the exception. Reserved Must be written as zero; returns zero on read XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 36 00_0000_0000_0011: 16KB 00_0000_0000_1111: 64KB 00_0000_0011_1111: 256KB 00_0000_1111_1111: 1MB 00_0011_1111_1111: 4MB 00_1111_1111_1111: 16MB 11_1111_1111_1111: 64MB Reserved 12:0 Must be written as zero; returns zero on read XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 37 Must be written as zero; returns zero on read 12:8 Ignored on write; return zero on read. Reserved Must be written as zero; returns zero on read XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 38 Wired register. Wired Register Reserved Wired Name Bits Description Reset Reserved 31:5 Must be written as zero; returns zero on read Wired TLB wired boundary XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 39 The BadVAddr register does not capture address information for cache or bus errors. BadVAddr Register BadVAddr Name Bits Description Reset BadVAddr 31:0 Failed virtual address in Address Error or TLB exceptions. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 40: Exception Control Registers

    These bits are reserved because MCU ASE is not implemented, read as zero and write is ignored. Indicates whether an interrupt exception uses the general XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 41 Exc Code Exception code. See Table 3.4 Must be written as zero; returns zero on read Table 3-4 Cause Register ExcCode Field Descriptions Exception Mnemonic Description XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 42 Floating point exception. 16-20 TLBRI TLB Read-Inhibit exception TLBXI TLB Execution-Inhibit exception MSADis MSA Disabled exception WATCH Reference to WatchHi/WatchLo address. Mcheck Machine Check. 25-31 Reserved. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 43 Moreover, the register can be modified via the MTC0 instruction. Exception Program Counter Name Bits Description Reset 31:0 Exception Program Counter. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 44 Reset exception. All bits of the ErrorEPC register are significant and writable. ErrorEPC Register ErrorEPC Name Bits Description Reset ErrorEPC 31:0 Error Exception Program Counter. undef XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 45: Timer Registers

    Compare register is write-only. As a side effect, writing to this register clears the timer intrerrupt. Compare Register Compare Name Bits Description Reset Compare 31:0 Interval count compare value XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 46: Cache Management Registers

    CACHE instruction reads the corresponding data values into the DataLo register. DataLo Register DataLo Name Bits Description Reset DataLo 31:0 Low-order data read from cache. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 47: Thread Context And Shadow Control Registers

    31 30 29 26 25 22 21 18 17 16 15 12 11 10 9 6 5 4 3 SRSMap Name Bits Description Reset SRSMap 31:0 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 48: Cpu Performance Monitor Registers

    Counter Register. See following chapter “ Performance Counter Events and Codes”for detail. Performance Counter Interrupt Enable. 0: Performance counter interrupt disabled. 1: Performance counter interrupt enabled. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 49 Occurred Data Cache miss latency by store Occurred Data Cache miss event by store reserved Reserved Occurred Instruction Cache miss latency Occurred Instruction Cache miss event Others Reserved Reserved XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 50: Debug Registers

    0: not running in debug mode 1: running in debug mode NoDCR Indicates whether the dseg segment is present: Read as zero, indicating that dseg segment is present. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 51 Controls whether single-step feature is enabled: 0: No debug single-step exception enabled. 1: Debug single step exception enabled. OffLine MIPS MT processors is not implemented, this bit is XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 52 Read as zero as the feature is not implemented Read as zero as the feature is not implemented PaCO Read as zero as the feature is not implemented XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 53 DESAVE Register DESAVE Name Bits Description Reset DESAVE 31:0 Debug exception save contents. Undef XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 54 If this bit is set, watch exception is enabled for loads that match the address. If this bit is set, watch exception is enabled for stores that match the address. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 55 This bit can only be set by hardware when an store condition matches the values in the watch register pair. This bit can only be cleared by software writing a 1 to the bit. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 56: User Mode Support Registers

    SYNCI instruction. CPUNum CPUNum present. Setting 1 permits programs in user mode to obtain the CPU ID number of the core. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 57 Load Linked instruction. The format of this register is implementation dependent, and an implementation may implement as many of the bits or format the address in any way that it find convenient. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 58: Kernel Mode Scratch Registers

    The presence of the KScratch3 register is indicated by Config4 = 1. KScrExist[4] KScratch3 Register KScratch3 Name Bits Description Reset KScratch3 31:0 Used by the kernel for temporary storage of information. undef XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 59 The presence of the KScratch6 register is indicated by Config4 = 1. KScrExist[7] KScratch6 Register KScratch6 Name Bits Description Reset KScratch6 31:0 Used by the kernel for temporary storage of information. undef XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 60: Exceptions And Interrupts

    Load/Store TLB miss, or Load/Store hit page with V=0 or RI=1 TLB Modify Store hit page with D=0 DDBL/DDBS Debug Break on Load address + data match XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 61: Exception Vector Locations

    0xff200200 Status.BEV Status.EXL Cause.IV Base Offset TLB Refill EBase[31:12],12'b0 0x000 0x180 0xbfc00200 0x000 0x180 Interrupt EBase[31:12],12'b0 0x180 0x200+ 0xbfc00200 0x180 0x200 Others EBase[31:12],12'b0 0x180 0xbfc00200 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 62: Exception Handling Process

    Return from Exception Handler Routine Return from exception routine is performed by executing ERET instruction for non-debug exceptions or DERET instruction for debug/debug mode exceptions. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 63: Exception Categories

    An Read-Inhibit Exception occurs when the virtual address of a load reference Inhibit matches a TLB entry whose RI bit is set. In the case, the ExcCode of Cause should XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 64 A Trap Exception occurs when a trap instruction results in a TRUE condition. DDBL/ A Debug Data Break Load/Store Exception occurs when a preset hardware data DDBS breakpoint matches the address of an executed load/store instruction. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 65: Memory Management Unit

    8 kinds of page size. The access right to virtual address space can be set for privileged and user modes to provide memory protection. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 66: Virtual Memory Space

    The core operates in user mode when the DM bit in the Debug register is 0 and the Status register contains the following bit values:  UM = 1  EXL = 0  ERL = 0 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 67: Kernel Mode

    0x9FFF_FFFF. References to kseg0 are unmapped; the designate physical address for kseg0 is defined by subtracting 0x8000_0000 from the virtual address of kseg0. The K0 field of the Config register controls kseg0's cacheability. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 68 0xFFFF_FFFF. References to kseg3 need be combined with the ASID field of EntryHi register to form a unique virtual address for address mapping by TLB XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 69: Tlb

    VTLB implements the following variable page size schemes:  if "enable ftlb" & "ftlb page-size=4KB" , then VTLB supported page sizes include: 16KB, 64KB, 256KB, 1MB, 4MB, 16MB, 64MB XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 70 PageMask field. ASID Address Space Identifier Identifies which process this TLB entry is associated with. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 71 0: V0==0 means even-page is invalid; V1==0 means odd-page is invalid; 1: V0==1 means even-page is valid; V1==1 means odd-page is valid; accessing an invalid page should cause a TLB Invalid exception XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 72: Fixed Page Size Tlb (Ftlb)

    Please note that FTLB has the similar TLB tag entry format and TLB data entry format except PageMask field because its page size is fixed. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 73: Filling Jtlb Entry

    Config4.FTLBpagesize == 2, use EntryHi.VPN2[20:15] to access the FTLB set, read LRU status of total 4 ways, then choose a LRU way to overwrite it. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 74: Virtual To Physical Address Translation

    VPN field of the entry, and either G bit of the TLB entry is set or ASID field of the virtual address (held in the EntryHi register) matches the ASID field of the TLB entry. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 75: Caches

    Table 6-2 Cache Coherency Attributes Description Encoding Cacheable, write-through, write-allocate Uncacheable write accelerated Uncacheable Cacheable, Write-back, write-allocate Cacheable, Write-through, write-allocate, streaming Cacheable, Write-back, write-allocate, streaming Reserved Reserved XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 76: Cache Relative Cp0 Registers

    Cache instruction specifies the cache on which to perform the operation. – Level 1 I-Cache – Level 1 D-Cache – Reserved – Secondary Cache XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 77 Reserved Prefetch and If the virtual address misses cache, the line containing the address is lock fetched from memory. The lock function is not implemented. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 78 For index operation, software should use UNMAPPED address to avoid TLB exceptions. For non-index operation, the result is UNDEFINED if the virtual address is uncacheable. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 79: Pref/Prefx Instruction

    Moreover, if an address relative exception may occur, the exception will be ignored and no allocation will be done. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 80: Sync Instruction

    (may be caused by Load/Store instruction, CACHE instruction, PREF instruction, etc.) to complete before the execution of SYNC. In other words, SYNC instruction eliminates potential data coherency hazard in the memory hierarchy in a core. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 81: L2-Cache

    512/8, 256/16 (256KB), 1024/8, 512/16 (512KB), 2048/8, 1024/16 (1MB) Lookup policy physically indexed Physically tagged Replace policy round-robin Lock Others smart HW prefetcher provides powerful streaming performance XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 82: Initialize Core State

    (power-on reset, watchdog reset). 7.2 Initialized Core State by Software 7.2.1 General Purpose Registers Initialization All 31 integer general purpose registers need be initialized by software after reset. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 83: Ccu

     Mailbox IRQ supporting IPI mechanism  Flexible IRQ mask bits masking IRQ  Hardware spinlock mechanism for atomic access of CCU by multiple cores XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 84: Register Description

    Bus Exception Control Register 0x000FFFFF 0x1f00 OST: Operating System Timer N: Core Number: 0, 1, 2, 3..For instance, the core3's MBR has the address offset 0x100C. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 85: Cores Sleep Control Register

    If any one of these bits is a zero, SOC can't enter sleep mode even if all cores finish the execution of the WAIT instruction. CPM: Clock and Power Management XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 86: Core Sleep Status Register

    Later, when an interrupt need be taken by core<N>, CCU should clear the corresponding SS<N> bit and restore Core<N>'s clock. The following picture is the relationship between CCU's CSCR, CSSR and SOC CPM's sleep mode. Refer to the chapter about CPM of Ingenic SOC manual for more information. CSRR.SRE0 CSSR.SS0 CORE0 CSCR.SM0...

  • Page 87: Core Software Reset Register

    SRE<N> to 1. Furthermore, after setting SRE<N> to 1, setting SRE<N> to 0 will let the core get away from reset status. But the read-write property of SRE0 is controlled by CFCR. EnSRE0Wr. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 88: Memory Subsystem Control Register

    1: Disable L2 cache controller. After disabling L2 cache controller, it seems that all memory access between CPU and external bus occuring normally except L2-cache disappeared. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 89: Memory Subsystem Implementation Register

    15:8 ProcessorID The same meaning as the field of PRID register 0x20 Revision Specifies the revision number of the memory subsystem including CCX and L2C. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 90: Cpu Configuration Register

    In the SMT system, the value means the total amount of the logic core. For examples, if a SMT system has 2 physical cores/4 threads, the value should be 3. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 91: Peripheral Irq Pending Register

    0: pending periperal IRQ can not enter its corresponding core 1: pending periperal IRQ can enter its corresponding core (GIMR IM<N> should be set 1 first, GIMR is described in later chapter) XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 92: Mailbox Irq Pending Register

    0: pending Mailbox IRQ can not enter its corresponding core 1: pending Mailbox IRQ can enter its corresponding core(GIMR IM<N> should be 1 first, GIMR is described in later chapter) XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 93: Ost Irq Pending Register

    0: pending OST IRQ can not enter its corresponding core 1: pending OST IRQ can enter its corresponding core (GIMR IM<N> should be 1 first, GIMR is described in later chapter) XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 94: Debug Interrupt Pending Register

    External Debug Interrupt Mask of core<N>. Every bit controls the enabling of the corresponding core<N>'s Debug interrupt request which comes directly from EJTAG. 0: debug interrupt disabled 1: debug interrupt enabled XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 95: Reset Entry Register

    Rst 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bits Name Description 31:0 Message to Core<N>. The nonzero value is available for use as software flags or parameters. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 96: Ccu Spin Lock Register

    When the CSLR.Lock is zero writing this filed by software is available, the current value to be written into CSAR.Value will be replicated into CSLR.Value by hardware automatically as well as setting CSLR.Lock to 1. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 97: Global Interrupt Mask Register

    0: Any IRQ can not enter its corresponding core; 1: Whether an IRQ can enter its corresponding core or not is determined by its local mask register (eg. PIMR/MIMR/OIMR) XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 98: Cpu Feature Configuration Register

    Note: the default value for each configuration field is the best one for normal chip configuration, DO NOT modify them except for special purpose (like performance diagnosis). XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 99: Bus Exception Control Register

    BusCnt as its inital value and then will decrease 1 per cycle until counting to 0 or bus becoming idle again before counting to 0. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 100: Usage

    (Cp0 Register 15， Select1). The function ccu_read() can load a value from the specified CCU register. The function ccu_write() can store a value into the specified CCU register. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 101: Ejtag Debug Support

    Software Breakpoint: The instruction “SDBBP” which causes a debug exception on execution. Debuggers will temporarily replace an instruction of your program with this instruction on setting a breakpoint in writeable memory. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 102: Detecting Debug Mode

    The term "hardware" is not applied to breakpoint, unless required to distinguish it from software breakpoint. In the XBurst2 core, there are two instruction breakpoints and two data breakpoints. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 103: Instruction Breakpoints

    Table 9-2 Overview of Registers for Each Data Breakpoint Register Mnemonic Register Name and Description Data Breakpoint Status XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 104: Conditions For Matching Breakpoints

    The registers for each data breakpoint contain the value and mask used in the compare, and the equation that determines the match is shown below in C-like notation. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 105: Simd Load/Store Handling

    9.7 Debug Exceptions from Breakpoints This section describes how to set up instruction and data breakpoints to generate debug exceptions when the match conditions are true. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 106: Debug Exception By Instruction Breakpoint

    ) interface which is TRST_N compatible with IEEE Std. 1149.1. • Target chip and EJTAG feature identification available through the Test Access Port (TAP) controller. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 107: Ejtag Internal And External Interfaces

    Instruction Register scan or Data Register scan is performed. The TAP consists of a small controller, driven by the input, which responds to the input as shown XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 108 Exit1 and Update states or enters the Pause state via Exit1. The reason for entering the Pause state is to temporarily suspend the shifting of data through either the Data or Instruction Register while a XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 109 Exit1_DR state. The instruction cannot change while the TAP controller is in this state. 9.8.2.6 Shift_DR State In this state the test data register connected between as a result of the current instruction XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 110 , the controller transitions to the Shift_IR state. A HIGH on causes the controller to transition to the Exit1_IR state. The instruction cannot change while the TAP controller is in this state. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 111: Test Access Port (Tap) Instructions

    Table 9-4 Implemented EJTAG Instructions Value Instruction Function 0x01 IDCODE Select Chip Identification data register 0x03 IMPCODE Select Implementation register 0x08 ADDRESS Select Address register XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 112 . It can be used in particular to minimize the overhead in switching the instruction in the instruction register. The first bit shifted out is bit 0 of the ECR. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 113: Tap Processor Accesses

    When a debug exception is taken, while the ProbTrap bit is set, the processor will start fetching instructions from address 0xFF20.0200. A pending processor access can only finish if the probe writes 0 to PrAcc or by a reset. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 114 10. The processor detects that PrAcc bit = 0, which means that it is ready to handle a new access. The above examples imply that no reset occurs during the operations, and that Rocc is cleared. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 115: Ejtag Registers

    1: Big endian 28:18 Must be written as zero; returns zero on read. DataBrk Indicates if data hardware breakpoint is implemented: 0: No data hardware breakpoint implemented XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 116: Instruction Breakpoint Registers

    Register Name and Description Mnemonic 0x1000 Instruction Breakpoint Status 0x1100 + n*0x100 IBAn Instruction Breakpoint Address n 0x1108 + n*0x100 IBMn Instruction Breakpoint Address Mask n XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 117 Bits not implemented are read-only (R) and read as zeros. Must be written as zero; returns zero on read. 29:28, 23:2 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 118 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 119: Data Breakpoint Registers

    All registers are in drseg, and the addresses are shown in below. n is breakpoint number in range 0 to 1. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 120 Indicates if a value compare on a load is supported in data breakpoints: 0: data value and address in condition on load. 1: address compare only in condition on load. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 121 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 122 Reset ASIDuse Use ASID value in compare for data breakpoint n: 0: do note use ASID value in compare. 1: Use ASID value in compare. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 123 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 124: Ejtag Tap Registers

    9.9.4.2 Data Registers Overview The EJTAG uses several data registers that are arranged in parallel from the primary input to the XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 125 This field identifies the version number of the processor derivative. PartNumb 27:12 Part Number (16 bits) This field identifies the part number of the processor XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 126 ASIDsize 22:21 Indicates size of the ASID field: 0: No ASID in implementation 1: 6-bit ASID 2: 8-bit ASID 3: Reserved XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 127 The bit indicates if a CPU reset has occurred: The Rocc bit will remain set to 1 as long as reset is applied. This bit must be cleared by the probe to acknowledge XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 128 1: Internal system clock is stopped PerRst Peripheral reset This bit has no effect. PrnW Processor Access Read and Write Undefined This bit indicates if the pending processor access is XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 129 Probe does handle EJTAG memory transactions 1: Probe does handle EJTAG memory transactions It is an error by the software controlling the probe if it XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 130 CPU was in low power mode. This bit is cleared by hardware when the debug exception is taken. The reset value of the bit depends on whether the XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 131 Data register read, 0(zero) must be shifted in for the unused bytes. The bytes in the Data Register are organized in little-endian. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 132: Debug Exception

    Debug Interrupt; from EJTAG TAP. Machine Check Non-Debug Interrupt Deferred Watch Debug Instruction Break Debug Watch on Instruction Fetch Non-Debug Address Error on Instruction Fetch XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 133: Debug Exception Vector Location

    Debug software need only look at the DBD bit in the Debug register to identify the address of the instruction that actually caused a precise debug exception. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 134: Debug Single Step Exception

    Debug Single Step exception is only possible when the NoSSt bit in the Debug register is 0. Debug Register Debug Status Bit Set XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 135: Debug Interrupt Exception

    DEPC register and the DBD bit in the Debug register indicate that the SDBBP instruction caused the debug exception. Debug Register Debug Status Bit Set XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 136: Debug Data Break On Load/Store Exception

    Table 9-27 Exception Handling in Debug Mode Priority Exception Type of Exception Highest Reset Handled Non-Debug Mode Debug Single Step Blocked Debug Interrupt; from EJTAG TAP. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 137: Debug Mode Exception Processing

    The value loaded into the DEPC register represents the restart address for the exception; typically debug software does not need to modify this value at the location of the debug exception. Debug XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 138: Mips Ejtag Compliant Mode

    It is connected between TDI and TDO by instruction CONTROL or ALL in ACC mode. Probe polls this 2-bit register to service the processor access to dmseg region. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 139 Processor Access (PA) 0: No pending processor access 1: Pending processor access Processor access is read or write Undefined 0: read access 1: write access XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 140: Processor Access Address Register In Acc Mode (Address_A)

    Pipeline lock label. Undefined 1- processor can proceed due to processor access to dmseg done 0- processor should be locked due to unfinished processor access to dmseg XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 141: Debug Mode Address Space In Compliant Mode (Am = 0)

    Dmseg (12M) 0xFFFF_FFFF 0xFFFF_FFFF (512M) NOTE: Dseg is always unmapped in debug mode in spite of attribute of Kseg3. Kuseg(2G) Extended Dseg space in ACC mode XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 142: Supported Jtag Instructions In Acc Mode

    Boot from probe host in ACC mode by setting ECREjtagbrk, EJTAGBOOTA ECRProbEn, ECRProbTrap and AM when reset. Bypass register is selected. 0x1F BYPASS Select Bypass register. XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 143: Revision History

    Auguest 30, 2018  Part of CCU  00.10 April 20, 2020 Remove sophisticated efficentless EJTAG debug mechanism for SMP system  Some syntax error fixed XBurst®2 CPU Core Programming Manual Copyright © 2005-2020 Ingenic Semiconductor Co., Ltd. All rights reserved.

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