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Ingenic JZ4775 Design Manual

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Ingenic
JZ4775
Board Design Guide
Revision: 1.1
Date: Sept. 2013

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Summary of Contents for Ingenic JZ4775

  • Page 1 ® Ingenic JZ4775 Board Design Guide Revision: 1.1 Date: Sept. 2013...
  • Page 3 Ingenic Terms and Conditions of Sale. Ingenic products are not designed for and should not be used in any medical or life sustaining or supporting equipment. All information in this document should be treated as preliminary. Ingenic may make changes to this document without notice.

  • Page 5: Table Of Contents

    USB Power ........................ 19 OTG Overview ........................19 6.2.1 OTG Power ....................... 19 Guidelines for the USB and OTG interface ................ 20 7 LCD ....................23 Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 6 JTAG/Debug Port ......................36 15 Platform Clock Guidelines ..............38 16 Platform Power Guidelines ..............39 16.1 Overview .......................... 39 16.2 Power Delivery and Decoupling ..................39 Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 7: Overview

    Overview Overview JZ4775 is a mobile application processor targeting for multimedia rich and mobile devices like tablet computer, EBook, mobile digital TV. This SOC introduces a kind of innovative architecture to fulfill both high performance mobile computing and high quality video decoding requirements addressed by mobile multimedia devices.

  • Page 8: Reference Platform

    Overview INGENIC. They should be used as an example, but may not be applicable to particular designs. Note: In this manual, processor means the JZ4775 processor if not specified. The guidelines recommended in this manual are based on experience and simulation work completed by INGENIC while developing systems with JZ4775.

  • Page 9: Platform Stack-Up And Placement

    Figure 2-1. Nominal 6-Layer Board Stack-Up The JZ4775 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%. Recommendations in this design guide are based on the following a 6-layer board stack-up:...

  • Page 10: Pcb Technology Considerations

    1.0 mils From top of trace PCB Technology Considerations The following recommendation aids in the design of a JZ4775 based platform. Simulations and reference platform are based on the following technology, and we recommend that designers adhere to these guidelines.

  • Page 11: 4-Layer Board Stack-Up

    1. The Cu Thickness is just a reference value. It is calculated by the PCB board producers for impedance matching. 4-Layer Board Stack-Up The JZ4775 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%. If a 4-layer board is used, the stack-up should be: Signal...

  • Page 12: 8-Layer Hdi Board Stack-Up

    Platform Stack-Up and Placement 8-Layer HDI Board Stack-Up The JZ4775 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%. If a 8-layer HDI board is used, the stack-up should be: Placement Layer 1 Prepreg...

  • Page 13: Static Memory Interface Design Guidelines

    @ MSC0 (use GPIO Port A) NAND boot @ CS1 SPI boot @ SPI0/CE0 USB boot (USB 2.0 device, EXTCLK=26MHz) NOR boot @ CS4 (just for FPGA testing) Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 14: Nand Flash Connection

    16-bit NAND Flash Interconnection Example JZ4775 NAND Flash CS[n]# FRE# FWE# FRB# R/B# NDQS SD [8:0] I/O [8:0] Figure 3-2 8-bit Toggle NAND Flash Interconnection Example Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 15: Ddr3 Sdram

    RAS# CAS# CK, CK# RESET# DQ [31:16] DQ [15:0] DQS2, DQS2_N LDQS, LDQS# DQS3, DQS3_N UDQS, UDQS# Figure 4-1 Two 16-bit DDR3 Interconnection Example Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 16: Connection To Four 1Gb X 8 Ddr3 Sdram Device

    DQS/DQS# signals are within ¼ of a clock period of the rising edge of the differential clock, CK/CK#. 4) Route all Vref and support signals (JTAG etc. if implemented) Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 17 This will interrupt the return currents that flow beneath the conductor and can lead to crosstalk with neighboring traces. This will also increase emissions from the board. Figure 4-3 GND Joined Together Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 18 Using many capacitors, rather than a large one, will reduce the inductance. The inductance of a capacitor is dependent on its size. The capacitor Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 19 +1.5V power plane should cover the entire keep out region.  Bypassing capacitors should be close to the devices, or positioned for the shortest connections to pins, with wide traces to reduce impedance. Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 20: Audio Codec Design Guidelines

    The ESD1 and ESD3 is an ESD transient voltage suppression component which provides a very high level of protection for sensitive electronic components that may be subjected to electrostatic Board Design Guide for JZ4775, Revision 1.0 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 21: Mic In

    SB_MICBIAS to 1 will close MICBIAS stage and the MICBIAS output voltage will be zero. MICBIAS output voltage scales with AVDCDC, equals to 5/6*AVDCDC (typical 2.08V). MICBIAS output current is 4mA max. Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 22: Speaker

    The device provides protection for contact discharges to greater than +/-15KV. Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 23: Layout Guideline

    EMI emissions and degrading the analog and digital signal quality.  Analog power and signal traces should be routed over the analog ground plane. Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 24 Regions between digital signal traces should be filled with copper, which should be electrically attached to the digital ground plane. Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 25: Usb And Otg Design Guidelines

    An OTG device can plays the role of both host and device. JZ4775 also integrates USB 2.0 OTG interface, which compliant with USB protocol Revision 2.0 OTG. It supports low-speed (1.5 Mbps), full-speed (12 Mbps) and high speed (480 Mbps). Operates either as the function controller of a high-/full-speed USB peripheral or as the host/peripheral in point-to-point or multi-point communications with other USB functions.

  • Page 26: Guidelines For The Usb And Otg Interface

    Guidelines for the USB and OTG interface  Unused USB ports should be terminated with 15 k pull-down resistors on both DP1/DM1 data lines. Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 27  47-pF caps must be placed as close as possible to the JZ4775 as well as on the processor side of the series resistors on the USB data lines (DP1, DM1). These caps are for signal quality (rise/fall time) and to help minimize EMI radiation.
  • Page 28 Motherboard Trace Driver 45  90  Driver Motherboard Trace 45  JZ4775 Transmission Line USB Twisted-pair Cable Figure 6-3 Recommend USB OTG Schematic Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 29: Lcd

    The JZ4775 integrated LCD controller has the capabilities to driving the latest TFT LCD panels. It also supports some special TFT panels used in consuming electronic products. The controller performs the basic memory based frame buffer and palette buffer to LCD panel data transfer through use of a dedicated DMA controller.
  • Page 30 Lcd_dat9 0 (NC for panel) Lcd_dat8 Lcd_dat7 Lcd_dat6 Lcd_dat5 Lcd_dat4 Lcd_dat3 Lcd_dat2 Lcd_dat1 Lcd_dat0 0 (NC for panel) Lcd_lo6_o[5] Lcd_lo6_o[4] Lcd_lo6_o[3] Lcd_lo6_o[2] Lcd_lo6_o[1] Lcd_lo6_o[0] Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 31 Lcd_dat5/Slcd_dat5 lcd_b7 Lcd_dat4/Slcd_dat4 lcd_b6 Lcd_dat3/Slcd_dat3 lcd_b5 Lcd_dat2/Slcd_dat2 lcd_b4 Lcd_dat1/Slcd_dat1 lcd_b3 Lcd_dat0/Slcd_dat0 lcd_b2 Lcd_lo6_o[5] lcd_r1 Lcd_lo6_o[4] lcd_r0 Lcd_lo6_o[3] lcd_g1 Lcd_lo6_o[2] lcd_g0 Lcd_lo6_o[1] lcd_b1 Lcd_lo6_o[0] lcd_b0 Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 32: Epd

    Overview The JZ4775 integrated EPD controller. The controller provides a low cost SOC solution for EPD applications. Features:  Supports PVI and AUO compatible EPD panels  Supports different size up to 4096x4096@20Hz  Supports 2/3/4 bits grayscale and color display ...

  • Page 33: Camera

    Camera Overview The CIM (Camera Interface Module) of JZ4775 connects to a CMOS or CCD type image sensor. The CIM source the digital image stream through a common 8-bit parallel common digital protocol. The CIM can directly connect to external CMOS image sensors and ITU656 standard video decoders.

  • Page 34: Sar A/D Controller

    10.2 Touch Screen The JZ4775 can support 5-wire resistive touch screen. There is needed a decouple capacitor for every channel to avoid the crosstalk from LCD. The value is decided by the touch screen and can be from 100pF to 1000pF.

  • Page 35: Battery Voltage Measurement

    Users who already deployed divider resistors on board level can use VBAT to direct measure the battery value. The following figure is the approach we recommend. Use the recommended resistance; you can control the power consumption easier. Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 36: Otp Efuse

    Maximum accumulative time for AVDEFUSE pin exposed under 2.5V+/-10% should be less than 1 sec. In read mode, leave AVDEFUSE to 0V. Board Design Guide for JZ4775, Revision 1.0 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 37: Ethernet Design Guidelines

    Ethernet Design Guidelines Ethernet Design Guidelines 12.1 Overview As the JZ4775 processor supports 10, 100 or 1000Mbps configuration 、 MII、 RMII、 GMII and RGMII PHY interfaces. 12.2 JZ4775 Ethernet Controller Connection JZ4775 connection example is shown as figure 11-1. TX_ER...

  • Page 38: Rtc

    PWRON directly. The resistance of R115 in the next figure is recommended to be ohm; in this case, you can consume less current when power down mode. Board Design Guide for JZ4775, Revision 1.0 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.
  • Page 39 +3.3V RESET CIRCUITS VRTC18 R112 RST_N 200k R113 PPRST_N SW11 R114 0 R115 Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 40: Miscellaneous Peripheral Design Guidelines

    The following figures show the connection example: JZ4775 Microwire Device SSI_CE# SSI_DR SSI_DT SSI_CLK Figure 14-1 Microwire Interconnection JZ4775 SSP Device SSI_CE# SSI_DR SSI_DT SSI_CLK SCLK Figure 14-2 SSP Interconnection Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 41: Uart

    14.2 UART The JZ4775 processor has four UARTs: All UARTs use the same programming model. Each of the serial ports can operate in interrupt based mode or DMA-based mode. The Universal asynchronous receiver/transmitter (UART) is compatible with the 16550 industry standard and can be used as slow infrared asynchronous interface that conforms to the Infrared Data Association (IrDA) serial infrared specification 1.1.0...

  • Page 42: Smb Bus

    The period comparator causes the output pin to be set and the free-running counter to reset when it matches the period value. The width comparator causes the output pin to reset when the counter value matches. JZ4775 contains eight pulse width modulators: PWM0 ~ PWM3.
  • Page 43 Miscellaneous Peripheral Design Guidelines JDI & Uart Con +3.3V TDO_TXD UART3_TXD R177 CPU_TDO R178 TRST_N TDI_RXD UART3_RXD R179 CPU_TDI CPU_TDI R180 CPU_TDO CPU_TMS CPU_TCK RST_N UART3_RXD UART3_TXD Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

  • Page 44: Platform Clock Guidelines

    Platform Clock Guidelines Platform Clock Guidelines The JZ4775 processor contains two PLL driven by the 24-MHz oscillator and a clock generator from which the following are derived:  CPU clock  System bus clock  Peripheral bus clock  DDR bus clock ...

  • Page 45: Platform Power Guidelines

    Platform Power Guidelines 16.1 Overview The JZ4775 processor needs four voltages: +3.3V, +1.5V for memory, +1.2V for core, +2.5V for USB OTG and HDMI. The following figure is a typical power circuit in the tablet and smart phone application. The +1.2V need a power chip which can supply at least 1A, 1.2A is recommended.
  • Page 46 The power of RTC should be as the following circuit. The capacitors should be placed near the Pin of power. The traces from capacitor to the Pin should be short and width. VRTC18 0.1uF Board Design Guide for JZ4775, Revision 1.1 Copyright® 2005-2013 Ingenic Semiconductor Co., Ltd. All rights reserved.

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